fdt.c 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <clock_legacy.h>
  7. #include <net.h>
  8. #include <linux/libfdt.h>
  9. #include <fdt_support.h>
  10. #include <asm/io.h>
  11. #include <asm/processor.h>
  12. #include <asm/arch/clock.h>
  13. #include <linux/ctype.h>
  14. #ifdef CONFIG_FSL_ESDHC
  15. #include <fsl_esdhc.h>
  16. #endif
  17. #include <tsec.h>
  18. #include <asm/arch/immap_ls102xa.h>
  19. #include <fsl_sec.h>
  20. #include <dm.h>
  21. DECLARE_GLOBAL_DATA_PTR;
  22. void ft_fixup_enet_phy_connect_type(void *fdt)
  23. {
  24. #ifdef CONFIG_DM_ETH
  25. struct udevice *dev;
  26. #else
  27. struct eth_device *dev;
  28. #endif
  29. struct tsec_private *priv;
  30. const char *enet_path, *phy_path;
  31. char enet[16];
  32. char phy[16];
  33. int phy_node;
  34. int i = 0;
  35. uint32_t ph;
  36. #ifdef CONFIG_DM_ETH
  37. char *name[3] = { "ethernet@2d10000", "ethernet@2d50000",
  38. "ethernet@2d90000" };
  39. #else
  40. char *name[3] = { "eTSEC1", "eTSEC2", "eTSEC3" };
  41. #endif
  42. for (; i < ARRAY_SIZE(name); i++) {
  43. dev = eth_get_dev_by_name(name[i]);
  44. if (dev) {
  45. sprintf(enet, "ethernet%d", i);
  46. sprintf(phy, "enet%d_rgmii_phy", i);
  47. } else {
  48. continue;
  49. }
  50. priv = dev->priv;
  51. if (priv->flags & TSEC_SGMII)
  52. continue;
  53. enet_path = fdt_get_alias(fdt, enet);
  54. if (!enet_path)
  55. continue;
  56. phy_path = fdt_get_alias(fdt, phy);
  57. if (!phy_path)
  58. continue;
  59. phy_node = fdt_path_offset(fdt, phy_path);
  60. if (phy_node < 0)
  61. continue;
  62. ph = fdt_create_phandle(fdt, phy_node);
  63. if (ph)
  64. do_fixup_by_path_u32(fdt, enet_path,
  65. "phy-handle", ph, 1);
  66. do_fixup_by_path(fdt, enet_path, "phy-connection-type",
  67. phy_string_for_interface(
  68. PHY_INTERFACE_MODE_RGMII_ID),
  69. strlen(phy_string_for_interface(
  70. PHY_INTERFACE_MODE_RGMII_ID)) + 1,
  71. 1);
  72. }
  73. }
  74. void ft_cpu_setup(void *blob, struct bd_info *bd)
  75. {
  76. int off;
  77. int val;
  78. const char *sysclk_path;
  79. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  80. unsigned int svr;
  81. svr = in_be32(&gur->svr);
  82. unsigned long busclk = get_bus_freq(0);
  83. /* delete crypto node if not on an E-processor */
  84. if (!IS_E_PROCESSOR(svr))
  85. fdt_fixup_crypto_node(blob, 0);
  86. #if CONFIG_SYS_FSL_SEC_COMPAT >= 4
  87. else {
  88. ccsr_sec_t __iomem *sec;
  89. sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR;
  90. fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms));
  91. }
  92. #endif
  93. off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4);
  94. while (off != -FDT_ERR_NOTFOUND) {
  95. val = gd->cpu_clk;
  96. fdt_setprop(blob, off, "clock-frequency", &val, 4);
  97. off = fdt_node_offset_by_prop_value(blob, off,
  98. "device_type", "cpu", 4);
  99. }
  100. do_fixup_by_prop_u32(blob, "device_type", "soc",
  101. 4, "bus-frequency", busclk, 1);
  102. ft_fixup_enet_phy_connect_type(blob);
  103. #ifdef CONFIG_SYS_NS16550
  104. do_fixup_by_compat_u32(blob, "fsl,16550-FIFO64",
  105. "clock-frequency", CONFIG_SYS_NS16550_CLK, 1);
  106. #endif
  107. sysclk_path = fdt_get_alias(blob, "sysclk");
  108. if (sysclk_path)
  109. do_fixup_by_path_u32(blob, sysclk_path, "clock-frequency",
  110. CONFIG_SYS_CLK_FREQ, 1);
  111. do_fixup_by_compat_u32(blob, "fsl,qoriq-sysclk-2.0",
  112. "clock-frequency", CONFIG_SYS_CLK_FREQ, 1);
  113. #if defined(CONFIG_DEEP_SLEEP) && defined(CONFIG_SD_BOOT)
  114. #define UBOOT_HEAD_LEN 0x1000
  115. /*
  116. * Reserved memory in SD boot deep sleep case.
  117. * Second stage uboot binary and malloc space should be reserved.
  118. * If the memory they occupied has not been reserved, then this
  119. * space would be used by kernel and overwritten in uboot when
  120. * deep sleep resume, which cause deep sleep failed.
  121. * Since second uboot binary has a head, that space need to be
  122. * reserved either(assuming its size is less than 0x1000).
  123. */
  124. off = fdt_add_mem_rsv(blob, CONFIG_SYS_TEXT_BASE - UBOOT_HEAD_LEN,
  125. CONFIG_SYS_MONITOR_LEN + CONFIG_SYS_SPL_MALLOC_SIZE +
  126. UBOOT_HEAD_LEN);
  127. if (off < 0)
  128. printf("Failed to reserve memory for SD boot deep sleep: %s\n",
  129. fdt_strerror(off));
  130. #endif
  131. #if defined(CONFIG_FSL_ESDHC)
  132. fdt_fixup_esdhc(blob, bd);
  133. #endif
  134. /*
  135. * platform bus clock = system bus clock/2
  136. * Here busclk = system bus clock
  137. * We are using the platform bus clock as 1588 Timer reference
  138. * clock source select
  139. */
  140. do_fixup_by_compat_u32(blob, "fsl, gianfar-ptp-timer",
  141. "timer-frequency", busclk / 2, 1);
  142. /*
  143. * clock-freq should change to clock-frequency and
  144. * flexcan-v1.0 should change to p1010-flexcan respectively
  145. * in the future.
  146. */
  147. do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
  148. "clock_freq", busclk / 2, 1);
  149. do_fixup_by_compat_u32(blob, "fsl, flexcan-v1.0",
  150. "clock-frequency", busclk / 2, 1);
  151. do_fixup_by_compat_u32(blob, "fsl, ls1021a-flexcan",
  152. "clock-frequency", busclk / 2, 1);
  153. #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI)
  154. off = fdt_node_offset_by_compat_reg(blob, FSL_IFC_COMPAT,
  155. CONFIG_SYS_IFC_ADDR);
  156. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  157. #else
  158. off = fdt_node_offset_by_compat_reg(blob, FSL_QSPI_COMPAT,
  159. QSPI0_BASE_ADDR);
  160. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  161. off = fdt_node_offset_by_compat_reg(blob, FSL_DSPI_COMPAT,
  162. DSPI1_BASE_ADDR);
  163. fdt_set_node_status(blob, off, FDT_STATUS_DISABLED, 0);
  164. #endif
  165. }