cpu.c 9.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2014 Freescale Semiconductor, Inc.
  4. */
  5. #include <common.h>
  6. #include <cpu_func.h>
  7. #include <init.h>
  8. #include <net.h>
  9. #include <vsprintf.h>
  10. #include <asm/arch/clock.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/immap_ls102xa.h>
  13. #include <asm/cache.h>
  14. #include <asm/system.h>
  15. #include <tsec.h>
  16. #include <netdev.h>
  17. #include <fsl_esdhc.h>
  18. #include <config.h>
  19. #include <fsl_wdog.h>
  20. #include <linux/delay.h>
  21. #include "fsl_epu.h"
  22. #define DCSR_RCPM2_BLOCK_OFFSET 0x223000
  23. #define DCSR_RCPM2_CPMFSMCR0 0x400
  24. #define DCSR_RCPM2_CPMFSMSR0 0x404
  25. #define DCSR_RCPM2_CPMFSMCR1 0x414
  26. #define DCSR_RCPM2_CPMFSMSR1 0x418
  27. #define CPMFSMSR_FSM_STATE_MASK 0x7f
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF)
  30. /*
  31. * Bit[1] of the descriptor indicates the descriptor type,
  32. * and bit[0] indicates whether the descriptor is valid.
  33. */
  34. #define PMD_TYPE_TABLE 0x3
  35. #define PMD_TYPE_SECT 0x1
  36. /* AttrIndx[2:0] */
  37. #define PMD_ATTRINDX(t) ((t) << 2)
  38. /* Section */
  39. #define PMD_SECT_AF (1 << 10)
  40. #define BLOCK_SIZE_L1 (1UL << 30)
  41. #define BLOCK_SIZE_L2 (1UL << 21)
  42. /* TTBCR flags */
  43. #define TTBCR_EAE (1 << 31)
  44. #define TTBCR_T0SZ(x) ((x) << 0)
  45. #define TTBCR_T1SZ(x) ((x) << 16)
  46. #define TTBCR_USING_TTBR0 (TTBCR_T0SZ(0) | TTBCR_T1SZ(0))
  47. #define TTBCR_IRGN0_NC (0 << 8)
  48. #define TTBCR_IRGN0_WBWA (1 << 8)
  49. #define TTBCR_IRGN0_WT (2 << 8)
  50. #define TTBCR_IRGN0_WBNWA (3 << 8)
  51. #define TTBCR_IRGN0_MASK (3 << 8)
  52. #define TTBCR_ORGN0_NC (0 << 10)
  53. #define TTBCR_ORGN0_WBWA (1 << 10)
  54. #define TTBCR_ORGN0_WT (2 << 10)
  55. #define TTBCR_ORGN0_WBNWA (3 << 10)
  56. #define TTBCR_ORGN0_MASK (3 << 10)
  57. #define TTBCR_SHARED_NON (0 << 12)
  58. #define TTBCR_SHARED_OUTER (2 << 12)
  59. #define TTBCR_SHARED_INNER (3 << 12)
  60. #define TTBCR_EPD0 (0 << 7)
  61. #define TTBCR (TTBCR_SHARED_NON | \
  62. TTBCR_ORGN0_NC | \
  63. TTBCR_IRGN0_NC | \
  64. TTBCR_USING_TTBR0 | \
  65. TTBCR_EAE)
  66. /*
  67. * Memory region attributes for LPAE (defined in pgtable):
  68. *
  69. * n = AttrIndx[2:0]
  70. *
  71. * n MAIR
  72. * UNCACHED 000 00000000
  73. * BUFFERABLE 001 01000100
  74. * DEV_WC 001 01000100
  75. * WRITETHROUGH 010 10101010
  76. * WRITEBACK 011 11101110
  77. * DEV_CACHED 011 11101110
  78. * DEV_SHARED 100 00000100
  79. * DEV_NONSHARED 100 00000100
  80. * unused 101
  81. * unused 110
  82. * WRITEALLOC 111 11111111
  83. */
  84. #define MT_MAIR0 0xeeaa4400
  85. #define MT_MAIR1 0xff000004
  86. #define MT_STRONLY_ORDER 0
  87. #define MT_NORMAL_NC 1
  88. #define MT_DEVICE_MEM 4
  89. #define MT_NORMAL 7
  90. /* The phy_addr must be aligned to 4KB */
  91. static inline void set_pgtable(u32 *page_table, u32 index, u32 phy_addr)
  92. {
  93. u32 value = phy_addr | PMD_TYPE_TABLE;
  94. page_table[2 * index] = value;
  95. page_table[2 * index + 1] = 0;
  96. }
  97. /* The phy_addr must be aligned to 4KB */
  98. static inline void set_pgsection(u32 *page_table, u32 index, u64 phy_addr,
  99. u32 memory_type)
  100. {
  101. u64 value;
  102. value = phy_addr | PMD_TYPE_SECT | PMD_SECT_AF;
  103. value |= PMD_ATTRINDX(memory_type);
  104. page_table[2 * index] = value & 0xFFFFFFFF;
  105. page_table[2 * index + 1] = (value >> 32) & 0xFFFFFFFF;
  106. }
  107. /*
  108. * Start MMU after DDR is available, we create MMU table in DRAM.
  109. * The base address of TTLB is gd->arch.tlb_addr. We use two
  110. * levels of translation tables here to cover 40-bit address space.
  111. *
  112. * The TTLBs are located at PHY 2G~4G.
  113. *
  114. * VA mapping:
  115. *
  116. * ------- <---- 0GB
  117. * | |
  118. * | |
  119. * |-------| <---- 0x24000000
  120. * |///////| ===> 192MB VA map for PCIe1 with offset 0x40_0000_0000
  121. * |-------| <---- 0x300000000
  122. * | |
  123. * |-------| <---- 0x34000000
  124. * |///////| ===> 192MB VA map for PCIe2 with offset 0x48_0000_0000
  125. * |-------| <---- 0x40000000
  126. * | |
  127. * |-------| <---- 0x80000000 DDR0 space start
  128. * |\\\\\\\|
  129. *.|\\\\\\\| ===> 2GB VA map for 2GB DDR0 Memory space
  130. * |\\\\\\\|
  131. * ------- <---- 4GB DDR0 space end
  132. */
  133. static void mmu_setup(void)
  134. {
  135. u32 *level0_table = (u32 *)gd->arch.tlb_addr;
  136. u32 *level1_table = (u32 *)(gd->arch.tlb_addr + 0x1000);
  137. u64 va_start = 0;
  138. u32 reg;
  139. int i;
  140. /* Level 0 Table 2-3 are used to map DDR */
  141. set_pgsection(level0_table, 3, 3 * BLOCK_SIZE_L1, MT_NORMAL);
  142. set_pgsection(level0_table, 2, 2 * BLOCK_SIZE_L1, MT_NORMAL);
  143. /* Level 0 Table 1 is used to map device */
  144. set_pgsection(level0_table, 1, 1 * BLOCK_SIZE_L1, MT_DEVICE_MEM);
  145. /* Level 0 Table 0 is used to map device including PCIe MEM */
  146. set_pgtable(level0_table, 0, (u32)level1_table);
  147. /* Level 1 has 512 entries */
  148. for (i = 0; i < 512; i++) {
  149. /* Mapping for PCIe 1 */
  150. if (va_start >= CONFIG_SYS_PCIE1_VIRT_ADDR &&
  151. va_start < (CONFIG_SYS_PCIE1_VIRT_ADDR +
  152. CONFIG_SYS_PCIE_MMAP_SIZE))
  153. set_pgsection(level1_table, i,
  154. CONFIG_SYS_PCIE1_PHYS_BASE + va_start,
  155. MT_DEVICE_MEM);
  156. /* Mapping for PCIe 2 */
  157. else if (va_start >= CONFIG_SYS_PCIE2_VIRT_ADDR &&
  158. va_start < (CONFIG_SYS_PCIE2_VIRT_ADDR +
  159. CONFIG_SYS_PCIE_MMAP_SIZE))
  160. set_pgsection(level1_table, i,
  161. CONFIG_SYS_PCIE2_PHYS_BASE + va_start,
  162. MT_DEVICE_MEM);
  163. else
  164. set_pgsection(level1_table, i,
  165. va_start,
  166. MT_DEVICE_MEM);
  167. va_start += BLOCK_SIZE_L2;
  168. }
  169. asm volatile("dsb sy;isb");
  170. asm volatile("mcr p15, 0, %0, c2, c0, 2" /* Write RT to TTBCR */
  171. : : "r" (TTBCR) : "memory");
  172. asm volatile("mcrr p15, 0, %0, %1, c2" /* TTBR 0 */
  173. : : "r" ((u32)level0_table), "r" (0) : "memory");
  174. asm volatile("mcr p15, 0, %0, c10, c2, 0" /* write MAIR 0 */
  175. : : "r" (MT_MAIR0) : "memory");
  176. asm volatile("mcr p15, 0, %0, c10, c2, 1" /* write MAIR 1 */
  177. : : "r" (MT_MAIR1) : "memory");
  178. /* Set the access control to all-supervisor */
  179. asm volatile("mcr p15, 0, %0, c3, c0, 0"
  180. : : "r" (~0));
  181. /* Enable the mmu */
  182. reg = get_cr();
  183. set_cr(reg | CR_M);
  184. }
  185. /*
  186. * This function is called from lib/board.c. It recreates MMU
  187. * table in main memory. MMU and i/d-cache are enabled here.
  188. */
  189. void enable_caches(void)
  190. {
  191. /* Invalidate all TLB */
  192. mmu_page_table_flush(gd->arch.tlb_addr,
  193. gd->arch.tlb_addr + gd->arch.tlb_size);
  194. /* Set up and enable mmu */
  195. mmu_setup();
  196. /* Invalidate & Enable d-cache */
  197. invalidate_dcache_all();
  198. set_cr(get_cr() | CR_C);
  199. }
  200. #endif /* #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) */
  201. uint get_svr(void)
  202. {
  203. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  204. return in_be32(&gur->svr);
  205. }
  206. #if defined(CONFIG_DISPLAY_CPUINFO)
  207. int print_cpuinfo(void)
  208. {
  209. char buf1[32], buf2[32];
  210. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  211. unsigned int svr, major, minor, ver, i;
  212. svr = in_be32(&gur->svr);
  213. major = SVR_MAJ(svr);
  214. minor = SVR_MIN(svr);
  215. puts("CPU: Freescale LayerScape ");
  216. ver = SVR_SOC_VER(svr);
  217. switch (ver) {
  218. case SOC_VER_SLS1020:
  219. puts("SLS1020");
  220. break;
  221. case SOC_VER_LS1020:
  222. puts("LS1020");
  223. break;
  224. case SOC_VER_LS1021:
  225. puts("LS1021");
  226. break;
  227. case SOC_VER_LS1022:
  228. puts("LS1022");
  229. break;
  230. default:
  231. puts("Unknown");
  232. break;
  233. }
  234. if (IS_E_PROCESSOR(svr) && (ver != SOC_VER_SLS1020))
  235. puts("E");
  236. printf(", Version: %d.%d, (0x%08x)\n", major, minor, svr);
  237. puts("Clock Configuration:");
  238. printf("\n CPU0(ARMV7):%-4s MHz, ", strmhz(buf1, gd->cpu_clk));
  239. printf("\n Bus:%-4s MHz, ", strmhz(buf1, gd->bus_clk));
  240. printf("DDR:%-4s MHz (%s MT/s data rate), ",
  241. strmhz(buf1, gd->mem_clk/2), strmhz(buf2, gd->mem_clk));
  242. puts("\n");
  243. /* Display the RCW, so that no one gets confused as to what RCW
  244. * we're actually using for this boot.
  245. */
  246. puts("Reset Configuration Word (RCW):");
  247. for (i = 0; i < ARRAY_SIZE(gur->rcwsr); i++) {
  248. u32 rcw = in_be32(&gur->rcwsr[i]);
  249. if ((i % 4) == 0)
  250. printf("\n %08x:", i * 4);
  251. printf(" %08x", rcw);
  252. }
  253. puts("\n");
  254. return 0;
  255. }
  256. #endif
  257. #ifdef CONFIG_FSL_ESDHC
  258. int cpu_mmc_init(struct bd_info *bis)
  259. {
  260. return fsl_esdhc_mmc_init(bis);
  261. }
  262. #endif
  263. int cpu_eth_init(struct bd_info *bis)
  264. {
  265. #if defined(CONFIG_TSEC_ENET) && !defined(CONFIG_DM_ETH)
  266. tsec_standard_init(bis);
  267. #endif
  268. return 0;
  269. }
  270. int arch_cpu_init(void)
  271. {
  272. void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET);
  273. void *rcpm2_base =
  274. (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET);
  275. struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR;
  276. u32 state;
  277. /*
  278. * The RCPM FSM state may not be reset after power-on.
  279. * So, reset them.
  280. */
  281. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR0) &
  282. CPMFSMSR_FSM_STATE_MASK;
  283. if (state != 0) {
  284. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x80);
  285. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR0, 0x0);
  286. }
  287. state = in_be32(rcpm2_base + DCSR_RCPM2_CPMFSMSR1) &
  288. CPMFSMSR_FSM_STATE_MASK;
  289. if (state != 0) {
  290. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x80);
  291. out_be32(rcpm2_base + DCSR_RCPM2_CPMFSMCR1, 0x0);
  292. }
  293. /*
  294. * After wakeup from deep sleep, Clear EPU registers
  295. * as early as possible to prevent from possible issue.
  296. * It's also safe to clear at normal boot.
  297. */
  298. fsl_epu_clean(epu_base);
  299. setbits_be32(&scfg->snpcnfgcr, SCFG_SNPCNFGCR_SEC_RD_WR);
  300. return 0;
  301. }
  302. #ifdef CONFIG_ARMV7_NONSEC
  303. /* Set the address at which the secondary core starts from.*/
  304. void smp_set_core_boot_addr(unsigned long addr, int corenr)
  305. {
  306. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  307. out_be32(&gur->scratchrw[0], addr);
  308. }
  309. /* Release the secondary core from holdoff state and kick it */
  310. void smp_kick_all_cpus(void)
  311. {
  312. struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR);
  313. out_be32(&gur->brrl, 0x2);
  314. /*
  315. * LS1 STANDBYWFE is not captured outside the ARM module in the soc.
  316. * So add a delay to wait bootrom execute WFE.
  317. */
  318. udelay(1);
  319. asm volatile("sev");
  320. }
  321. #endif
  322. void reset_cpu(ulong addr)
  323. {
  324. struct watchdog_regs *wdog = (struct watchdog_regs *)WDOG1_BASE_ADDR;
  325. clrbits_be16(&wdog->wcr, WCR_SRS);
  326. while (1) {
  327. /*
  328. * Let the watchdog trigger
  329. */
  330. }
  331. }
  332. void arch_preboot_os(void)
  333. {
  334. unsigned long ctrl;
  335. /* Disable PL1 Physical Timer */
  336. asm("mrc p15, 0, %0, c14, c2, 1" : "=r" (ctrl));
  337. ctrl &= ~ARCH_TIMER_CTRL_ENABLE;
  338. asm("mcr p15, 0, %0, c14, c2, 1" : : "r" (ctrl));
  339. }