mxs.c 6.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Freescale i.MX23/i.MX28 common code
  4. *
  5. * Copyright (C) 2011 Marek Vasut <marek.vasut@gmail.com>
  6. * on behalf of DENX Software Engineering GmbH
  7. *
  8. * Based on code from LTIB:
  9. * Copyright (C) 2010 Freescale Semiconductor, Inc.
  10. */
  11. #include <common.h>
  12. #include <command.h>
  13. #include <cpu_func.h>
  14. #include <hang.h>
  15. #include <init.h>
  16. #include <net.h>
  17. #include <linux/delay.h>
  18. #include <linux/errno.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/mach-imx/dma.h>
  22. #include <asm/arch/gpio.h>
  23. #include <asm/arch/iomux.h>
  24. #include <asm/arch/imx-regs.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <linux/compiler.h>
  27. DECLARE_GLOBAL_DATA_PTR;
  28. /* Lowlevel init isn't used on i.MX28, so just have a dummy here */
  29. __weak void lowlevel_init(void) {}
  30. void reset_cpu(ulong ignored) __attribute__((noreturn));
  31. void reset_cpu(ulong ignored)
  32. {
  33. struct mxs_rtc_regs *rtc_regs =
  34. (struct mxs_rtc_regs *)MXS_RTC_BASE;
  35. struct mxs_lcdif_regs *lcdif_regs =
  36. (struct mxs_lcdif_regs *)MXS_LCDIF_BASE;
  37. /*
  38. * Shut down the LCD controller as it interferes with BootROM boot mode
  39. * pads sampling.
  40. */
  41. writel(LCDIF_CTRL_RUN, &lcdif_regs->hw_lcdif_ctrl_clr);
  42. /* Wait 1 uS before doing the actual watchdog reset */
  43. writel(1, &rtc_regs->hw_rtc_watchdog);
  44. writel(RTC_CTRL_WATCHDOGEN, &rtc_regs->hw_rtc_ctrl_set);
  45. /* Endless loop, reset will exit from here */
  46. for (;;)
  47. ;
  48. }
  49. /*
  50. * This function will craft a jumptable at 0x0 which will redirect interrupt
  51. * vectoring to proper location of U-Boot in RAM.
  52. *
  53. * The structure of the jumptable will be as follows:
  54. * ldr pc, [pc, #0x18] ..... for each vector, thus repeated 8 times
  55. * <destination address> ... for each previous ldr, thus also repeated 8 times
  56. *
  57. * The "ldr pc, [pc, #0x18]" instruction above loads address from memory at
  58. * offset 0x18 from current value of PC register. Note that PC is already
  59. * incremented by 4 when computing the offset, so the effective offset is
  60. * actually 0x20, this the associated <destination address>. Loading the PC
  61. * register with an address performs a jump to that address.
  62. */
  63. void mx28_fixup_vt(uint32_t start_addr)
  64. {
  65. /* ldr pc, [pc, #0x18] */
  66. const uint32_t ldr_pc = 0xe59ff018;
  67. /* Jumptable location is 0x0 */
  68. uint32_t *vt = (uint32_t *)0x0;
  69. int i;
  70. for (i = 0; i < 8; i++) {
  71. /* cppcheck-suppress nullPointer */
  72. vt[i] = ldr_pc;
  73. /* cppcheck-suppress nullPointer */
  74. vt[i + 8] = start_addr + (4 * i);
  75. }
  76. }
  77. #ifdef CONFIG_ARCH_MISC_INIT
  78. int arch_misc_init(void)
  79. {
  80. mx28_fixup_vt(gd->relocaddr);
  81. return 0;
  82. }
  83. #endif
  84. int arch_cpu_init(void)
  85. {
  86. struct mxs_clkctrl_regs *clkctrl_regs =
  87. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  88. extern uint32_t _start;
  89. mx28_fixup_vt((uint32_t)&_start);
  90. /*
  91. * Enable NAND clock
  92. */
  93. /* Set bypass bit */
  94. writel(CLKCTRL_CLKSEQ_BYPASS_GPMI,
  95. &clkctrl_regs->hw_clkctrl_clkseq_set);
  96. /* Set GPMI clock to ref_xtal / 1 */
  97. clrbits_le32(&clkctrl_regs->hw_clkctrl_gpmi, CLKCTRL_GPMI_CLKGATE);
  98. while (readl(&clkctrl_regs->hw_clkctrl_gpmi) & CLKCTRL_GPMI_CLKGATE)
  99. ;
  100. clrsetbits_le32(&clkctrl_regs->hw_clkctrl_gpmi,
  101. CLKCTRL_GPMI_DIV_MASK, 1);
  102. udelay(1000);
  103. /*
  104. * Configure GPIO unit
  105. */
  106. mxs_gpio_init();
  107. #ifdef CONFIG_APBH_DMA
  108. /* Start APBH DMA */
  109. mxs_dma_init();
  110. #endif
  111. return 0;
  112. }
  113. u32 get_cpu_rev(void)
  114. {
  115. struct mxs_digctl_regs *digctl_regs =
  116. (struct mxs_digctl_regs *)MXS_DIGCTL_BASE;
  117. uint8_t rev = readl(&digctl_regs->hw_digctl_chipid) & 0x000000FF;
  118. switch (readl(&digctl_regs->hw_digctl_chipid) & HW_DIGCTL_CHIPID_MASK) {
  119. case HW_DIGCTL_CHIPID_MX23:
  120. switch (rev) {
  121. case 0x0:
  122. case 0x1:
  123. case 0x2:
  124. case 0x3:
  125. case 0x4:
  126. return (MXC_CPU_MX23 << 12) | (rev + 0x10);
  127. default:
  128. return 0;
  129. }
  130. case HW_DIGCTL_CHIPID_MX28:
  131. switch (rev) {
  132. case 0x1:
  133. return (MXC_CPU_MX28 << 12) | 0x12;
  134. default:
  135. return 0;
  136. }
  137. default:
  138. return 0;
  139. }
  140. }
  141. #if defined(CONFIG_DISPLAY_CPUINFO)
  142. const char *get_imx_type(u32 imxtype)
  143. {
  144. switch (imxtype) {
  145. case MXC_CPU_MX23:
  146. return "23";
  147. case MXC_CPU_MX28:
  148. return "28";
  149. default:
  150. return "??";
  151. }
  152. }
  153. int print_cpuinfo(void)
  154. {
  155. u32 cpurev;
  156. struct mxs_spl_data *data = MXS_SPL_DATA;
  157. cpurev = get_cpu_rev();
  158. printf("CPU: Freescale i.MX%s rev%d.%d at %d MHz\n",
  159. get_imx_type((cpurev & 0xFF000) >> 12),
  160. (cpurev & 0x000F0) >> 4,
  161. (cpurev & 0x0000F) >> 0,
  162. mxc_get_clock(MXC_ARM_CLK) / 1000000);
  163. printf("BOOT: %s\n", mxs_boot_modes[data->boot_mode_idx].mode);
  164. return 0;
  165. }
  166. #endif
  167. int do_mx28_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  168. char *const argv[])
  169. {
  170. printf("CPU: %3d MHz\n", mxc_get_clock(MXC_ARM_CLK) / 1000000);
  171. printf("BUS: %3d MHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000000);
  172. printf("EMI: %3d MHz\n", mxc_get_clock(MXC_EMI_CLK));
  173. printf("GPMI: %3d MHz\n", mxc_get_clock(MXC_GPMI_CLK) / 1000000);
  174. return 0;
  175. }
  176. /*
  177. * Initializes on-chip ethernet controllers.
  178. */
  179. #if defined(CONFIG_MX28) && defined(CONFIG_CMD_NET)
  180. int cpu_eth_init(struct bd_info *bis)
  181. {
  182. struct mxs_clkctrl_regs *clkctrl_regs =
  183. (struct mxs_clkctrl_regs *)MXS_CLKCTRL_BASE;
  184. /* Turn on ENET clocks */
  185. clrbits_le32(&clkctrl_regs->hw_clkctrl_enet,
  186. CLKCTRL_ENET_SLEEP | CLKCTRL_ENET_DISABLE);
  187. /* Set up ENET PLL for 50 MHz */
  188. /* Power on ENET PLL */
  189. writel(CLKCTRL_PLL2CTRL0_POWER,
  190. &clkctrl_regs->hw_clkctrl_pll2ctrl0_set);
  191. udelay(10);
  192. /* Gate on ENET PLL */
  193. writel(CLKCTRL_PLL2CTRL0_CLKGATE,
  194. &clkctrl_regs->hw_clkctrl_pll2ctrl0_clr);
  195. /* Enable pad output */
  196. setbits_le32(&clkctrl_regs->hw_clkctrl_enet, CLKCTRL_ENET_CLK_OUT_EN);
  197. return 0;
  198. }
  199. #endif
  200. __weak void mx28_adjust_mac(int dev_id, unsigned char *mac)
  201. {
  202. mac[0] = 0x00;
  203. mac[1] = 0x04; /* Use FSL vendor MAC address by default */
  204. if (dev_id == 1) /* Let MAC1 be MAC0 + 1 by default */
  205. mac[5] += 1;
  206. }
  207. #ifdef CONFIG_MX28_FEC_MAC_IN_OCOTP
  208. #define MXS_OCOTP_MAX_TIMEOUT 1000000
  209. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  210. {
  211. struct mxs_ocotp_regs *ocotp_regs =
  212. (struct mxs_ocotp_regs *)MXS_OCOTP_BASE;
  213. uint32_t data;
  214. memset(mac, 0, 6);
  215. writel(OCOTP_CTRL_RD_BANK_OPEN, &ocotp_regs->hw_ocotp_ctrl_set);
  216. if (mxs_wait_mask_clr(&ocotp_regs->hw_ocotp_ctrl_reg, OCOTP_CTRL_BUSY,
  217. MXS_OCOTP_MAX_TIMEOUT)) {
  218. printf("MXS FEC: Can't get MAC from OCOTP\n");
  219. return;
  220. }
  221. data = readl(&ocotp_regs->hw_ocotp_cust0);
  222. mac[2] = (data >> 24) & 0xff;
  223. mac[3] = (data >> 16) & 0xff;
  224. mac[4] = (data >> 8) & 0xff;
  225. mac[5] = data & 0xff;
  226. mx28_adjust_mac(dev_id, mac);
  227. }
  228. #else
  229. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  230. {
  231. memset(mac, 0, 6);
  232. }
  233. #endif
  234. int mxs_dram_init(void)
  235. {
  236. struct mxs_spl_data *data = MXS_SPL_DATA;
  237. if (data->mem_dram_size == 0) {
  238. printf("MXS:\n"
  239. "Error, the RAM size passed up from SPL is 0!\n");
  240. hang();
  241. }
  242. gd->ram_size = data->mem_dram_size;
  243. return 0;
  244. }
  245. U_BOOT_CMD(
  246. clocks, CONFIG_SYS_MAXARGS, 1, do_mx28_showclocks,
  247. "display clocks",
  248. ""
  249. );