generic.c 8.3 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
  4. * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
  5. */
  6. #include <common.h>
  7. #include <div64.h>
  8. #include <net.h>
  9. #include <netdev.h>
  10. #include <vsprintf.h>
  11. #include <asm/io.h>
  12. #include <asm/arch/imx-regs.h>
  13. #include <asm/arch/clock.h>
  14. #include <asm/arch/gpio.h>
  15. #include <asm/mach-imx/sys_proto.h>
  16. #ifdef CONFIG_MMC_MXC
  17. #include <asm/arch/mxcmmc.h>
  18. #endif
  19. /*
  20. * get the system pll clock in Hz
  21. *
  22. * mfi + mfn / (mfd +1)
  23. * f = 2 * f_ref * --------------------
  24. * pd + 1
  25. */
  26. static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
  27. {
  28. unsigned int mfi = (pll >> 10) & 0xf;
  29. unsigned int mfn = pll & 0x3ff;
  30. unsigned int mfd = (pll >> 16) & 0x3ff;
  31. unsigned int pd = (pll >> 26) & 0xf;
  32. mfi = mfi <= 5 ? 5 : mfi;
  33. return lldiv(2 * (u64)f_ref * (mfi * (mfd + 1) + mfn),
  34. (mfd + 1) * (pd + 1));
  35. }
  36. static ulong clk_in_32k(void)
  37. {
  38. return 1024 * CONFIG_MX27_CLK32;
  39. }
  40. static ulong clk_in_26m(void)
  41. {
  42. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  43. if (readl(&pll->cscr) & CSCR_OSC26M_DIV1P5) {
  44. /* divide by 1.5 */
  45. return 26000000 * 2 / 3;
  46. } else {
  47. return 26000000;
  48. }
  49. }
  50. static ulong imx_get_mpllclk(void)
  51. {
  52. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  53. ulong cscr = readl(&pll->cscr);
  54. ulong fref;
  55. if (cscr & CSCR_MCU_SEL)
  56. fref = clk_in_26m();
  57. else
  58. fref = clk_in_32k();
  59. return imx_decode_pll(readl(&pll->mpctl0), fref);
  60. }
  61. static ulong imx_get_armclk(void)
  62. {
  63. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  64. ulong cscr = readl(&pll->cscr);
  65. ulong fref = imx_get_mpllclk();
  66. ulong div;
  67. if (!(cscr & CSCR_ARM_SRC_MPLL))
  68. fref = lldiv((fref * 2), 3);
  69. div = ((cscr >> 12) & 0x3) + 1;
  70. return lldiv(fref, div);
  71. }
  72. static ulong imx_get_ahbclk(void)
  73. {
  74. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  75. ulong cscr = readl(&pll->cscr);
  76. ulong fref = imx_get_mpllclk();
  77. ulong div;
  78. div = ((cscr >> 8) & 0x3) + 1;
  79. return lldiv(fref * 2, 3 * div);
  80. }
  81. static __attribute__((unused)) ulong imx_get_spllclk(void)
  82. {
  83. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  84. ulong cscr = readl(&pll->cscr);
  85. ulong fref;
  86. if (cscr & CSCR_SP_SEL)
  87. fref = clk_in_26m();
  88. else
  89. fref = clk_in_32k();
  90. return imx_decode_pll(readl(&pll->spctl0), fref);
  91. }
  92. static ulong imx_decode_perclk(ulong div)
  93. {
  94. return lldiv((imx_get_mpllclk() * 2), (div * 3));
  95. }
  96. static ulong imx_get_perclk1(void)
  97. {
  98. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  99. return imx_decode_perclk((readl(&pll->pcdr1) & 0x3f) + 1);
  100. }
  101. static ulong imx_get_perclk2(void)
  102. {
  103. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  104. return imx_decode_perclk(((readl(&pll->pcdr1) >> 8) & 0x3f) + 1);
  105. }
  106. static __attribute__((unused)) ulong imx_get_perclk3(void)
  107. {
  108. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  109. return imx_decode_perclk(((readl(&pll->pcdr1) >> 16) & 0x3f) + 1);
  110. }
  111. static __attribute__((unused)) ulong imx_get_perclk4(void)
  112. {
  113. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  114. return imx_decode_perclk(((readl(&pll->pcdr1) >> 24) & 0x3f) + 1);
  115. }
  116. unsigned int mxc_get_clock(enum mxc_clock clk)
  117. {
  118. switch (clk) {
  119. case MXC_ARM_CLK:
  120. return imx_get_armclk();
  121. case MXC_I2C_CLK:
  122. return imx_get_ahbclk()/2;
  123. case MXC_UART_CLK:
  124. return imx_get_perclk1();
  125. case MXC_FEC_CLK:
  126. return imx_get_ahbclk();
  127. case MXC_ESDHC_CLK:
  128. return imx_get_perclk2();
  129. }
  130. return -1;
  131. }
  132. u32 get_cpu_rev(void)
  133. {
  134. return MXC_CPU_MX27 << 12;
  135. }
  136. #if defined(CONFIG_DISPLAY_CPUINFO)
  137. int print_cpuinfo (void)
  138. {
  139. char buf[32];
  140. printf("CPU: Freescale i.MX27 at %s MHz\n\n",
  141. strmhz(buf, imx_get_mpllclk()));
  142. return 0;
  143. }
  144. #endif
  145. int cpu_eth_init(struct bd_info *bis)
  146. {
  147. #if defined(CONFIG_FEC_MXC)
  148. struct pll_regs *pll = (struct pll_regs *)IMX_PLL_BASE;
  149. /* enable FEC clock */
  150. writel(readl(&pll->pccr1) | PCCR1_HCLK_FEC, &pll->pccr1);
  151. writel(readl(&pll->pccr0) | PCCR0_FEC_EN, &pll->pccr0);
  152. return fecmxc_initialize(bis);
  153. #else
  154. return 0;
  155. #endif
  156. }
  157. /*
  158. * Initializes on-chip MMC controllers.
  159. * to override, implement board_mmc_init()
  160. */
  161. int cpu_mmc_init(struct bd_info *bis)
  162. {
  163. #ifdef CONFIG_MMC_MXC
  164. return mxc_mmc_init(bis);
  165. #else
  166. return 0;
  167. #endif
  168. }
  169. void imx_gpio_mode(int gpio_mode)
  170. {
  171. struct gpio_port_regs *regs = (struct gpio_port_regs *)IMX_GPIO_BASE;
  172. unsigned int pin = gpio_mode & GPIO_PIN_MASK;
  173. unsigned int port = (gpio_mode & GPIO_PORT_MASK) >> GPIO_PORT_SHIFT;
  174. unsigned int ocr = (gpio_mode & GPIO_OCR_MASK) >> GPIO_OCR_SHIFT;
  175. unsigned int aout = (gpio_mode & GPIO_AOUT_MASK) >> GPIO_AOUT_SHIFT;
  176. unsigned int bout = (gpio_mode & GPIO_BOUT_MASK) >> GPIO_BOUT_SHIFT;
  177. unsigned int tmp;
  178. /* Pullup enable */
  179. if (gpio_mode & GPIO_PUEN) {
  180. writel(readl(&regs->port[port].puen) | (1 << pin),
  181. &regs->port[port].puen);
  182. } else {
  183. writel(readl(&regs->port[port].puen) & ~(1 << pin),
  184. &regs->port[port].puen);
  185. }
  186. /* Data direction */
  187. if (gpio_mode & GPIO_OUT) {
  188. writel(readl(&regs->port[port].gpio_dir) | 1 << pin,
  189. &regs->port[port].gpio_dir);
  190. } else {
  191. writel(readl(&regs->port[port].gpio_dir) & ~(1 << pin),
  192. &regs->port[port].gpio_dir);
  193. }
  194. /* Primary / alternate function */
  195. if (gpio_mode & GPIO_AF) {
  196. writel(readl(&regs->port[port].gpr) | (1 << pin),
  197. &regs->port[port].gpr);
  198. } else {
  199. writel(readl(&regs->port[port].gpr) & ~(1 << pin),
  200. &regs->port[port].gpr);
  201. }
  202. /* use as gpio? */
  203. if (!(gpio_mode & (GPIO_PF | GPIO_AF))) {
  204. writel(readl(&regs->port[port].gius) | (1 << pin),
  205. &regs->port[port].gius);
  206. } else {
  207. writel(readl(&regs->port[port].gius) & ~(1 << pin),
  208. &regs->port[port].gius);
  209. }
  210. /* Output / input configuration */
  211. if (pin < 16) {
  212. tmp = readl(&regs->port[port].ocr1);
  213. tmp &= ~(3 << (pin * 2));
  214. tmp |= (ocr << (pin * 2));
  215. writel(tmp, &regs->port[port].ocr1);
  216. writel(readl(&regs->port[port].iconfa1) & ~(3 << (pin * 2)),
  217. &regs->port[port].iconfa1);
  218. writel(readl(&regs->port[port].iconfa1) | aout << (pin * 2),
  219. &regs->port[port].iconfa1);
  220. writel(readl(&regs->port[port].iconfb1) & ~(3 << (pin * 2)),
  221. &regs->port[port].iconfb1);
  222. writel(readl(&regs->port[port].iconfb1) | bout << (pin * 2),
  223. &regs->port[port].iconfb1);
  224. } else {
  225. pin -= 16;
  226. tmp = readl(&regs->port[port].ocr2);
  227. tmp &= ~(3 << (pin * 2));
  228. tmp |= (ocr << (pin * 2));
  229. writel(tmp, &regs->port[port].ocr2);
  230. writel(readl(&regs->port[port].iconfa2) & ~(3 << (pin * 2)),
  231. &regs->port[port].iconfa2);
  232. writel(readl(&regs->port[port].iconfa2) | aout << (pin * 2),
  233. &regs->port[port].iconfa2);
  234. writel(readl(&regs->port[port].iconfb2) & ~(3 << (pin * 2)),
  235. &regs->port[port].iconfb2);
  236. writel(readl(&regs->port[port].iconfb2) | bout << (pin * 2),
  237. &regs->port[port].iconfb2);
  238. }
  239. }
  240. #ifdef CONFIG_MXC_UART
  241. void mx27_uart1_init_pins(void)
  242. {
  243. int i;
  244. unsigned int mode[] = {
  245. PE12_PF_UART1_TXD,
  246. PE13_PF_UART1_RXD,
  247. };
  248. for (i = 0; i < ARRAY_SIZE(mode); i++)
  249. imx_gpio_mode(mode[i]);
  250. }
  251. #endif /* CONFIG_MXC_UART */
  252. #ifdef CONFIG_FEC_MXC
  253. void mx27_fec_init_pins(void)
  254. {
  255. int i;
  256. unsigned int mode[] = {
  257. PD0_AIN_FEC_TXD0,
  258. PD1_AIN_FEC_TXD1,
  259. PD2_AIN_FEC_TXD2,
  260. PD3_AIN_FEC_TXD3,
  261. PD4_AOUT_FEC_RX_ER,
  262. PD5_AOUT_FEC_RXD1,
  263. PD6_AOUT_FEC_RXD2,
  264. PD7_AOUT_FEC_RXD3,
  265. PD8_AF_FEC_MDIO,
  266. PD9_AIN_FEC_MDC | GPIO_PUEN,
  267. PD10_AOUT_FEC_CRS,
  268. PD11_AOUT_FEC_TX_CLK,
  269. PD12_AOUT_FEC_RXD0,
  270. PD13_AOUT_FEC_RX_DV,
  271. PD14_AOUT_FEC_CLR,
  272. PD15_AOUT_FEC_COL,
  273. PD16_AIN_FEC_TX_ER,
  274. PF23_AIN_FEC_TX_EN,
  275. };
  276. for (i = 0; i < ARRAY_SIZE(mode); i++)
  277. imx_gpio_mode(mode[i]);
  278. }
  279. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  280. {
  281. int i;
  282. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  283. struct fuse_bank *bank = &iim->bank[0];
  284. struct fuse_bank0_regs *fuse =
  285. (struct fuse_bank0_regs *)bank->fuse_regs;
  286. for (i = 0; i < 6; i++)
  287. mac[6 - 1 - i] = readl(&fuse->mac_addr[i]) & 0xff;
  288. }
  289. #endif /* CONFIG_FEC_MXC */
  290. #ifdef CONFIG_MMC_MXC
  291. void mx27_sd1_init_pins(void)
  292. {
  293. int i;
  294. unsigned int mode[] = {
  295. PE18_PF_SD1_D0,
  296. PE19_PF_SD1_D1,
  297. PE20_PF_SD1_D2,
  298. PE21_PF_SD1_D3,
  299. PE22_PF_SD1_CMD,
  300. PE23_PF_SD1_CLK,
  301. };
  302. for (i = 0; i < ARRAY_SIZE(mode); i++)
  303. imx_gpio_mode(mode[i]);
  304. }
  305. void mx27_sd2_init_pins(void)
  306. {
  307. int i;
  308. unsigned int mode[] = {
  309. PB4_PF_SD2_D0,
  310. PB5_PF_SD2_D1,
  311. PB6_PF_SD2_D2,
  312. PB7_PF_SD2_D3,
  313. PB8_PF_SD2_CMD,
  314. PB9_PF_SD2_CLK,
  315. };
  316. for (i = 0; i < ARRAY_SIZE(mode); i++)
  317. imx_gpio_mode(mode[i]);
  318. }
  319. #endif /* CONFIG_MMC_MXC */