generic.c 5.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2009 DENX Software Engineering
  4. * Author: John Rigby <jrigby@gmail.com>
  5. *
  6. * Based on mx27/generic.c:
  7. * Copyright (c) 2008 Eric Jarrige <eric.jarrige@armadeus.org>
  8. * Copyright (c) 2009 Ilya Yanok <yanok@emcraft.com>
  9. */
  10. #include <common.h>
  11. #include <clock_legacy.h>
  12. #include <div64.h>
  13. #include <init.h>
  14. #include <net.h>
  15. #include <netdev.h>
  16. #include <vsprintf.h>
  17. #include <asm/io.h>
  18. #include <asm/arch-imx/cpu.h>
  19. #include <asm/arch/imx-regs.h>
  20. #include <asm/arch/clock.h>
  21. #ifdef CONFIG_FSL_ESDHC_IMX
  22. #include <fsl_esdhc_imx.h>
  23. DECLARE_GLOBAL_DATA_PTR;
  24. #endif
  25. /*
  26. * get the system pll clock in Hz
  27. *
  28. * mfi + mfn / (mfd +1)
  29. * f = 2 * f_ref * --------------------
  30. * pd + 1
  31. */
  32. static unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref)
  33. {
  34. unsigned int mfi = (pll >> CCM_PLL_MFI_SHIFT)
  35. & CCM_PLL_MFI_MASK;
  36. int mfn = (pll >> CCM_PLL_MFN_SHIFT)
  37. & CCM_PLL_MFN_MASK;
  38. unsigned int mfd = (pll >> CCM_PLL_MFD_SHIFT)
  39. & CCM_PLL_MFD_MASK;
  40. unsigned int pd = (pll >> CCM_PLL_PD_SHIFT)
  41. & CCM_PLL_PD_MASK;
  42. mfi = mfi <= 5 ? 5 : mfi;
  43. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  44. mfd += 1;
  45. pd += 1;
  46. return lldiv(2 * (u64) f_ref * (mfi * mfd + mfn),
  47. mfd * pd);
  48. }
  49. static ulong imx_get_mpllclk(void)
  50. {
  51. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  52. ulong fref = MXC_HCLK;
  53. return imx_decode_pll(readl(&ccm->mpctl), fref);
  54. }
  55. static ulong imx_get_upllclk(void)
  56. {
  57. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  58. ulong fref = MXC_HCLK;
  59. return imx_decode_pll(readl(&ccm->upctl), fref);
  60. }
  61. static ulong imx_get_armclk(void)
  62. {
  63. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  64. ulong cctl = readl(&ccm->cctl);
  65. ulong fref = imx_get_mpllclk();
  66. ulong div;
  67. if (cctl & CCM_CCTL_ARM_SRC)
  68. fref = lldiv((u64) fref * 3, 4);
  69. div = ((cctl >> CCM_CCTL_ARM_DIV_SHIFT)
  70. & CCM_CCTL_ARM_DIV_MASK) + 1;
  71. return fref / div;
  72. }
  73. static ulong imx_get_ahbclk(void)
  74. {
  75. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  76. ulong cctl = readl(&ccm->cctl);
  77. ulong fref = imx_get_armclk();
  78. ulong div;
  79. div = ((cctl >> CCM_CCTL_AHB_DIV_SHIFT)
  80. & CCM_CCTL_AHB_DIV_MASK) + 1;
  81. return fref / div;
  82. }
  83. static ulong imx_get_ipgclk(void)
  84. {
  85. return imx_get_ahbclk() / 2;
  86. }
  87. static ulong imx_get_perclk(int clk)
  88. {
  89. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  90. ulong fref = readl(&ccm->mcr) & (1 << clk) ? imx_get_upllclk() :
  91. imx_get_ahbclk();
  92. ulong div;
  93. div = readl(&ccm->pcdr[CCM_PERCLK_REG(clk)]);
  94. div = ((div >> CCM_PERCLK_SHIFT(clk)) & CCM_PERCLK_MASK) + 1;
  95. return fref / div;
  96. }
  97. int imx_set_perclk(enum mxc_clock clk, bool from_upll, unsigned int freq)
  98. {
  99. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  100. ulong fref = from_upll ? imx_get_upllclk() : imx_get_ahbclk();
  101. ulong div = (fref + freq - 1) / freq;
  102. if (clk > MXC_UART_CLK || !div || --div > CCM_PERCLK_MASK)
  103. return -EINVAL;
  104. clrsetbits_le32(&ccm->pcdr[CCM_PERCLK_REG(clk)],
  105. CCM_PERCLK_MASK << CCM_PERCLK_SHIFT(clk),
  106. div << CCM_PERCLK_SHIFT(clk));
  107. if (from_upll)
  108. setbits_le32(&ccm->mcr, 1 << clk);
  109. else
  110. clrbits_le32(&ccm->mcr, 1 << clk);
  111. return 0;
  112. }
  113. unsigned int mxc_get_clock(enum mxc_clock clk)
  114. {
  115. if (clk >= MXC_CLK_NUM)
  116. return -1;
  117. switch (clk) {
  118. case MXC_ARM_CLK:
  119. return imx_get_armclk();
  120. case MXC_AHB_CLK:
  121. return imx_get_ahbclk();
  122. case MXC_IPG_CLK:
  123. case MXC_CSPI_CLK:
  124. case MXC_FEC_CLK:
  125. return imx_get_ipgclk();
  126. default:
  127. return imx_get_perclk(clk);
  128. }
  129. }
  130. u32 get_cpu_rev(void)
  131. {
  132. u32 srev;
  133. u32 system_rev = 0x25000;
  134. /* read SREV register from IIM module */
  135. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  136. srev = readl(&iim->iim_srev);
  137. switch (srev) {
  138. case 0x00:
  139. system_rev |= CHIP_REV_1_0;
  140. break;
  141. case 0x01:
  142. system_rev |= CHIP_REV_1_1;
  143. break;
  144. case 0x02:
  145. system_rev |= CHIP_REV_1_2;
  146. break;
  147. default:
  148. system_rev |= 0x8000;
  149. break;
  150. }
  151. return system_rev;
  152. }
  153. #if defined(CONFIG_DISPLAY_CPUINFO)
  154. static char *get_reset_cause(void)
  155. {
  156. /* read RCSR register from CCM module */
  157. struct ccm_regs *ccm =
  158. (struct ccm_regs *)IMX_CCM_BASE;
  159. u32 cause = readl(&ccm->rcsr) & 0x0f;
  160. if (cause == 0)
  161. return "POR";
  162. else if (cause == 1)
  163. return "RST";
  164. else if ((cause & 2) == 2)
  165. return "WDOG";
  166. else if ((cause & 4) == 4)
  167. return "SW RESET";
  168. else if ((cause & 8) == 8)
  169. return "JTAG";
  170. else
  171. return "unknown reset";
  172. }
  173. int print_cpuinfo(void)
  174. {
  175. char buf[32];
  176. u32 cpurev = get_cpu_rev();
  177. printf("CPU: Freescale i.MX25 rev%d.%d%s at %s MHz\n",
  178. (cpurev & 0xF0) >> 4, (cpurev & 0x0F),
  179. ((cpurev & 0x8000) ? " unknown" : ""),
  180. strmhz(buf, imx_get_armclk()));
  181. printf("Reset cause: %s\n", get_reset_cause());
  182. return 0;
  183. }
  184. #endif
  185. #if defined(CONFIG_FEC_MXC)
  186. /*
  187. * Initializes on-chip ethernet controllers.
  188. * to override, implement board_eth_init()
  189. */
  190. int cpu_eth_init(struct bd_info *bis)
  191. {
  192. struct ccm_regs *ccm = (struct ccm_regs *)IMX_CCM_BASE;
  193. ulong val;
  194. val = readl(&ccm->cgr0);
  195. val |= (1 << 23);
  196. writel(val, &ccm->cgr0);
  197. return fecmxc_initialize(bis);
  198. }
  199. #endif
  200. int get_clocks(void)
  201. {
  202. #ifdef CONFIG_FSL_ESDHC_IMX
  203. #if CONFIG_SYS_FSL_ESDHC_ADDR == IMX_MMC_SDHC2_BASE
  204. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  205. #else
  206. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  207. #endif
  208. #endif
  209. return 0;
  210. }
  211. #ifdef CONFIG_FSL_ESDHC_IMX
  212. /*
  213. * Initializes on-chip MMC controllers.
  214. * to override, implement board_mmc_init()
  215. */
  216. int cpu_mmc_init(struct bd_info *bis)
  217. {
  218. return fsl_esdhc_mmc_init(bis);
  219. }
  220. #endif
  221. #ifdef CONFIG_FEC_MXC
  222. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  223. {
  224. int i;
  225. struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
  226. struct fuse_bank *bank = &iim->bank[0];
  227. struct fuse_bank0_regs *fuse =
  228. (struct fuse_bank0_regs *)bank->fuse_regs;
  229. for (i = 0; i < 6; i++)
  230. mac[i] = readl(&fuse->mac_addr[i]) & 0xff;
  231. }
  232. #endif /* CONFIG_FEC_MXC */