generic.c 12 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007
  4. * Sascha Hauer, Pengutronix
  5. *
  6. * (C) Copyright 2008-2010 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <clock_legacy.h>
  10. #include <command.h>
  11. #include <div64.h>
  12. #include <init.h>
  13. #include <net.h>
  14. #include <asm/io.h>
  15. #include <linux/errno.h>
  16. #include <asm/arch/imx-regs.h>
  17. #include <asm/arch/crm_regs.h>
  18. #include <asm/arch/clock.h>
  19. #include <asm/arch/sys_proto.h>
  20. #ifdef CONFIG_FSL_ESDHC_IMX
  21. #include <fsl_esdhc_imx.h>
  22. #endif
  23. #include <netdev.h>
  24. #include <spl.h>
  25. #define CLK_CODE(arm, ahb, sel) (((arm) << 16) + ((ahb) << 8) + (sel))
  26. #define CLK_CODE_ARM(c) (((c) >> 16) & 0xFF)
  27. #define CLK_CODE_AHB(c) (((c) >> 8) & 0xFF)
  28. #define CLK_CODE_PATH(c) ((c) & 0xFF)
  29. #define CCM_GET_DIVIDER(x, m, o) (((x) & (m)) >> (o))
  30. #ifdef CONFIG_FSL_ESDHC_IMX
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #endif
  33. static int g_clk_mux_auto[8] = {
  34. CLK_CODE(1, 3, 0), CLK_CODE(1, 2, 1), CLK_CODE(2, 1, 1), -1,
  35. CLK_CODE(1, 6, 0), CLK_CODE(1, 4, 1), CLK_CODE(2, 2, 1), -1,
  36. };
  37. static int g_clk_mux_consumer[16] = {
  38. CLK_CODE(1, 4, 0), CLK_CODE(1, 3, 1), CLK_CODE(1, 3, 1), -1,
  39. -1, -1, CLK_CODE(4, 1, 0), CLK_CODE(1, 5, 0),
  40. CLK_CODE(1, 8, 1), CLK_CODE(1, 6, 1), CLK_CODE(2, 4, 0), -1,
  41. -1, -1, CLK_CODE(4, 2, 0), -1,
  42. };
  43. static int hsp_div_table[3][16] = {
  44. {4, 3, 2, -1, -1, -1, 1, 5, 4, 3, 2, -1, -1, -1, 1, -1},
  45. {-1, -1, -1, -1, -1, -1, -1, -1, 8, 6, 4, -1, -1, -1, 2, -1},
  46. {3, -1, -1, -1, -1, -1, -1, -1, 3, -1, -1, -1, -1, -1, -1, -1},
  47. };
  48. u32 get_cpu_rev(void)
  49. {
  50. int reg;
  51. struct iim_regs *iim =
  52. (struct iim_regs *)IIM_BASE_ADDR;
  53. reg = readl(&iim->iim_srev);
  54. if (!reg) {
  55. reg = readw(ROMPATCH_REV);
  56. reg <<= 4;
  57. } else {
  58. reg += CHIP_REV_1_0;
  59. }
  60. return 0x35000 + (reg & 0xFF);
  61. }
  62. static u32 get_arm_div(u32 pdr0, u32 *fi, u32 *fd)
  63. {
  64. int *pclk_mux;
  65. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  66. pclk_mux = g_clk_mux_consumer +
  67. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  68. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  69. } else {
  70. pclk_mux = g_clk_mux_auto +
  71. ((pdr0 & MXC_CCM_PDR0_AUTO_MUX_DIV_MASK) >>
  72. MXC_CCM_PDR0_AUTO_MUX_DIV_OFFSET);
  73. }
  74. if ((*pclk_mux) == -1)
  75. return -1;
  76. if (fi && fd) {
  77. if (!CLK_CODE_PATH(*pclk_mux)) {
  78. *fi = *fd = 1;
  79. return CLK_CODE_ARM(*pclk_mux);
  80. }
  81. if (pdr0 & MXC_CCM_PDR0_AUTO_CON) {
  82. *fi = 3;
  83. *fd = 4;
  84. } else {
  85. *fi = 2;
  86. *fd = 3;
  87. }
  88. }
  89. return CLK_CODE_ARM(*pclk_mux);
  90. }
  91. static int get_ahb_div(u32 pdr0)
  92. {
  93. int *pclk_mux;
  94. pclk_mux = g_clk_mux_consumer +
  95. ((pdr0 & MXC_CCM_PDR0_CON_MUX_DIV_MASK) >>
  96. MXC_CCM_PDR0_CON_MUX_DIV_OFFSET);
  97. if ((*pclk_mux) == -1)
  98. return -1;
  99. return CLK_CODE_AHB(*pclk_mux);
  100. }
  101. static u32 decode_pll(u32 reg, u32 infreq)
  102. {
  103. u32 mfi = (reg >> 10) & 0xf;
  104. s32 mfn = reg & 0x3ff;
  105. u32 mfd = (reg >> 16) & 0x3ff;
  106. u32 pd = (reg >> 26) & 0xf;
  107. mfi = mfi <= 5 ? 5 : mfi;
  108. mfn = mfn >= 512 ? mfn - 1024 : mfn;
  109. mfd += 1;
  110. pd += 1;
  111. return lldiv(2 * (u64)infreq * (mfi * mfd + mfn),
  112. mfd * pd);
  113. }
  114. static u32 get_mcu_main_clk(void)
  115. {
  116. u32 arm_div = 0, fi = 0, fd = 0;
  117. struct ccm_regs *ccm =
  118. (struct ccm_regs *)IMX_CCM_BASE;
  119. arm_div = get_arm_div(readl(&ccm->pdr0), &fi, &fd);
  120. fi *= decode_pll(readl(&ccm->mpctl), MXC_HCLK);
  121. return fi / (arm_div * fd);
  122. }
  123. static u32 get_ipg_clk(void)
  124. {
  125. u32 freq = get_mcu_main_clk();
  126. struct ccm_regs *ccm =
  127. (struct ccm_regs *)IMX_CCM_BASE;
  128. u32 pdr0 = readl(&ccm->pdr0);
  129. return freq / (get_ahb_div(pdr0) * 2);
  130. }
  131. static u32 get_ipg_per_clk(void)
  132. {
  133. u32 freq = get_mcu_main_clk();
  134. struct ccm_regs *ccm =
  135. (struct ccm_regs *)IMX_CCM_BASE;
  136. u32 pdr0 = readl(&ccm->pdr0);
  137. u32 pdr4 = readl(&ccm->pdr4);
  138. u32 div;
  139. if (pdr0 & MXC_CCM_PDR0_PER_SEL) {
  140. div = CCM_GET_DIVIDER(pdr4,
  141. MXC_CCM_PDR4_PER0_PODF_MASK,
  142. MXC_CCM_PDR4_PER0_PODF_OFFSET) + 1;
  143. } else {
  144. div = CCM_GET_DIVIDER(pdr0,
  145. MXC_CCM_PDR0_PER_PODF_MASK,
  146. MXC_CCM_PDR0_PER_PODF_OFFSET) + 1;
  147. div *= get_ahb_div(pdr0);
  148. }
  149. return freq / div;
  150. }
  151. u32 imx_get_uartclk(void)
  152. {
  153. u32 freq;
  154. struct ccm_regs *ccm =
  155. (struct ccm_regs *)IMX_CCM_BASE;
  156. u32 pdr4 = readl(&ccm->pdr4);
  157. if (readl(&ccm->pdr3) & MXC_CCM_PDR3_UART_M_U)
  158. freq = get_mcu_main_clk();
  159. else
  160. freq = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  161. freq /= CCM_GET_DIVIDER(pdr4,
  162. MXC_CCM_PDR4_UART_PODF_MASK,
  163. MXC_CCM_PDR4_UART_PODF_OFFSET) + 1;
  164. return freq;
  165. }
  166. unsigned int mxc_get_main_clock(enum mxc_main_clock clk)
  167. {
  168. u32 nfc_pdf, hsp_podf;
  169. u32 pll, ret_val = 0, usb_podf;
  170. struct ccm_regs *ccm =
  171. (struct ccm_regs *)IMX_CCM_BASE;
  172. u32 reg = readl(&ccm->pdr0);
  173. u32 reg4 = readl(&ccm->pdr4);
  174. reg |= 0x1;
  175. switch (clk) {
  176. case CPU_CLK:
  177. ret_val = get_mcu_main_clk();
  178. break;
  179. case AHB_CLK:
  180. ret_val = get_mcu_main_clk();
  181. break;
  182. case HSP_CLK:
  183. if (reg & CLKMODE_CONSUMER) {
  184. hsp_podf = (reg >> 20) & 0x3;
  185. pll = get_mcu_main_clk();
  186. hsp_podf = hsp_div_table[hsp_podf][(reg>>16)&0xF];
  187. if (hsp_podf > 0) {
  188. ret_val = pll / hsp_podf;
  189. } else {
  190. puts("mismatch HSP with ARM clock setting\n");
  191. ret_val = 0;
  192. }
  193. } else {
  194. ret_val = get_mcu_main_clk();
  195. }
  196. break;
  197. case IPG_CLK:
  198. ret_val = get_ipg_clk();
  199. break;
  200. case IPG_PER_CLK:
  201. ret_val = get_ipg_per_clk();
  202. break;
  203. case NFC_CLK:
  204. nfc_pdf = (reg4 >> 28) & 0xF;
  205. pll = get_mcu_main_clk();
  206. /* AHB/nfc_pdf */
  207. ret_val = pll / (nfc_pdf + 1);
  208. break;
  209. case USB_CLK:
  210. usb_podf = (reg4 >> 22) & 0x3F;
  211. if (reg4 & 0x200)
  212. pll = get_mcu_main_clk();
  213. else
  214. pll = decode_pll(readl(&ccm->ppctl), MXC_HCLK);
  215. ret_val = pll / (usb_podf + 1);
  216. break;
  217. default:
  218. printf("Unknown clock: %d\n", clk);
  219. break;
  220. }
  221. return ret_val;
  222. }
  223. unsigned int mxc_get_peri_clock(enum mxc_peri_clock clk)
  224. {
  225. u32 ret_val = 0, pdf, pre_pdf, clk_sel;
  226. struct ccm_regs *ccm =
  227. (struct ccm_regs *)IMX_CCM_BASE;
  228. u32 mpdr2 = readl(&ccm->pdr2);
  229. u32 mpdr3 = readl(&ccm->pdr3);
  230. u32 mpdr4 = readl(&ccm->pdr4);
  231. switch (clk) {
  232. case UART1_BAUD:
  233. case UART2_BAUD:
  234. case UART3_BAUD:
  235. clk_sel = mpdr3 & (1 << 14);
  236. pdf = (mpdr4 >> 10) & 0x3F;
  237. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  238. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  239. break;
  240. case SSI1_BAUD:
  241. pre_pdf = (mpdr2 >> 24) & 0x7;
  242. pdf = mpdr2 & 0x3F;
  243. clk_sel = mpdr2 & (1 << 6);
  244. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  245. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  246. ((pre_pdf + 1) * (pdf + 1));
  247. break;
  248. case SSI2_BAUD:
  249. pre_pdf = (mpdr2 >> 27) & 0x7;
  250. pdf = (mpdr2 >> 8) & 0x3F;
  251. clk_sel = mpdr2 & (1 << 6);
  252. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  253. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  254. ((pre_pdf + 1) * (pdf + 1));
  255. break;
  256. case CSI_BAUD:
  257. clk_sel = mpdr2 & (1 << 7);
  258. pdf = (mpdr2 >> 16) & 0x3F;
  259. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  260. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  261. break;
  262. case MSHC_CLK:
  263. pre_pdf = readl(&ccm->pdr1);
  264. clk_sel = (pre_pdf & 0x80);
  265. pdf = (pre_pdf >> 22) & 0x3F;
  266. pre_pdf = (pre_pdf >> 28) & 0x7;
  267. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  268. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  269. ((pre_pdf + 1) * (pdf + 1));
  270. break;
  271. case ESDHC1_CLK:
  272. clk_sel = mpdr3 & 0x40;
  273. pdf = mpdr3 & 0x3F;
  274. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  275. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  276. break;
  277. case ESDHC2_CLK:
  278. clk_sel = mpdr3 & 0x40;
  279. pdf = (mpdr3 >> 8) & 0x3F;
  280. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  281. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  282. break;
  283. case ESDHC3_CLK:
  284. clk_sel = mpdr3 & 0x40;
  285. pdf = (mpdr3 >> 16) & 0x3F;
  286. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  287. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) / (pdf + 1);
  288. break;
  289. case SPDIF_CLK:
  290. clk_sel = mpdr3 & 0x400000;
  291. pre_pdf = (mpdr3 >> 29) & 0x7;
  292. pdf = (mpdr3 >> 23) & 0x3F;
  293. ret_val = ((clk_sel != 0) ? mxc_get_main_clock(CPU_CLK) :
  294. decode_pll(readl(&ccm->ppctl), MXC_HCLK)) /
  295. ((pre_pdf + 1) * (pdf + 1));
  296. break;
  297. default:
  298. printf("%s(): This clock: %d not supported yet\n",
  299. __func__, clk);
  300. break;
  301. }
  302. return ret_val;
  303. }
  304. unsigned int mxc_get_clock(enum mxc_clock clk)
  305. {
  306. switch (clk) {
  307. case MXC_ARM_CLK:
  308. return get_mcu_main_clk();
  309. case MXC_AHB_CLK:
  310. break;
  311. case MXC_IPG_CLK:
  312. return get_ipg_clk();
  313. case MXC_IPG_PERCLK:
  314. case MXC_I2C_CLK:
  315. return get_ipg_per_clk();
  316. case MXC_UART_CLK:
  317. return imx_get_uartclk();
  318. case MXC_ESDHC1_CLK:
  319. return mxc_get_peri_clock(ESDHC1_CLK);
  320. case MXC_ESDHC2_CLK:
  321. return mxc_get_peri_clock(ESDHC2_CLK);
  322. case MXC_ESDHC3_CLK:
  323. return mxc_get_peri_clock(ESDHC3_CLK);
  324. case MXC_USB_CLK:
  325. return mxc_get_main_clock(USB_CLK);
  326. case MXC_FEC_CLK:
  327. return get_ipg_clk();
  328. case MXC_CSPI_CLK:
  329. return get_ipg_clk();
  330. }
  331. return -1;
  332. }
  333. #ifdef CONFIG_FEC_MXC
  334. /*
  335. * The MX35 has no fuse for MAC, return a NULL MAC
  336. */
  337. void imx_get_mac_from_fuse(int dev_id, unsigned char *mac)
  338. {
  339. memset(mac, 0, 6);
  340. }
  341. u32 imx_get_fecclk(void)
  342. {
  343. return mxc_get_clock(MXC_IPG_CLK);
  344. }
  345. #endif
  346. int do_mx35_showclocks(struct cmd_tbl *cmdtp, int flag, int argc,
  347. char *const argv[])
  348. {
  349. u32 cpufreq = get_mcu_main_clk();
  350. printf("mx35 cpu clock: %dMHz\n", cpufreq / 1000000);
  351. printf("ipg clock : %dHz\n", get_ipg_clk());
  352. printf("ipg per clock : %dHz\n", get_ipg_per_clk());
  353. printf("uart clock : %dHz\n", mxc_get_clock(MXC_UART_CLK));
  354. return 0;
  355. }
  356. U_BOOT_CMD(
  357. clocks, CONFIG_SYS_MAXARGS, 1, do_mx35_showclocks,
  358. "display clocks",
  359. ""
  360. );
  361. #if defined(CONFIG_DISPLAY_CPUINFO)
  362. static char *get_reset_cause(void)
  363. {
  364. /* read RCSR register from CCM module */
  365. struct ccm_regs *ccm =
  366. (struct ccm_regs *)IMX_CCM_BASE;
  367. u32 cause = readl(&ccm->rcsr) & 0x0F;
  368. switch (cause) {
  369. case 0x0000:
  370. return "POR";
  371. case 0x0002:
  372. return "JTAG";
  373. case 0x0004:
  374. return "RST";
  375. case 0x0008:
  376. return "WDOG";
  377. default:
  378. return "unknown reset";
  379. }
  380. }
  381. int print_cpuinfo(void)
  382. {
  383. u32 srev = get_cpu_rev();
  384. printf("CPU: Freescale i.MX35 rev %d.%d at %d MHz.\n",
  385. (srev & 0xF0) >> 4, (srev & 0x0F),
  386. get_mcu_main_clk() / 1000000);
  387. printf("Reset cause: %s\n", get_reset_cause());
  388. return 0;
  389. }
  390. #endif
  391. /*
  392. * Initializes on-chip ethernet controllers.
  393. * to override, implement board_eth_init()
  394. */
  395. int cpu_eth_init(struct bd_info *bis)
  396. {
  397. int rc = -ENODEV;
  398. #if defined(CONFIG_FEC_MXC)
  399. rc = fecmxc_initialize(bis);
  400. #endif
  401. return rc;
  402. }
  403. #ifdef CONFIG_FSL_ESDHC_IMX
  404. /*
  405. * Initializes on-chip MMC controllers.
  406. * to override, implement board_mmc_init()
  407. */
  408. int cpu_mmc_init(struct bd_info *bis)
  409. {
  410. return fsl_esdhc_mmc_init(bis);
  411. }
  412. #endif
  413. int get_clocks(void)
  414. {
  415. #ifdef CONFIG_FSL_ESDHC_IMX
  416. #if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR
  417. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK);
  418. #elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR
  419. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK);
  420. #else
  421. gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC1_CLK);
  422. #endif
  423. #endif
  424. return 0;
  425. }
  426. #define RCSR_MEM_CTL_WEIM 0
  427. #define RCSR_MEM_CTL_NAND 1
  428. #define RCSR_MEM_CTL_ATA 2
  429. #define RCSR_MEM_CTL_EXPANSION 3
  430. #define RCSR_MEM_TYPE_NOR 0
  431. #define RCSR_MEM_TYPE_ONENAND 2
  432. #define RCSR_MEM_TYPE_SD 0
  433. #define RCSR_MEM_TYPE_I2C 2
  434. #define RCSR_MEM_TYPE_SPI 3
  435. u32 spl_boot_device(void)
  436. {
  437. struct ccm_regs *ccm =
  438. (struct ccm_regs *)IMX_CCM_BASE;
  439. u32 rcsr = readl(&ccm->rcsr);
  440. u32 mem_type, mem_ctl;
  441. /* In external mode, no boot device is returned */
  442. if ((rcsr >> 10) & 0x03)
  443. return BOOT_DEVICE_NONE;
  444. mem_ctl = (rcsr >> 25) & 0x03;
  445. mem_type = (rcsr >> 23) & 0x03;
  446. switch (mem_ctl) {
  447. case RCSR_MEM_CTL_WEIM:
  448. switch (mem_type) {
  449. case RCSR_MEM_TYPE_NOR:
  450. return BOOT_DEVICE_NOR;
  451. case RCSR_MEM_TYPE_ONENAND:
  452. return BOOT_DEVICE_ONENAND;
  453. default:
  454. return BOOT_DEVICE_NONE;
  455. }
  456. case RCSR_MEM_CTL_NAND:
  457. return BOOT_DEVICE_NAND;
  458. case RCSR_MEM_CTL_EXPANSION:
  459. switch (mem_type) {
  460. case RCSR_MEM_TYPE_SD:
  461. return BOOT_DEVICE_MMC1;
  462. case RCSR_MEM_TYPE_I2C:
  463. return BOOT_DEVICE_I2C;
  464. case RCSR_MEM_TYPE_SPI:
  465. return BOOT_DEVICE_SPI;
  466. default:
  467. return BOOT_DEVICE_NONE;
  468. }
  469. }
  470. return BOOT_DEVICE_NONE;
  471. }