usb.c 18 KB

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  1. /*
  2. * Copyright (c) 2011 The Chromium OS Authors.
  3. * (C) Copyright 2010,2011 NVIDIA Corporation <www.nvidia.com>
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/io.h>
  25. #include <asm-generic/gpio.h>
  26. #include <asm/arch/clock.h>
  27. #include <asm/arch/gpio.h>
  28. #include <asm/arch/pinmux.h>
  29. #include <asm/arch/tegra.h>
  30. #include <asm/arch/usb.h>
  31. #include <usb/ulpi.h>
  32. #include <asm/arch-tegra/clk_rst.h>
  33. #include <asm/arch-tegra/sys_proto.h>
  34. #include <asm/arch-tegra/uart.h>
  35. #include <libfdt.h>
  36. #include <fdtdec.h>
  37. #ifdef CONFIG_USB_ULPI
  38. #ifndef CONFIG_USB_ULPI_VIEWPORT
  39. #error "To use CONFIG_USB_ULPI on Tegra Boards you have to also \
  40. define CONFIG_USB_ULPI_VIEWPORT"
  41. #endif
  42. #endif
  43. enum {
  44. USB_PORTS_MAX = 4, /* Maximum ports we allow */
  45. };
  46. /* Parameters we need for USB */
  47. enum {
  48. PARAM_DIVN, /* PLL FEEDBACK DIVIDer */
  49. PARAM_DIVM, /* PLL INPUT DIVIDER */
  50. PARAM_DIVP, /* POST DIVIDER (2^N) */
  51. PARAM_CPCON, /* BASE PLLC CHARGE Pump setup ctrl */
  52. PARAM_LFCON, /* BASE PLLC LOOP FILter setup ctrl */
  53. PARAM_ENABLE_DELAY_COUNT, /* PLL-U Enable Delay Count */
  54. PARAM_STABLE_COUNT, /* PLL-U STABLE count */
  55. PARAM_ACTIVE_DELAY_COUNT, /* PLL-U Active delay count */
  56. PARAM_XTAL_FREQ_COUNT, /* PLL-U XTAL frequency count */
  57. PARAM_DEBOUNCE_A_TIME, /* 10MS DELAY for BIAS_DEBOUNCE_A */
  58. PARAM_BIAS_TIME, /* 20US DELAY AFter bias cell op */
  59. PARAM_COUNT
  60. };
  61. /* Possible port types (dual role mode) */
  62. enum dr_mode {
  63. DR_MODE_NONE = 0,
  64. DR_MODE_HOST, /* supports host operation */
  65. DR_MODE_DEVICE, /* supports device operation */
  66. DR_MODE_OTG, /* supports both */
  67. };
  68. /* Information about a USB port */
  69. struct fdt_usb {
  70. struct usb_ctlr *reg; /* address of registers in physical memory */
  71. unsigned utmi:1; /* 1 if port has external tranceiver, else 0 */
  72. unsigned ulpi:1; /* 1 if port has external ULPI transceiver */
  73. unsigned enabled:1; /* 1 to enable, 0 to disable */
  74. unsigned has_legacy_mode:1; /* 1 if this port has legacy mode */
  75. enum dr_mode dr_mode; /* dual role mode */
  76. enum periph_id periph_id;/* peripheral id */
  77. struct fdt_gpio_state vbus_gpio; /* GPIO for vbus enable */
  78. struct fdt_gpio_state phy_reset_gpio; /* GPIO to reset ULPI phy */
  79. };
  80. static struct fdt_usb port[USB_PORTS_MAX]; /* List of valid USB ports */
  81. static unsigned port_count; /* Number of available ports */
  82. /*
  83. * This table has USB timing parameters for each Oscillator frequency we
  84. * support. There are four sets of values:
  85. *
  86. * 1. PLLU configuration information (reference clock is osc/clk_m and
  87. * PLLU-FOs are fixed at 12MHz/60MHz/480MHz).
  88. *
  89. * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
  90. * ----------------------------------------------------------------------
  91. * DIVN 960 (0x3c0) 200 (0c8) 960 (3c0h) 960 (3c0)
  92. * DIVM 13 (0d) 4 (04) 12 (0c) 26 (1a)
  93. * Filter frequency (MHz) 1 4.8 6 2
  94. * CPCON 1100b 0011b 1100b 1100b
  95. * LFCON0 0 0 0 0
  96. *
  97. * 2. PLL CONFIGURATION & PARAMETERS for different clock generators:
  98. *
  99. * Reference frequency 13.0MHz 19.2MHz 12.0MHz 26.0MHz
  100. * ---------------------------------------------------------------------------
  101. * PLLU_ENABLE_DLY_COUNT 02 (0x02) 03 (03) 02 (02) 04 (04)
  102. * PLLU_STABLE_COUNT 51 (33) 75 (4B) 47 (2F) 102 (66)
  103. * PLL_ACTIVE_DLY_COUNT 05 (05) 06 (06) 04 (04) 09 (09)
  104. * XTAL_FREQ_COUNT 127 (7F) 187 (BB) 118 (76) 254 (FE)
  105. *
  106. * 3. Debounce values IdDig, Avalid, Bvalid, VbusValid, VbusWakeUp, and
  107. * SessEnd. Each of these signals have their own debouncer and for each of
  108. * those one out of two debouncing times can be chosen (BIAS_DEBOUNCE_A or
  109. * BIAS_DEBOUNCE_B).
  110. *
  111. * The values of DEBOUNCE_A and DEBOUNCE_B are calculated as follows:
  112. * 0xffff -> No debouncing at all
  113. * <n> ms = <n> *1000 / (1/19.2MHz) / 4
  114. *
  115. * So to program a 1 ms debounce for BIAS_DEBOUNCE_A, we have:
  116. * BIAS_DEBOUNCE_A[15:0] = 1000 * 19.2 / 4 = 4800 = 0x12c0
  117. *
  118. * We need to use only DebounceA for BOOTROM. We don't need the DebounceB
  119. * values, so we can keep those to default.
  120. *
  121. * 4. The 20 microsecond delay after bias cell operation.
  122. */
  123. static const unsigned usb_pll[CLOCK_OSC_FREQ_COUNT][PARAM_COUNT] = {
  124. /* DivN, DivM, DivP, CPCON, LFCON, Delays Debounce, Bias */
  125. { 0x3C0, 0x0D, 0x00, 0xC, 0, 0x02, 0x33, 0x05, 0x7F, 0x7EF4, 5 },
  126. { 0x0C8, 0x04, 0x00, 0x3, 0, 0x03, 0x4B, 0x06, 0xBB, 0xBB80, 7 },
  127. { 0x3C0, 0x0C, 0x00, 0xC, 0, 0x02, 0x2F, 0x04, 0x76, 0x7530, 5 },
  128. { 0x3C0, 0x1A, 0x00, 0xC, 0, 0x04, 0x66, 0x09, 0xFE, 0xFDE8, 9 }
  129. };
  130. /* UTMIP Idle Wait Delay */
  131. static const u8 utmip_idle_wait_delay = 17;
  132. /* UTMIP Elastic limit */
  133. static const u8 utmip_elastic_limit = 16;
  134. /* UTMIP High Speed Sync Start Delay */
  135. static const u8 utmip_hs_sync_start_delay = 9;
  136. /* Put the port into host mode */
  137. static void set_host_mode(struct fdt_usb *config)
  138. {
  139. /*
  140. * If we are an OTG port, check if remote host is driving VBus and
  141. * bail out in this case.
  142. */
  143. if (config->dr_mode == DR_MODE_OTG &&
  144. (readl(&config->reg->phy_vbus_sensors) & VBUS_VLD_STS))
  145. return;
  146. /*
  147. * If not driving, we set the GPIO to enable VBUS. We assume
  148. * that the pinmux is set up correctly for this.
  149. */
  150. if (fdt_gpio_isvalid(&config->vbus_gpio)) {
  151. fdtdec_setup_gpio(&config->vbus_gpio);
  152. gpio_direction_output(config->vbus_gpio.gpio,
  153. (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
  154. 0 : 1);
  155. debug("set_host_mode: GPIO %d %s\n", config->vbus_gpio.gpio,
  156. (config->vbus_gpio.flags & FDT_GPIO_ACTIVE_LOW) ?
  157. "low" : "high");
  158. }
  159. }
  160. void usbf_reset_controller(struct fdt_usb *config, struct usb_ctlr *usbctlr)
  161. {
  162. /* Reset the USB controller with 2us delay */
  163. reset_periph(config->periph_id, 2);
  164. /*
  165. * Set USB1_NO_LEGACY_MODE to 1, Registers are accessible under
  166. * base address
  167. */
  168. if (config->has_legacy_mode)
  169. setbits_le32(&usbctlr->usb1_legacy_ctrl, USB1_NO_LEGACY_MODE);
  170. /* Put UTMIP1/3 in reset */
  171. setbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
  172. /* Enable the UTMIP PHY */
  173. if (config->utmi)
  174. setbits_le32(&usbctlr->susp_ctrl, UTMIP_PHY_ENB);
  175. /*
  176. * TODO: where do we take the USB1 out of reset? The old code would
  177. * take USB3 out of reset, but not USB1. This code doesn't do either.
  178. */
  179. }
  180. /* set up the UTMI USB controller with the parameters provided */
  181. static int init_utmi_usb_controller(struct fdt_usb *config,
  182. struct usb_ctlr *usbctlr, const u32 timing[])
  183. {
  184. u32 val;
  185. int loop_count;
  186. clock_enable(config->periph_id);
  187. /* Reset the usb controller */
  188. usbf_reset_controller(config, usbctlr);
  189. /* Stop crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN low */
  190. clrbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
  191. /* Follow the crystal clock disable by >100ns delay */
  192. udelay(1);
  193. /*
  194. * To Use the A Session Valid for cable detection logic, VBUS_WAKEUP
  195. * mux must be switched to actually use a_sess_vld threshold.
  196. */
  197. if (fdt_gpio_isvalid(&config->vbus_gpio)) {
  198. clrsetbits_le32(&usbctlr->usb1_legacy_ctrl,
  199. VBUS_SENSE_CTL_MASK,
  200. VBUS_SENSE_CTL_A_SESS_VLD << VBUS_SENSE_CTL_SHIFT);
  201. }
  202. /*
  203. * PLL Delay CONFIGURATION settings. The following parameters control
  204. * the bring up of the plls.
  205. */
  206. val = readl(&usbctlr->utmip_misc_cfg1);
  207. clrsetbits_le32(&val, UTMIP_PLLU_STABLE_COUNT_MASK,
  208. timing[PARAM_STABLE_COUNT] << UTMIP_PLLU_STABLE_COUNT_SHIFT);
  209. clrsetbits_le32(&val, UTMIP_PLL_ACTIVE_DLY_COUNT_MASK,
  210. timing[PARAM_ACTIVE_DELAY_COUNT] <<
  211. UTMIP_PLL_ACTIVE_DLY_COUNT_SHIFT);
  212. writel(val, &usbctlr->utmip_misc_cfg1);
  213. /* Set PLL enable delay count and crystal frequency count */
  214. val = readl(&usbctlr->utmip_pll_cfg1);
  215. clrsetbits_le32(&val, UTMIP_PLLU_ENABLE_DLY_COUNT_MASK,
  216. timing[PARAM_ENABLE_DELAY_COUNT] <<
  217. UTMIP_PLLU_ENABLE_DLY_COUNT_SHIFT);
  218. clrsetbits_le32(&val, UTMIP_XTAL_FREQ_COUNT_MASK,
  219. timing[PARAM_XTAL_FREQ_COUNT] <<
  220. UTMIP_XTAL_FREQ_COUNT_SHIFT);
  221. writel(val, &usbctlr->utmip_pll_cfg1);
  222. /* Setting the tracking length time */
  223. clrsetbits_le32(&usbctlr->utmip_bias_cfg1,
  224. UTMIP_BIAS_PDTRK_COUNT_MASK,
  225. timing[PARAM_BIAS_TIME] << UTMIP_BIAS_PDTRK_COUNT_SHIFT);
  226. /* Program debounce time for VBUS to become valid */
  227. clrsetbits_le32(&usbctlr->utmip_debounce_cfg0,
  228. UTMIP_DEBOUNCE_CFG0_MASK,
  229. timing[PARAM_DEBOUNCE_A_TIME] << UTMIP_DEBOUNCE_CFG0_SHIFT);
  230. setbits_le32(&usbctlr->utmip_tx_cfg0, UTMIP_FS_PREAMBLE_J);
  231. /* Disable battery charge enabling bit */
  232. setbits_le32(&usbctlr->utmip_bat_chrg_cfg0, UTMIP_PD_CHRG);
  233. clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_XCVR_LSBIAS_SE);
  234. setbits_le32(&usbctlr->utmip_spare_cfg0, FUSE_SETUP_SEL);
  235. /*
  236. * Configure the UTMIP_IDLE_WAIT and UTMIP_ELASTIC_LIMIT
  237. * Setting these fields, together with default values of the
  238. * other fields, results in programming the registers below as
  239. * follows:
  240. * UTMIP_HSRX_CFG0 = 0x9168c000
  241. * UTMIP_HSRX_CFG1 = 0x13
  242. */
  243. /* Set PLL enable delay count and Crystal frequency count */
  244. val = readl(&usbctlr->utmip_hsrx_cfg0);
  245. clrsetbits_le32(&val, UTMIP_IDLE_WAIT_MASK,
  246. utmip_idle_wait_delay << UTMIP_IDLE_WAIT_SHIFT);
  247. clrsetbits_le32(&val, UTMIP_ELASTIC_LIMIT_MASK,
  248. utmip_elastic_limit << UTMIP_ELASTIC_LIMIT_SHIFT);
  249. writel(val, &usbctlr->utmip_hsrx_cfg0);
  250. /* Configure the UTMIP_HS_SYNC_START_DLY */
  251. clrsetbits_le32(&usbctlr->utmip_hsrx_cfg1,
  252. UTMIP_HS_SYNC_START_DLY_MASK,
  253. utmip_hs_sync_start_delay << UTMIP_HS_SYNC_START_DLY_SHIFT);
  254. /* Preceed the crystal clock disable by >100ns delay. */
  255. udelay(1);
  256. /* Resuscitate crystal clock by setting UTMIP_PHY_XTAL_CLOCKEN */
  257. setbits_le32(&usbctlr->utmip_misc_cfg1, UTMIP_PHY_XTAL_CLOCKEN);
  258. /* Finished the per-controller init. */
  259. /* De-assert UTMIP_RESET to bring out of reset. */
  260. clrbits_le32(&usbctlr->susp_ctrl, UTMIP_RESET);
  261. /* Wait for the phy clock to become valid in 100 ms */
  262. for (loop_count = 100000; loop_count != 0; loop_count--) {
  263. if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
  264. break;
  265. udelay(1);
  266. }
  267. if (!loop_count)
  268. return -1;
  269. /* Disable ICUSB FS/LS transceiver */
  270. clrbits_le32(&usbctlr->icusb_ctrl, IC_ENB1);
  271. /* Select UTMI parallel interface */
  272. clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK,
  273. PTS_UTMI << PTS_SHIFT);
  274. clrbits_le32(&usbctlr->port_sc1, STS);
  275. /* Deassert power down state */
  276. clrbits_le32(&usbctlr->utmip_xcvr_cfg0, UTMIP_FORCE_PD_POWERDOWN |
  277. UTMIP_FORCE_PD2_POWERDOWN | UTMIP_FORCE_PDZI_POWERDOWN);
  278. clrbits_le32(&usbctlr->utmip_xcvr_cfg1, UTMIP_FORCE_PDDISC_POWERDOWN |
  279. UTMIP_FORCE_PDCHRP_POWERDOWN | UTMIP_FORCE_PDDR_POWERDOWN);
  280. return 0;
  281. }
  282. #ifdef CONFIG_USB_ULPI
  283. /* if board file does not set a ULPI reference frequency we default to 24MHz */
  284. #ifndef CONFIG_ULPI_REF_CLK
  285. #define CONFIG_ULPI_REF_CLK 24000000
  286. #endif
  287. /* set up the ULPI USB controller with the parameters provided */
  288. static int init_ulpi_usb_controller(struct fdt_usb *config,
  289. struct usb_ctlr *usbctlr)
  290. {
  291. u32 val;
  292. int loop_count;
  293. struct ulpi_viewport ulpi_vp;
  294. /* set up ULPI reference clock on pllp_out4 */
  295. clock_enable(PERIPH_ID_DEV2_OUT);
  296. clock_set_pllout(CLOCK_ID_PERIPH, PLL_OUT4, CONFIG_ULPI_REF_CLK);
  297. /* reset ULPI phy */
  298. if (fdt_gpio_isvalid(&config->phy_reset_gpio)) {
  299. fdtdec_setup_gpio(&config->phy_reset_gpio);
  300. gpio_direction_output(config->phy_reset_gpio.gpio, 0);
  301. mdelay(5);
  302. gpio_set_value(config->phy_reset_gpio.gpio, 1);
  303. }
  304. /* Reset the usb controller */
  305. clock_enable(config->periph_id);
  306. usbf_reset_controller(config, usbctlr);
  307. /* enable pinmux bypass */
  308. setbits_le32(&usbctlr->ulpi_timing_ctrl_0,
  309. ULPI_CLKOUT_PINMUX_BYP | ULPI_OUTPUT_PINMUX_BYP);
  310. /* Select ULPI parallel interface */
  311. clrsetbits_le32(&usbctlr->port_sc1, PTS_MASK, PTS_ULPI << PTS_SHIFT);
  312. /* enable ULPI transceiver */
  313. setbits_le32(&usbctlr->susp_ctrl, ULPI_PHY_ENB);
  314. /* configure ULPI transceiver timings */
  315. val = 0;
  316. writel(val, &usbctlr->ulpi_timing_ctrl_1);
  317. val |= ULPI_DATA_TRIMMER_SEL(4);
  318. val |= ULPI_STPDIRNXT_TRIMMER_SEL(4);
  319. val |= ULPI_DIR_TRIMMER_SEL(4);
  320. writel(val, &usbctlr->ulpi_timing_ctrl_1);
  321. udelay(10);
  322. val |= ULPI_DATA_TRIMMER_LOAD;
  323. val |= ULPI_STPDIRNXT_TRIMMER_LOAD;
  324. val |= ULPI_DIR_TRIMMER_LOAD;
  325. writel(val, &usbctlr->ulpi_timing_ctrl_1);
  326. /* set up phy for host operation with external vbus supply */
  327. ulpi_vp.port_num = 0;
  328. ulpi_vp.viewport_addr = (u32)&usbctlr->ulpi_viewport;
  329. if (ulpi_init(&ulpi_vp)) {
  330. printf("Tegra ULPI viewport init failed\n");
  331. return -1;
  332. }
  333. ulpi_set_vbus(&ulpi_vp, 1, 1);
  334. ulpi_set_vbus_indicator(&ulpi_vp, 1, 1, 0);
  335. /* enable wakeup events */
  336. setbits_le32(&usbctlr->port_sc1, WKCN | WKDS | WKOC);
  337. /* Enable and wait for the phy clock to become valid in 100 ms */
  338. setbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
  339. for (loop_count = 100000; loop_count != 0; loop_count--) {
  340. if (readl(&usbctlr->susp_ctrl) & USB_PHY_CLK_VALID)
  341. break;
  342. udelay(1);
  343. }
  344. if (!loop_count)
  345. return -1;
  346. clrbits_le32(&usbctlr->susp_ctrl, USB_SUSP_CLR);
  347. return 0;
  348. }
  349. #else
  350. static int init_ulpi_usb_controller(struct fdt_usb *config,
  351. struct usb_ctlr *usbctlr)
  352. {
  353. printf("No code to set up ULPI controller, please enable"
  354. "CONFIG_USB_ULPI and CONFIG_USB_ULPI_VIEWPORT");
  355. return -1;
  356. }
  357. #endif
  358. static void config_clock(const u32 timing[])
  359. {
  360. clock_start_pll(CLOCK_ID_USB,
  361. timing[PARAM_DIVM], timing[PARAM_DIVN], timing[PARAM_DIVP],
  362. timing[PARAM_CPCON], timing[PARAM_LFCON]);
  363. }
  364. /**
  365. * Add a new USB port to the list of available ports.
  366. *
  367. * @param config USB port configuration
  368. * @return 0 if ok, -1 if error (too many ports)
  369. */
  370. static int add_port(struct fdt_usb *config, const u32 timing[])
  371. {
  372. struct usb_ctlr *usbctlr = config->reg;
  373. if (port_count == USB_PORTS_MAX) {
  374. printf("tegrausb: Cannot register more than %d ports\n",
  375. USB_PORTS_MAX);
  376. return -1;
  377. }
  378. if (config->utmi && init_utmi_usb_controller(config, usbctlr, timing)) {
  379. printf("tegrausb: Cannot init port\n");
  380. return -1;
  381. }
  382. if (config->ulpi && init_ulpi_usb_controller(config, usbctlr)) {
  383. printf("tegrausb: Cannot init port\n");
  384. return -1;
  385. }
  386. port[port_count++] = *config;
  387. return 0;
  388. }
  389. int tegrausb_start_port(int portnum, u32 *hccr, u32 *hcor)
  390. {
  391. struct usb_ctlr *usbctlr;
  392. if (portnum >= port_count)
  393. return -1;
  394. set_host_mode(&port[portnum]);
  395. usbctlr = port[portnum].reg;
  396. *hccr = (u32)&usbctlr->cap_length;
  397. *hcor = (u32)&usbctlr->usb_cmd;
  398. return 0;
  399. }
  400. int tegrausb_stop_port(int portnum)
  401. {
  402. struct usb_ctlr *usbctlr;
  403. usbctlr = port[portnum].reg;
  404. /* Stop controller */
  405. writel(0, &usbctlr->usb_cmd);
  406. udelay(1000);
  407. /* Initiate controller reset */
  408. writel(2, &usbctlr->usb_cmd);
  409. udelay(1000);
  410. return 0;
  411. }
  412. int fdt_decode_usb(const void *blob, int node, unsigned osc_frequency_mhz,
  413. struct fdt_usb *config)
  414. {
  415. const char *phy, *mode;
  416. config->reg = (struct usb_ctlr *)fdtdec_get_addr(blob, node, "reg");
  417. mode = fdt_getprop(blob, node, "dr_mode", NULL);
  418. if (mode) {
  419. if (0 == strcmp(mode, "host"))
  420. config->dr_mode = DR_MODE_HOST;
  421. else if (0 == strcmp(mode, "peripheral"))
  422. config->dr_mode = DR_MODE_DEVICE;
  423. else if (0 == strcmp(mode, "otg"))
  424. config->dr_mode = DR_MODE_OTG;
  425. else {
  426. debug("%s: Cannot decode dr_mode '%s'\n", __func__,
  427. mode);
  428. return -FDT_ERR_NOTFOUND;
  429. }
  430. } else {
  431. config->dr_mode = DR_MODE_HOST;
  432. }
  433. phy = fdt_getprop(blob, node, "phy_type", NULL);
  434. config->utmi = phy && 0 == strcmp("utmi", phy);
  435. config->ulpi = phy && 0 == strcmp("ulpi", phy);
  436. config->enabled = fdtdec_get_is_enabled(blob, node);
  437. config->has_legacy_mode = fdtdec_get_bool(blob, node,
  438. "nvidia,has-legacy-mode");
  439. config->periph_id = clock_decode_periph_id(blob, node);
  440. if (config->periph_id == PERIPH_ID_NONE) {
  441. debug("%s: Missing/invalid peripheral ID\n", __func__);
  442. return -FDT_ERR_NOTFOUND;
  443. }
  444. fdtdec_decode_gpio(blob, node, "nvidia,vbus-gpio", &config->vbus_gpio);
  445. fdtdec_decode_gpio(blob, node, "nvidia,phy-reset-gpio",
  446. &config->phy_reset_gpio);
  447. debug("enabled=%d, legacy_mode=%d, utmi=%d, ulpi=%d, periph_id=%d, "
  448. "vbus=%d, phy_reset=%d, dr_mode=%d\n",
  449. config->enabled, config->has_legacy_mode, config->utmi,
  450. config->ulpi, config->periph_id, config->vbus_gpio.gpio,
  451. config->phy_reset_gpio.gpio, config->dr_mode);
  452. return 0;
  453. }
  454. int board_usb_init(const void *blob)
  455. {
  456. struct fdt_usb config;
  457. unsigned osc_freq = clock_get_rate(CLOCK_ID_OSC);
  458. enum clock_osc_freq freq;
  459. int node_list[USB_PORTS_MAX];
  460. int node, count, i;
  461. /* Set up the USB clocks correctly based on our oscillator frequency */
  462. freq = clock_get_osc_freq();
  463. config_clock(usb_pll[freq]);
  464. /* count may return <0 on error */
  465. count = fdtdec_find_aliases_for_id(blob, "usb",
  466. COMPAT_NVIDIA_TEGRA20_USB, node_list, USB_PORTS_MAX);
  467. for (i = 0; i < count; i++) {
  468. debug("USB %d: ", i);
  469. node = node_list[i];
  470. if (!node)
  471. continue;
  472. if (fdt_decode_usb(blob, node, osc_freq, &config)) {
  473. debug("Cannot decode USB node %s\n",
  474. fdt_get_name(blob, node, NULL));
  475. return -1;
  476. }
  477. if (add_port(&config, usb_pll[freq]))
  478. return -1;
  479. set_host_mode(&config);
  480. }
  481. return 0;
  482. }