clocks.c 16 KB

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  1. /*
  2. *
  3. * Clock initialization for OMAP5
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. * Sricharan R <r.sricharan@ti.com>
  10. *
  11. * Based on previous work by:
  12. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  13. * Rajendra Nayak <rnayak@ti.com>
  14. *
  15. * See file CREDITS for list of people who contributed to this
  16. * project.
  17. *
  18. * This program is free software; you can redistribute it and/or
  19. * modify it under the terms of the GNU General Public License as
  20. * published by the Free Software Foundation; either version 2 of
  21. * the License, or (at your option) any later version.
  22. *
  23. * This program is distributed in the hope that it will be useful,
  24. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  25. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  26. * GNU General Public License for more details.
  27. *
  28. * You should have received a copy of the GNU General Public License
  29. * along with this program; if not, write to the Free Software
  30. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  31. * MA 02111-1307 USA
  32. */
  33. #include <common.h>
  34. #include <asm/omap_common.h>
  35. #include <asm/arch/clocks.h>
  36. #include <asm/arch/sys_proto.h>
  37. #include <asm/utils.h>
  38. #include <asm/omap_gpio.h>
  39. #ifndef CONFIG_SPL_BUILD
  40. /*
  41. * printing to console doesn't work unless
  42. * this code is executed from SPL
  43. */
  44. #define printf(fmt, args...)
  45. #define puts(s)
  46. #endif
  47. struct omap5_prcm_regs *const prcm = (struct omap5_prcm_regs *)0x4A004100;
  48. const u32 sys_clk_array[8] = {
  49. 12000000, /* 12 MHz */
  50. 0, /* NA */
  51. 16800000, /* 16.8 MHz */
  52. 19200000, /* 19.2 MHz */
  53. 26000000, /* 26 MHz */
  54. 0, /* NA */
  55. 38400000, /* 38.4 MHz */
  56. };
  57. static const struct dpll_params mpu_dpll_params_1_5ghz[NUM_SYS_CLKS] = {
  58. {125, 0, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  59. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  60. {625, 6, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  61. {625, 7, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  62. {750, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  63. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  64. {625, 15, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  65. };
  66. static const struct dpll_params mpu_dpll_params_2ghz[NUM_SYS_CLKS] = {
  67. {500, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  68. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  69. {2024, 16, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  70. {625, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  71. {1000, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  72. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  73. {625, 11, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  74. };
  75. static const struct dpll_params mpu_dpll_params_1100mhz[NUM_SYS_CLKS] = {
  76. {275, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  77. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  78. {1375, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  79. {1375, 23, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  80. {550, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  81. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  82. {1375, 47, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  83. };
  84. static const struct dpll_params mpu_dpll_params_800mhz[NUM_SYS_CLKS] = {
  85. {200, 2, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  86. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  87. {1000, 20, 1, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  88. {375, 8, 1, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  89. {400, 12, 1, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  90. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  91. {375, 17, 1, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  92. };
  93. static const struct dpll_params mpu_dpll_params_400mhz[NUM_SYS_CLKS] = {
  94. {200, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  95. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  96. {1000, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  97. {375, 8, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  98. {400, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  99. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  100. {375, 17, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  101. };
  102. static const struct dpll_params mpu_dpll_params_550mhz[NUM_SYS_CLKS] = {
  103. {275, 2, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  104. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  105. {1375, 20, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  106. {1375, 23, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  107. {550, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  108. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  109. {1375, 47, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  110. };
  111. static const struct dpll_params
  112. core_dpll_params_2128mhz_ddr532[NUM_SYS_CLKS] = {
  113. {266, 2, 2, 5, 8, 4, 62, 5, 5, 7}, /* 12 MHz */
  114. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  115. {570, 8, 2, 5, 8, 4, 62, 5, 5, 7}, /* 16.8 MHz */
  116. {665, 11, 2, 5, 8, 4, 62, 5, 5, 7}, /* 19.2 MHz */
  117. {532, 12, 2, 5, 8, 4, 62, 5, 5, 7}, /* 26 MHz */
  118. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  119. {665, 23, 2, 5, 8, 4, 62, 5, 5, 7} /* 38.4 MHz */
  120. };
  121. static const struct dpll_params
  122. core_dpll_params_2128mhz_ddr266[NUM_SYS_CLKS] = {
  123. {266, 2, 4, 5, 8, 8, 62, 10, 10, 14}, /* 12 MHz */
  124. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  125. {570, 8, 4, 5, 8, 8, 62, 10, 10, 14}, /* 16.8 MHz */
  126. {665, 11, 4, 5, 8, 8, 62, 10, 10, 14}, /* 19.2 MHz */
  127. {532, 12, 4, 8, 8, 8, 62, 10, 10, 14}, /* 26 MHz */
  128. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  129. {665, 23, 4, 8, 8, 8, 62, 10, 10, 14} /* 38.4 MHz */
  130. };
  131. static const struct dpll_params per_dpll_params_768mhz[NUM_SYS_CLKS] = {
  132. {32, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 12 MHz */
  133. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  134. {160, 6, 4, 3, 6, 4, -1, 2, -1, -1}, /* 16.8 MHz */
  135. {20, 0, 4, 3, 6, 4, -1, 2, -1, -1}, /* 19.2 MHz */
  136. {192, 12, 4, 3, 6, 4, -1, 2, -1, -1}, /* 26 MHz */
  137. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  138. {10, 0, 4, 3, 6, 4, -1, 2, -1, -1} /* 38.4 MHz */
  139. };
  140. static const struct dpll_params iva_dpll_params_2330mhz[NUM_SYS_CLKS] = {
  141. {1165, 11, -1, -1, 5, 6, -1, -1, -1, -1}, /* 12 MHz */
  142. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  143. {2011, 28, -1, -1, 5, 6, -1, -1, -1, -1}, /* 16.8 MHz */
  144. {1881, 30, -1, -1, 5, 6, -1, -1, -1, -1}, /* 19.2 MHz */
  145. {1165, 25, -1, -1, 5, 6, -1, -1, -1, -1}, /* 26 MHz */
  146. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  147. {1972, 64, -1, -1, 5, 6, -1, -1, -1, -1} /* 38.4 MHz */
  148. };
  149. /* ABE M & N values with sys_clk as source */
  150. static const struct dpll_params
  151. abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
  152. {49, 5, 1, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  153. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  154. {35, 5, 1, 1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  155. {46, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  156. {34, 8, 1, 1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  157. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  158. {64, 24, 1, 1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  159. };
  160. /* ABE M & N values with 32K clock as source */
  161. static const struct dpll_params abe_dpll_params_32k_196608khz = {
  162. 750, 0, 1, 1, -1, -1, -1, -1, -1, -1
  163. };
  164. static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
  165. {400, 4, 2, -1, -1, -1, -1, -1, -1, -1}, /* 12 MHz */
  166. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 13 MHz */
  167. {400, 6, 2, -1, -1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  168. {400, 7, 2, -1, -1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  169. {480, 12, 2, -1, -1, -1, -1, -1, -1, -1}, /* 26 MHz */
  170. {-1, -1, -1, -1, -1, -1, -1, -1, -1, -1}, /* 27 MHz */
  171. {400, 15, 2, -1, -1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  172. };
  173. void setup_post_dividers(u32 *const base, const struct dpll_params *params)
  174. {
  175. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  176. /* Setup post-dividers */
  177. if (params->m2 >= 0)
  178. writel(params->m2, &dpll_regs->cm_div_m2_dpll);
  179. if (params->m3 >= 0)
  180. writel(params->m3, &dpll_regs->cm_div_m3_dpll);
  181. if (params->h11 >= 0)
  182. writel(params->h11, &dpll_regs->cm_div_h11_dpll);
  183. if (params->h12 >= 0)
  184. writel(params->h12, &dpll_regs->cm_div_h12_dpll);
  185. if (params->h13 >= 0)
  186. writel(params->h13, &dpll_regs->cm_div_h13_dpll);
  187. if (params->h14 >= 0)
  188. writel(params->h14, &dpll_regs->cm_div_h14_dpll);
  189. if (params->h22 >= 0)
  190. writel(params->h22, &dpll_regs->cm_div_h22_dpll);
  191. if (params->h23 >= 0)
  192. writel(params->h23, &dpll_regs->cm_div_h23_dpll);
  193. }
  194. const struct dpll_params *get_mpu_dpll_params(void)
  195. {
  196. u32 sysclk_ind = get_sys_clk_index();
  197. return &mpu_dpll_params_800mhz[sysclk_ind];
  198. }
  199. const struct dpll_params *get_core_dpll_params(void)
  200. {
  201. u32 sysclk_ind = get_sys_clk_index();
  202. /* Configuring the DDR to be at 532mhz */
  203. return &core_dpll_params_2128mhz_ddr532[sysclk_ind];
  204. }
  205. const struct dpll_params *get_per_dpll_params(void)
  206. {
  207. u32 sysclk_ind = get_sys_clk_index();
  208. return &per_dpll_params_768mhz[sysclk_ind];
  209. }
  210. const struct dpll_params *get_iva_dpll_params(void)
  211. {
  212. u32 sysclk_ind = get_sys_clk_index();
  213. return &iva_dpll_params_2330mhz[sysclk_ind];
  214. }
  215. const struct dpll_params *get_usb_dpll_params(void)
  216. {
  217. u32 sysclk_ind = get_sys_clk_index();
  218. return &usb_dpll_params_1920mhz[sysclk_ind];
  219. }
  220. const struct dpll_params *get_abe_dpll_params(void)
  221. {
  222. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  223. u32 sysclk_ind = get_sys_clk_index();
  224. return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
  225. #else
  226. return &abe_dpll_params_32k_196608khz;
  227. #endif
  228. }
  229. /*
  230. * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
  231. * We set the maximum voltages allowed here because Smart-Reflex is not
  232. * enabled in bootloader. Voltage initialization in the kernel will set
  233. * these to the nominal values after enabling Smart-Reflex
  234. */
  235. void scale_vcores(void)
  236. {
  237. u32 volt_core, volt_mpu, volt_mm;
  238. omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
  239. /* Palmas settings */
  240. if (omap_revision() != OMAP5432_ES1_0) {
  241. volt_core = VDD_CORE;
  242. volt_mpu = VDD_MPU;
  243. volt_mm = VDD_MM;
  244. } else {
  245. volt_core = VDD_CORE_5432;
  246. volt_mpu = VDD_MPU_5432;
  247. volt_mm = VDD_MM_5432;
  248. }
  249. do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core);
  250. do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu);
  251. do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm);
  252. if (omap_revision() == OMAP5432_ES1_0) {
  253. /* Configure LDO SRAM "magic" bits */
  254. writel(2, &prcm->prm_sldo_core_setup);
  255. writel(2, &prcm->prm_sldo_mpu_setup);
  256. writel(2, &prcm->prm_sldo_mm_setup);
  257. }
  258. }
  259. u32 get_offset_code(u32 volt_offset)
  260. {
  261. u32 offset_code, step = 10000; /* 10 mV represented in uV */
  262. volt_offset -= PALMAS_SMPS_BASE_VOLT_UV;
  263. offset_code = (volt_offset + step - 1) / step;
  264. /*
  265. * Offset codes 1-6 all give the base voltage in Palmas
  266. * Offset code 0 switches OFF the SMPS
  267. */
  268. return offset_code + 6;
  269. }
  270. /*
  271. * Enable essential clock domains, modules and
  272. * do some additional special settings needed
  273. */
  274. void enable_basic_clocks(void)
  275. {
  276. u32 *const clk_domains_essential[] = {
  277. &prcm->cm_l4per_clkstctrl,
  278. &prcm->cm_l3init_clkstctrl,
  279. &prcm->cm_memif_clkstctrl,
  280. &prcm->cm_l4cfg_clkstctrl,
  281. 0
  282. };
  283. u32 *const clk_modules_hw_auto_essential[] = {
  284. &prcm->cm_l3_2_gpmc_clkctrl,
  285. &prcm->cm_memif_emif_1_clkctrl,
  286. &prcm->cm_memif_emif_2_clkctrl,
  287. &prcm->cm_l4cfg_l4_cfg_clkctrl,
  288. &prcm->cm_wkup_gpio1_clkctrl,
  289. &prcm->cm_l4per_gpio2_clkctrl,
  290. &prcm->cm_l4per_gpio3_clkctrl,
  291. &prcm->cm_l4per_gpio4_clkctrl,
  292. &prcm->cm_l4per_gpio5_clkctrl,
  293. &prcm->cm_l4per_gpio6_clkctrl,
  294. 0
  295. };
  296. u32 *const clk_modules_explicit_en_essential[] = {
  297. &prcm->cm_wkup_gptimer1_clkctrl,
  298. &prcm->cm_l3init_hsmmc1_clkctrl,
  299. &prcm->cm_l3init_hsmmc2_clkctrl,
  300. &prcm->cm_l4per_gptimer2_clkctrl,
  301. &prcm->cm_wkup_wdtimer2_clkctrl,
  302. &prcm->cm_l4per_uart3_clkctrl,
  303. &prcm->cm_l4per_i2c1_clkctrl,
  304. 0
  305. };
  306. /* Enable optional additional functional clock for GPIO4 */
  307. setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
  308. GPIO4_CLKCTRL_OPTFCLKEN_MASK);
  309. /* Enable 96 MHz clock for MMC1 & MMC2 */
  310. setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
  311. HSMMC_CLKCTRL_CLKSEL_MASK);
  312. setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
  313. HSMMC_CLKCTRL_CLKSEL_MASK);
  314. /* Set the correct clock dividers for mmc */
  315. setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
  316. HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
  317. setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
  318. HSMMC_CLKCTRL_CLKSEL_DIV_MASK);
  319. /* Select 32KHz clock as the source of GPTIMER1 */
  320. setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
  321. GPTIMER1_CLKCTRL_CLKSEL_MASK);
  322. do_enable_clocks(clk_domains_essential,
  323. clk_modules_hw_auto_essential,
  324. clk_modules_explicit_en_essential,
  325. 1);
  326. /* Select 384Mhz for GPU as its the POR for ES1.0 */
  327. setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
  328. CLKSEL_GPU_HYD_GCLK_MASK);
  329. setbits_le32(&prcm->cm_sgx_sgx_clkctrl,
  330. CLKSEL_GPU_CORE_GCLK_MASK);
  331. /* Enable SCRM OPT clocks for PER and CORE dpll */
  332. setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
  333. OPTFCLKEN_SCRM_PER_MASK);
  334. setbits_le32(&prcm->cm_wkupaon_scrm_clkctrl,
  335. OPTFCLKEN_SCRM_CORE_MASK);
  336. }
  337. void enable_basic_uboot_clocks(void)
  338. {
  339. u32 *const clk_domains_essential[] = {
  340. 0
  341. };
  342. u32 *const clk_modules_hw_auto_essential[] = {
  343. 0
  344. };
  345. u32 *const clk_modules_explicit_en_essential[] = {
  346. &prcm->cm_l4per_mcspi1_clkctrl,
  347. &prcm->cm_l4per_i2c2_clkctrl,
  348. &prcm->cm_l4per_i2c3_clkctrl,
  349. &prcm->cm_l4per_i2c4_clkctrl,
  350. &prcm->cm_l3init_hsusbtll_clkctrl,
  351. &prcm->cm_l3init_hsusbhost_clkctrl,
  352. &prcm->cm_l3init_fsusb_clkctrl,
  353. 0
  354. };
  355. do_enable_clocks(clk_domains_essential,
  356. clk_modules_hw_auto_essential,
  357. clk_modules_explicit_en_essential,
  358. 1);
  359. }
  360. /*
  361. * Enable non-essential clock domains, modules and
  362. * do some additional special settings needed
  363. */
  364. void enable_non_essential_clocks(void)
  365. {
  366. u32 *const clk_domains_non_essential[] = {
  367. &prcm->cm_mpu_m3_clkstctrl,
  368. &prcm->cm_ivahd_clkstctrl,
  369. &prcm->cm_dsp_clkstctrl,
  370. &prcm->cm_dss_clkstctrl,
  371. &prcm->cm_sgx_clkstctrl,
  372. &prcm->cm1_abe_clkstctrl,
  373. &prcm->cm_c2c_clkstctrl,
  374. &prcm->cm_cam_clkstctrl,
  375. &prcm->cm_dss_clkstctrl,
  376. &prcm->cm_sdma_clkstctrl,
  377. 0
  378. };
  379. u32 *const clk_modules_hw_auto_non_essential[] = {
  380. &prcm->cm_mpu_m3_mpu_m3_clkctrl,
  381. &prcm->cm_ivahd_ivahd_clkctrl,
  382. &prcm->cm_ivahd_sl2_clkctrl,
  383. &prcm->cm_dsp_dsp_clkctrl,
  384. &prcm->cm_l3instr_l3_3_clkctrl,
  385. &prcm->cm_l3instr_l3_instr_clkctrl,
  386. &prcm->cm_l3instr_intrconn_wp1_clkctrl,
  387. &prcm->cm_l3init_hsi_clkctrl,
  388. &prcm->cm_l4per_hdq1w_clkctrl,
  389. 0
  390. };
  391. u32 *const clk_modules_explicit_en_non_essential[] = {
  392. &prcm->cm1_abe_aess_clkctrl,
  393. &prcm->cm1_abe_pdm_clkctrl,
  394. &prcm->cm1_abe_dmic_clkctrl,
  395. &prcm->cm1_abe_mcasp_clkctrl,
  396. &prcm->cm1_abe_mcbsp1_clkctrl,
  397. &prcm->cm1_abe_mcbsp2_clkctrl,
  398. &prcm->cm1_abe_mcbsp3_clkctrl,
  399. &prcm->cm1_abe_slimbus_clkctrl,
  400. &prcm->cm1_abe_timer5_clkctrl,
  401. &prcm->cm1_abe_timer6_clkctrl,
  402. &prcm->cm1_abe_timer7_clkctrl,
  403. &prcm->cm1_abe_timer8_clkctrl,
  404. &prcm->cm1_abe_wdt3_clkctrl,
  405. &prcm->cm_l4per_gptimer9_clkctrl,
  406. &prcm->cm_l4per_gptimer10_clkctrl,
  407. &prcm->cm_l4per_gptimer11_clkctrl,
  408. &prcm->cm_l4per_gptimer3_clkctrl,
  409. &prcm->cm_l4per_gptimer4_clkctrl,
  410. &prcm->cm_l4per_mcspi2_clkctrl,
  411. &prcm->cm_l4per_mcspi3_clkctrl,
  412. &prcm->cm_l4per_mcspi4_clkctrl,
  413. &prcm->cm_l4per_mmcsd3_clkctrl,
  414. &prcm->cm_l4per_mmcsd4_clkctrl,
  415. &prcm->cm_l4per_mmcsd5_clkctrl,
  416. &prcm->cm_l4per_uart1_clkctrl,
  417. &prcm->cm_l4per_uart2_clkctrl,
  418. &prcm->cm_l4per_uart4_clkctrl,
  419. &prcm->cm_wkup_keyboard_clkctrl,
  420. &prcm->cm_wkup_wdtimer2_clkctrl,
  421. &prcm->cm_cam_iss_clkctrl,
  422. &prcm->cm_cam_fdif_clkctrl,
  423. &prcm->cm_dss_dss_clkctrl,
  424. &prcm->cm_sgx_sgx_clkctrl,
  425. 0
  426. };
  427. /* Enable optional functional clock for ISS */
  428. setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
  429. /* Enable all optional functional clocks of DSS */
  430. setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
  431. do_enable_clocks(clk_domains_non_essential,
  432. clk_modules_hw_auto_non_essential,
  433. clk_modules_explicit_en_non_essential,
  434. 0);
  435. /* Put camera module in no sleep mode */
  436. clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
  437. CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
  438. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  439. }