clocks.c 15 KB

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  1. /*
  2. *
  3. * Clock initialization for OMAP4
  4. *
  5. * (C) Copyright 2010
  6. * Texas Instruments, <www.ti.com>
  7. *
  8. * Aneesh V <aneesh@ti.com>
  9. *
  10. * Based on previous work by:
  11. * Santosh Shilimkar <santosh.shilimkar@ti.com>
  12. * Rajendra Nayak <rnayak@ti.com>
  13. *
  14. * See file CREDITS for list of people who contributed to this
  15. * project.
  16. *
  17. * This program is free software; you can redistribute it and/or
  18. * modify it under the terms of the GNU General Public License as
  19. * published by the Free Software Foundation; either version 2 of
  20. * the License, or (at your option) any later version.
  21. *
  22. * This program is distributed in the hope that it will be useful,
  23. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  24. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  25. * GNU General Public License for more details.
  26. *
  27. * You should have received a copy of the GNU General Public License
  28. * along with this program; if not, write to the Free Software
  29. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  30. * MA 02111-1307 USA
  31. */
  32. #include <common.h>
  33. #include <asm/omap_common.h>
  34. #include <asm/gpio.h>
  35. #include <asm/arch/clocks.h>
  36. #include <asm/arch/sys_proto.h>
  37. #include <asm/utils.h>
  38. #include <asm/omap_gpio.h>
  39. #ifndef CONFIG_SPL_BUILD
  40. /*
  41. * printing to console doesn't work unless
  42. * this code is executed from SPL
  43. */
  44. #define printf(fmt, args...)
  45. #define puts(s)
  46. #endif /* !CONFIG_SPL_BUILD */
  47. struct omap4_prcm_regs *const prcm = (struct omap4_prcm_regs *)0x4A004100;
  48. const u32 sys_clk_array[8] = {
  49. 12000000, /* 12 MHz */
  50. 13000000, /* 13 MHz */
  51. 16800000, /* 16.8 MHz */
  52. 19200000, /* 19.2 MHz */
  53. 26000000, /* 26 MHz */
  54. 27000000, /* 27 MHz */
  55. 38400000, /* 38.4 MHz */
  56. };
  57. /*
  58. * The M & N values in the following tables are created using the
  59. * following tool:
  60. * tools/omap/clocks_get_m_n.c
  61. * Please use this tool for creating the table for any new frequency.
  62. */
  63. /* dpll locked at 1400 MHz MPU clk at 700 MHz(OPP100) - DCC OFF */
  64. static const struct dpll_params mpu_dpll_params_1400mhz[NUM_SYS_CLKS] = {
  65. {175, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
  66. {700, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
  67. {125, 2, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  68. {401, 10, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  69. {350, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
  70. {700, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
  71. {638, 34, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  72. };
  73. /* dpll locked at 1584 MHz - MPU clk at 792 MHz(OPP Turbo 4430) */
  74. static const struct dpll_params mpu_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  75. {200, 2, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
  76. {800, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
  77. {619, 12, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  78. {125, 2, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  79. {400, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
  80. {800, 26, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
  81. {125, 5, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  82. };
  83. /* dpll locked at 1200 MHz - MPU clk at 600 MHz */
  84. static const struct dpll_params mpu_dpll_params_1200mhz[NUM_SYS_CLKS] = {
  85. {50, 0, 1, -1, -1, -1, -1, -1}, /* 12 MHz */
  86. {600, 12, 1, -1, -1, -1, -1, -1}, /* 13 MHz */
  87. {250, 6, 1, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  88. {125, 3, 1, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  89. {300, 12, 1, -1, -1, -1, -1, -1}, /* 26 MHz */
  90. {200, 8, 1, -1, -1, -1, -1, -1}, /* 27 MHz */
  91. {125, 7, 1, -1, -1, -1, -1, -1} /* 38.4 MHz */
  92. };
  93. static const struct dpll_params core_dpll_params_1600mhz[NUM_SYS_CLKS] = {
  94. {200, 2, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
  95. {800, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
  96. {619, 12, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
  97. {125, 2, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
  98. {400, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
  99. {800, 26, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
  100. {125, 5, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
  101. };
  102. static const struct dpll_params core_dpll_params_es1_1524mhz[NUM_SYS_CLKS] = {
  103. {127, 1, 1, 5, 8, 4, 6, 5}, /* 12 MHz */
  104. {762, 12, 1, 5, 8, 4, 6, 5}, /* 13 MHz */
  105. {635, 13, 1, 5, 8, 4, 6, 5}, /* 16.8 MHz */
  106. {635, 15, 1, 5, 8, 4, 6, 5}, /* 19.2 MHz */
  107. {381, 12, 1, 5, 8, 4, 6, 5}, /* 26 MHz */
  108. {254, 8, 1, 5, 8, 4, 6, 5}, /* 27 MHz */
  109. {496, 24, 1, 5, 8, 4, 6, 5} /* 38.4 MHz */
  110. };
  111. static const struct dpll_params
  112. core_dpll_params_es2_1600mhz_ddr200mhz[NUM_SYS_CLKS] = {
  113. {200, 2, 2, 5, 8, 4, 6, 5}, /* 12 MHz */
  114. {800, 12, 2, 5, 8, 4, 6, 5}, /* 13 MHz */
  115. {619, 12, 2, 5, 8, 4, 6, 5}, /* 16.8 MHz */
  116. {125, 2, 2, 5, 8, 4, 6, 5}, /* 19.2 MHz */
  117. {400, 12, 2, 5, 8, 4, 6, 5}, /* 26 MHz */
  118. {800, 26, 2, 5, 8, 4, 6, 5}, /* 27 MHz */
  119. {125, 5, 2, 5, 8, 4, 6, 5} /* 38.4 MHz */
  120. };
  121. static const struct dpll_params per_dpll_params_1536mhz[NUM_SYS_CLKS] = {
  122. {64, 0, 8, 6, 12, 9, 4, 5}, /* 12 MHz */
  123. {768, 12, 8, 6, 12, 9, 4, 5}, /* 13 MHz */
  124. {320, 6, 8, 6, 12, 9, 4, 5}, /* 16.8 MHz */
  125. {40, 0, 8, 6, 12, 9, 4, 5}, /* 19.2 MHz */
  126. {384, 12, 8, 6, 12, 9, 4, 5}, /* 26 MHz */
  127. {256, 8, 8, 6, 12, 9, 4, 5}, /* 27 MHz */
  128. {20, 0, 8, 6, 12, 9, 4, 5} /* 38.4 MHz */
  129. };
  130. static const struct dpll_params iva_dpll_params_1862mhz[NUM_SYS_CLKS] = {
  131. {931, 11, -1, -1, 4, 7, -1, -1}, /* 12 MHz */
  132. {931, 12, -1, -1, 4, 7, -1, -1}, /* 13 MHz */
  133. {665, 11, -1, -1, 4, 7, -1, -1}, /* 16.8 MHz */
  134. {727, 14, -1, -1, 4, 7, -1, -1}, /* 19.2 MHz */
  135. {931, 25, -1, -1, 4, 7, -1, -1}, /* 26 MHz */
  136. {931, 26, -1, -1, 4, 7, -1, -1}, /* 27 MHz */
  137. {291, 11, -1, -1, 4, 7, -1, -1} /* 38.4 MHz */
  138. };
  139. /* ABE M & N values with sys_clk as source */
  140. static const struct dpll_params
  141. abe_dpll_params_sysclk_196608khz[NUM_SYS_CLKS] = {
  142. {49, 5, 1, 1, -1, -1, -1, -1}, /* 12 MHz */
  143. {68, 8, 1, 1, -1, -1, -1, -1}, /* 13 MHz */
  144. {35, 5, 1, 1, -1, -1, -1, -1}, /* 16.8 MHz */
  145. {46, 8, 1, 1, -1, -1, -1, -1}, /* 19.2 MHz */
  146. {34, 8, 1, 1, -1, -1, -1, -1}, /* 26 MHz */
  147. {29, 7, 1, 1, -1, -1, -1, -1}, /* 27 MHz */
  148. {64, 24, 1, 1, -1, -1, -1, -1} /* 38.4 MHz */
  149. };
  150. /* ABE M & N values with 32K clock as source */
  151. static const struct dpll_params abe_dpll_params_32k_196608khz = {
  152. 750, 0, 1, 1, -1, -1, -1, -1
  153. };
  154. static const struct dpll_params usb_dpll_params_1920mhz[NUM_SYS_CLKS] = {
  155. {80, 0, 2, -1, -1, -1, -1, -1}, /* 12 MHz */
  156. {960, 12, 2, -1, -1, -1, -1, -1}, /* 13 MHz */
  157. {400, 6, 2, -1, -1, -1, -1, -1}, /* 16.8 MHz */
  158. {50, 0, 2, -1, -1, -1, -1, -1}, /* 19.2 MHz */
  159. {480, 12, 2, -1, -1, -1, -1, -1}, /* 26 MHz */
  160. {320, 8, 2, -1, -1, -1, -1, -1}, /* 27 MHz */
  161. {25, 0, 2, -1, -1, -1, -1, -1} /* 38.4 MHz */
  162. };
  163. void setup_post_dividers(u32 *const base, const struct dpll_params *params)
  164. {
  165. struct dpll_regs *const dpll_regs = (struct dpll_regs *)base;
  166. /* Setup post-dividers */
  167. if (params->m2 >= 0)
  168. writel(params->m2, &dpll_regs->cm_div_m2_dpll);
  169. if (params->m3 >= 0)
  170. writel(params->m3, &dpll_regs->cm_div_m3_dpll);
  171. if (params->m4 >= 0)
  172. writel(params->m4, &dpll_regs->cm_div_m4_dpll);
  173. if (params->m5 >= 0)
  174. writel(params->m5, &dpll_regs->cm_div_m5_dpll);
  175. if (params->m6 >= 0)
  176. writel(params->m6, &dpll_regs->cm_div_m6_dpll);
  177. if (params->m7 >= 0)
  178. writel(params->m7, &dpll_regs->cm_div_m7_dpll);
  179. }
  180. /*
  181. * Lock MPU dpll
  182. *
  183. * Resulting MPU frequencies:
  184. * 4430 ES1.0 : 600 MHz
  185. * 4430 ES2.x : 792 MHz (OPP Turbo)
  186. * 4460 : 920 MHz (OPP Turbo) - DCC disabled
  187. */
  188. const struct dpll_params *get_mpu_dpll_params(void)
  189. {
  190. u32 omap_rev, sysclk_ind;
  191. omap_rev = omap_revision();
  192. sysclk_ind = get_sys_clk_index();
  193. if (omap_rev == OMAP4430_ES1_0)
  194. return &mpu_dpll_params_1200mhz[sysclk_ind];
  195. else if (omap_rev < OMAP4460_ES1_0)
  196. return &mpu_dpll_params_1600mhz[sysclk_ind];
  197. else
  198. return &mpu_dpll_params_1400mhz[sysclk_ind];
  199. }
  200. const struct dpll_params *get_core_dpll_params(void)
  201. {
  202. u32 sysclk_ind = get_sys_clk_index();
  203. switch (omap_revision()) {
  204. case OMAP4430_ES1_0:
  205. return &core_dpll_params_es1_1524mhz[sysclk_ind];
  206. case OMAP4430_ES2_0:
  207. case OMAP4430_SILICON_ID_INVALID:
  208. /* safest */
  209. return &core_dpll_params_es2_1600mhz_ddr200mhz[sysclk_ind];
  210. default:
  211. return &core_dpll_params_1600mhz[sysclk_ind];
  212. }
  213. }
  214. const struct dpll_params *get_per_dpll_params(void)
  215. {
  216. u32 sysclk_ind = get_sys_clk_index();
  217. return &per_dpll_params_1536mhz[sysclk_ind];
  218. }
  219. const struct dpll_params *get_iva_dpll_params(void)
  220. {
  221. u32 sysclk_ind = get_sys_clk_index();
  222. return &iva_dpll_params_1862mhz[sysclk_ind];
  223. }
  224. const struct dpll_params *get_usb_dpll_params(void)
  225. {
  226. u32 sysclk_ind = get_sys_clk_index();
  227. return &usb_dpll_params_1920mhz[sysclk_ind];
  228. }
  229. const struct dpll_params *get_abe_dpll_params(void)
  230. {
  231. #ifdef CONFIG_SYS_OMAP_ABE_SYSCK
  232. u32 sysclk_ind = get_sys_clk_index();
  233. return &abe_dpll_params_sysclk_196608khz[sysclk_ind];
  234. #else
  235. return &abe_dpll_params_32k_196608khz;
  236. #endif
  237. }
  238. /*
  239. * Setup the voltages for vdd_mpu, vdd_core, and vdd_iva
  240. * We set the maximum voltages allowed here because Smart-Reflex is not
  241. * enabled in bootloader. Voltage initialization in the kernel will set
  242. * these to the nominal values after enabling Smart-Reflex
  243. */
  244. void scale_vcores(void)
  245. {
  246. u32 volt, omap_rev;
  247. omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
  248. omap_rev = omap_revision();
  249. /*
  250. * Scale Voltage rails:
  251. * 1. VDD_CORE
  252. * 3. VDD_MPU
  253. * 3. VDD_IVA
  254. */
  255. if (omap_rev < OMAP4460_ES1_0) {
  256. /*
  257. * OMAP4430:
  258. * VDD_CORE = TWL6030 VCORE3
  259. * VDD_MPU = TWL6030 VCORE1
  260. * VDD_IVA = TWL6030 VCORE2
  261. */
  262. volt = 1200;
  263. do_scale_vcore(SMPS_REG_ADDR_VCORE3, volt);
  264. /*
  265. * note on VDD_MPU:
  266. * Setting a high voltage for Nitro mode as smart reflex is not
  267. * enabled. We use the maximum possible value in the AVS range
  268. * because the next higher voltage in the discrete range
  269. * (code >= 0b111010) is way too high.
  270. */
  271. volt = 1325;
  272. do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
  273. volt = 1200;
  274. do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
  275. } else {
  276. /*
  277. * OMAP4460:
  278. * VDD_CORE = TWL6030 VCORE1
  279. * VDD_MPU = TPS62361
  280. * VDD_IVA = TWL6030 VCORE2
  281. */
  282. volt = 1200;
  283. do_scale_vcore(SMPS_REG_ADDR_VCORE1, volt);
  284. /* TPS62361 */
  285. volt = 1203;
  286. do_scale_tps62361(TPS62361_VSEL0_GPIO,
  287. TPS62361_REG_ADDR_SET1, volt);
  288. /* VCORE 2 - supplies vdd_iva */
  289. volt = 1200;
  290. do_scale_vcore(SMPS_REG_ADDR_VCORE2, volt);
  291. }
  292. }
  293. u32 get_offset_code(u32 offset)
  294. {
  295. u32 offset_code, step = 12660; /* 12.66 mV represented in uV */
  296. if (omap_revision() == OMAP4430_ES1_0)
  297. offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_UV;
  298. else
  299. offset -= PHOENIX_SMPS_BASE_VOLT_STD_MODE_WITH_OFFSET_UV;
  300. offset_code = (offset + step - 1) / step;
  301. /* The code starts at 1 not 0 */
  302. return ++offset_code;
  303. }
  304. /*
  305. * Enable essential clock domains, modules and
  306. * do some additional special settings needed
  307. */
  308. void enable_basic_clocks(void)
  309. {
  310. u32 *const clk_domains_essential[] = {
  311. &prcm->cm_l4per_clkstctrl,
  312. &prcm->cm_l3init_clkstctrl,
  313. &prcm->cm_memif_clkstctrl,
  314. &prcm->cm_l4cfg_clkstctrl,
  315. 0
  316. };
  317. u32 *const clk_modules_hw_auto_essential[] = {
  318. &prcm->cm_l3_2_gpmc_clkctrl,
  319. &prcm->cm_memif_emif_1_clkctrl,
  320. &prcm->cm_memif_emif_2_clkctrl,
  321. &prcm->cm_l4cfg_l4_cfg_clkctrl,
  322. &prcm->cm_wkup_gpio1_clkctrl,
  323. &prcm->cm_l4per_gpio2_clkctrl,
  324. &prcm->cm_l4per_gpio3_clkctrl,
  325. &prcm->cm_l4per_gpio4_clkctrl,
  326. &prcm->cm_l4per_gpio5_clkctrl,
  327. &prcm->cm_l4per_gpio6_clkctrl,
  328. 0
  329. };
  330. u32 *const clk_modules_explicit_en_essential[] = {
  331. &prcm->cm_wkup_gptimer1_clkctrl,
  332. &prcm->cm_l3init_hsmmc1_clkctrl,
  333. &prcm->cm_l3init_hsmmc2_clkctrl,
  334. &prcm->cm_l4per_gptimer2_clkctrl,
  335. &prcm->cm_wkup_wdtimer2_clkctrl,
  336. &prcm->cm_l4per_uart3_clkctrl,
  337. 0
  338. };
  339. /* Enable optional additional functional clock for GPIO4 */
  340. setbits_le32(&prcm->cm_l4per_gpio4_clkctrl,
  341. GPIO4_CLKCTRL_OPTFCLKEN_MASK);
  342. /* Enable 96 MHz clock for MMC1 & MMC2 */
  343. setbits_le32(&prcm->cm_l3init_hsmmc1_clkctrl,
  344. HSMMC_CLKCTRL_CLKSEL_MASK);
  345. setbits_le32(&prcm->cm_l3init_hsmmc2_clkctrl,
  346. HSMMC_CLKCTRL_CLKSEL_MASK);
  347. /* Select 32KHz clock as the source of GPTIMER1 */
  348. setbits_le32(&prcm->cm_wkup_gptimer1_clkctrl,
  349. GPTIMER1_CLKCTRL_CLKSEL_MASK);
  350. /* Enable optional 48M functional clock for USB PHY */
  351. setbits_le32(&prcm->cm_l3init_usbphy_clkctrl,
  352. USBPHY_CLKCTRL_OPTFCLKEN_PHY_48M_MASK);
  353. do_enable_clocks(clk_domains_essential,
  354. clk_modules_hw_auto_essential,
  355. clk_modules_explicit_en_essential,
  356. 1);
  357. }
  358. void enable_basic_uboot_clocks(void)
  359. {
  360. u32 *const clk_domains_essential[] = {
  361. 0
  362. };
  363. u32 *const clk_modules_hw_auto_essential[] = {
  364. &prcm->cm_l3init_hsusbotg_clkctrl,
  365. &prcm->cm_l3init_usbphy_clkctrl,
  366. &prcm->cm_l3init_usbphy_clkctrl,
  367. &prcm->cm_clksel_usb_60mhz,
  368. &prcm->cm_l3init_hsusbtll_clkctrl,
  369. 0
  370. };
  371. u32 *const clk_modules_explicit_en_essential[] = {
  372. &prcm->cm_l4per_mcspi1_clkctrl,
  373. &prcm->cm_l4per_i2c1_clkctrl,
  374. &prcm->cm_l4per_i2c2_clkctrl,
  375. &prcm->cm_l4per_i2c3_clkctrl,
  376. &prcm->cm_l4per_i2c4_clkctrl,
  377. &prcm->cm_l3init_hsusbhost_clkctrl,
  378. 0
  379. };
  380. do_enable_clocks(clk_domains_essential,
  381. clk_modules_hw_auto_essential,
  382. clk_modules_explicit_en_essential,
  383. 1);
  384. }
  385. /*
  386. * Enable non-essential clock domains, modules and
  387. * do some additional special settings needed
  388. */
  389. void enable_non_essential_clocks(void)
  390. {
  391. u32 *const clk_domains_non_essential[] = {
  392. &prcm->cm_mpu_m3_clkstctrl,
  393. &prcm->cm_ivahd_clkstctrl,
  394. &prcm->cm_dsp_clkstctrl,
  395. &prcm->cm_dss_clkstctrl,
  396. &prcm->cm_sgx_clkstctrl,
  397. &prcm->cm1_abe_clkstctrl,
  398. &prcm->cm_c2c_clkstctrl,
  399. &prcm->cm_cam_clkstctrl,
  400. &prcm->cm_dss_clkstctrl,
  401. &prcm->cm_sdma_clkstctrl,
  402. 0
  403. };
  404. u32 *const clk_modules_hw_auto_non_essential[] = {
  405. &prcm->cm_l3instr_l3_3_clkctrl,
  406. &prcm->cm_l3instr_l3_instr_clkctrl,
  407. &prcm->cm_l3instr_intrconn_wp1_clkctrl,
  408. &prcm->cm_l3init_hsi_clkctrl,
  409. 0
  410. };
  411. u32 *const clk_modules_explicit_en_non_essential[] = {
  412. &prcm->cm1_abe_aess_clkctrl,
  413. &prcm->cm1_abe_pdm_clkctrl,
  414. &prcm->cm1_abe_dmic_clkctrl,
  415. &prcm->cm1_abe_mcasp_clkctrl,
  416. &prcm->cm1_abe_mcbsp1_clkctrl,
  417. &prcm->cm1_abe_mcbsp2_clkctrl,
  418. &prcm->cm1_abe_mcbsp3_clkctrl,
  419. &prcm->cm1_abe_slimbus_clkctrl,
  420. &prcm->cm1_abe_timer5_clkctrl,
  421. &prcm->cm1_abe_timer6_clkctrl,
  422. &prcm->cm1_abe_timer7_clkctrl,
  423. &prcm->cm1_abe_timer8_clkctrl,
  424. &prcm->cm1_abe_wdt3_clkctrl,
  425. &prcm->cm_l4per_gptimer9_clkctrl,
  426. &prcm->cm_l4per_gptimer10_clkctrl,
  427. &prcm->cm_l4per_gptimer11_clkctrl,
  428. &prcm->cm_l4per_gptimer3_clkctrl,
  429. &prcm->cm_l4per_gptimer4_clkctrl,
  430. &prcm->cm_l4per_hdq1w_clkctrl,
  431. &prcm->cm_l4per_mcbsp4_clkctrl,
  432. &prcm->cm_l4per_mcspi2_clkctrl,
  433. &prcm->cm_l4per_mcspi3_clkctrl,
  434. &prcm->cm_l4per_mcspi4_clkctrl,
  435. &prcm->cm_l4per_mmcsd3_clkctrl,
  436. &prcm->cm_l4per_mmcsd4_clkctrl,
  437. &prcm->cm_l4per_mmcsd5_clkctrl,
  438. &prcm->cm_l4per_uart1_clkctrl,
  439. &prcm->cm_l4per_uart2_clkctrl,
  440. &prcm->cm_l4per_uart4_clkctrl,
  441. &prcm->cm_wkup_keyboard_clkctrl,
  442. &prcm->cm_wkup_wdtimer2_clkctrl,
  443. &prcm->cm_cam_iss_clkctrl,
  444. &prcm->cm_cam_fdif_clkctrl,
  445. &prcm->cm_dss_dss_clkctrl,
  446. &prcm->cm_sgx_sgx_clkctrl,
  447. 0
  448. };
  449. /* Enable optional functional clock for ISS */
  450. setbits_le32(&prcm->cm_cam_iss_clkctrl, ISS_CLKCTRL_OPTFCLKEN_MASK);
  451. /* Enable all optional functional clocks of DSS */
  452. setbits_le32(&prcm->cm_dss_dss_clkctrl, DSS_CLKCTRL_OPTFCLKEN_MASK);
  453. do_enable_clocks(clk_domains_non_essential,
  454. clk_modules_hw_auto_non_essential,
  455. clk_modules_explicit_en_non_essential,
  456. 0);
  457. /* Put camera module in no sleep mode */
  458. clrsetbits_le32(&prcm->cm_cam_clkstctrl, MODULE_CLKCTRL_MODULEMODE_MASK,
  459. CD_CLKCTRL_CLKTRCTRL_NO_SLEEP <<
  460. MODULE_CLKCTRL_MODULEMODE_SHIFT);
  461. }