core.c 24 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /**
  3. * core.c - DesignWare USB3 DRD Controller Core file
  4. *
  5. * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com
  6. *
  7. * Authors: Felipe Balbi <balbi@ti.com>,
  8. * Sebastian Andrzej Siewior <bigeasy@linutronix.de>
  9. *
  10. * Taken from Linux Kernel v3.19-rc1 (drivers/usb/dwc3/core.c) and ported
  11. * to uboot.
  12. *
  13. * commit cd72f890d2 : usb: dwc3: core: enable phy suspend quirk on non-FPGA
  14. */
  15. #include <common.h>
  16. #include <cpu_func.h>
  17. #include <malloc.h>
  18. #include <dwc3-uboot.h>
  19. #include <dm/device_compat.h>
  20. #include <dm/devres.h>
  21. #include <linux/bug.h>
  22. #include <linux/delay.h>
  23. #include <linux/dma-mapping.h>
  24. #include <linux/err.h>
  25. #include <linux/ioport.h>
  26. #include <dm.h>
  27. #include <generic-phy.h>
  28. #include <linux/usb/ch9.h>
  29. #include <linux/usb/gadget.h>
  30. #include "core.h"
  31. #include "gadget.h"
  32. #include "io.h"
  33. #include "linux-compat.h"
  34. static LIST_HEAD(dwc3_list);
  35. /* -------------------------------------------------------------------------- */
  36. static void dwc3_set_mode(struct dwc3 *dwc, u32 mode)
  37. {
  38. u32 reg;
  39. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  40. reg &= ~(DWC3_GCTL_PRTCAPDIR(DWC3_GCTL_PRTCAP_OTG));
  41. reg |= DWC3_GCTL_PRTCAPDIR(mode);
  42. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  43. }
  44. /**
  45. * dwc3_core_soft_reset - Issues core soft reset and PHY reset
  46. * @dwc: pointer to our context structure
  47. */
  48. static int dwc3_core_soft_reset(struct dwc3 *dwc)
  49. {
  50. u32 reg;
  51. /* Before Resetting PHY, put Core in Reset */
  52. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  53. reg |= DWC3_GCTL_CORESOFTRESET;
  54. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  55. /* Assert USB3 PHY reset */
  56. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  57. reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST;
  58. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  59. /* Assert USB2 PHY reset */
  60. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  61. reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST;
  62. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  63. mdelay(100);
  64. /* Clear USB3 PHY reset */
  65. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  66. reg &= ~DWC3_GUSB3PIPECTL_PHYSOFTRST;
  67. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  68. /* Clear USB2 PHY reset */
  69. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  70. reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST;
  71. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  72. mdelay(100);
  73. /* After PHYs are stable we can take Core out of reset state */
  74. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  75. reg &= ~DWC3_GCTL_CORESOFTRESET;
  76. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  77. return 0;
  78. }
  79. /**
  80. * dwc3_free_one_event_buffer - Frees one event buffer
  81. * @dwc: Pointer to our controller context structure
  82. * @evt: Pointer to event buffer to be freed
  83. */
  84. static void dwc3_free_one_event_buffer(struct dwc3 *dwc,
  85. struct dwc3_event_buffer *evt)
  86. {
  87. dma_free_coherent(evt->buf);
  88. }
  89. /**
  90. * dwc3_alloc_one_event_buffer - Allocates one event buffer structure
  91. * @dwc: Pointer to our controller context structure
  92. * @length: size of the event buffer
  93. *
  94. * Returns a pointer to the allocated event buffer structure on success
  95. * otherwise ERR_PTR(errno).
  96. */
  97. static struct dwc3_event_buffer *dwc3_alloc_one_event_buffer(struct dwc3 *dwc,
  98. unsigned length)
  99. {
  100. struct dwc3_event_buffer *evt;
  101. evt = devm_kzalloc((struct udevice *)dwc->dev, sizeof(*evt),
  102. GFP_KERNEL);
  103. if (!evt)
  104. return ERR_PTR(-ENOMEM);
  105. evt->dwc = dwc;
  106. evt->length = length;
  107. evt->buf = dma_alloc_coherent(length,
  108. (unsigned long *)&evt->dma);
  109. if (!evt->buf)
  110. return ERR_PTR(-ENOMEM);
  111. dwc3_flush_cache((uintptr_t)evt->buf, evt->length);
  112. return evt;
  113. }
  114. /**
  115. * dwc3_free_event_buffers - frees all allocated event buffers
  116. * @dwc: Pointer to our controller context structure
  117. */
  118. static void dwc3_free_event_buffers(struct dwc3 *dwc)
  119. {
  120. struct dwc3_event_buffer *evt;
  121. int i;
  122. for (i = 0; i < dwc->num_event_buffers; i++) {
  123. evt = dwc->ev_buffs[i];
  124. if (evt)
  125. dwc3_free_one_event_buffer(dwc, evt);
  126. }
  127. }
  128. /**
  129. * dwc3_alloc_event_buffers - Allocates @num event buffers of size @length
  130. * @dwc: pointer to our controller context structure
  131. * @length: size of event buffer
  132. *
  133. * Returns 0 on success otherwise negative errno. In the error case, dwc
  134. * may contain some buffers allocated but not all which were requested.
  135. */
  136. static int dwc3_alloc_event_buffers(struct dwc3 *dwc, unsigned length)
  137. {
  138. int num;
  139. int i;
  140. num = DWC3_NUM_INT(dwc->hwparams.hwparams1);
  141. dwc->num_event_buffers = num;
  142. dwc->ev_buffs = memalign(CONFIG_SYS_CACHELINE_SIZE,
  143. sizeof(*dwc->ev_buffs) * num);
  144. if (!dwc->ev_buffs)
  145. return -ENOMEM;
  146. for (i = 0; i < num; i++) {
  147. struct dwc3_event_buffer *evt;
  148. evt = dwc3_alloc_one_event_buffer(dwc, length);
  149. if (IS_ERR(evt)) {
  150. dev_err(dwc->dev, "can't allocate event buffer\n");
  151. return PTR_ERR(evt);
  152. }
  153. dwc->ev_buffs[i] = evt;
  154. }
  155. return 0;
  156. }
  157. /**
  158. * dwc3_event_buffers_setup - setup our allocated event buffers
  159. * @dwc: pointer to our controller context structure
  160. *
  161. * Returns 0 on success otherwise negative errno.
  162. */
  163. static int dwc3_event_buffers_setup(struct dwc3 *dwc)
  164. {
  165. struct dwc3_event_buffer *evt;
  166. int n;
  167. for (n = 0; n < dwc->num_event_buffers; n++) {
  168. evt = dwc->ev_buffs[n];
  169. dev_dbg(dwc->dev, "Event buf %p dma %08llx length %d\n",
  170. evt->buf, (unsigned long long) evt->dma,
  171. evt->length);
  172. evt->lpos = 0;
  173. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n),
  174. lower_32_bits(evt->dma));
  175. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n),
  176. upper_32_bits(evt->dma));
  177. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n),
  178. DWC3_GEVNTSIZ_SIZE(evt->length));
  179. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  180. }
  181. return 0;
  182. }
  183. static void dwc3_event_buffers_cleanup(struct dwc3 *dwc)
  184. {
  185. struct dwc3_event_buffer *evt;
  186. int n;
  187. for (n = 0; n < dwc->num_event_buffers; n++) {
  188. evt = dwc->ev_buffs[n];
  189. evt->lpos = 0;
  190. dwc3_writel(dwc->regs, DWC3_GEVNTADRLO(n), 0);
  191. dwc3_writel(dwc->regs, DWC3_GEVNTADRHI(n), 0);
  192. dwc3_writel(dwc->regs, DWC3_GEVNTSIZ(n), DWC3_GEVNTSIZ_INTMASK
  193. | DWC3_GEVNTSIZ_SIZE(0));
  194. dwc3_writel(dwc->regs, DWC3_GEVNTCOUNT(n), 0);
  195. }
  196. }
  197. static int dwc3_alloc_scratch_buffers(struct dwc3 *dwc)
  198. {
  199. if (!dwc->has_hibernation)
  200. return 0;
  201. if (!dwc->nr_scratch)
  202. return 0;
  203. dwc->scratchbuf = kmalloc_array(dwc->nr_scratch,
  204. DWC3_SCRATCHBUF_SIZE, GFP_KERNEL);
  205. if (!dwc->scratchbuf)
  206. return -ENOMEM;
  207. return 0;
  208. }
  209. static int dwc3_setup_scratch_buffers(struct dwc3 *dwc)
  210. {
  211. dma_addr_t scratch_addr;
  212. u32 param;
  213. int ret;
  214. if (!dwc->has_hibernation)
  215. return 0;
  216. if (!dwc->nr_scratch)
  217. return 0;
  218. scratch_addr = dma_map_single(dwc->scratchbuf,
  219. dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  220. DMA_BIDIRECTIONAL);
  221. if (dma_mapping_error(dwc->dev, scratch_addr)) {
  222. dev_err(dwc->dev, "failed to map scratch buffer\n");
  223. ret = -EFAULT;
  224. goto err0;
  225. }
  226. dwc->scratch_addr = scratch_addr;
  227. param = lower_32_bits(scratch_addr);
  228. ret = dwc3_send_gadget_generic_command(dwc,
  229. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_LO, param);
  230. if (ret < 0)
  231. goto err1;
  232. param = upper_32_bits(scratch_addr);
  233. ret = dwc3_send_gadget_generic_command(dwc,
  234. DWC3_DGCMD_SET_SCRATCHPAD_ADDR_HI, param);
  235. if (ret < 0)
  236. goto err1;
  237. return 0;
  238. err1:
  239. dma_unmap_single(scratch_addr, dwc->nr_scratch * DWC3_SCRATCHBUF_SIZE,
  240. DMA_BIDIRECTIONAL);
  241. err0:
  242. return ret;
  243. }
  244. static void dwc3_free_scratch_buffers(struct dwc3 *dwc)
  245. {
  246. if (!dwc->has_hibernation)
  247. return;
  248. if (!dwc->nr_scratch)
  249. return;
  250. dma_unmap_single(dwc->scratch_addr, dwc->nr_scratch *
  251. DWC3_SCRATCHBUF_SIZE, DMA_BIDIRECTIONAL);
  252. kfree(dwc->scratchbuf);
  253. }
  254. static void dwc3_core_num_eps(struct dwc3 *dwc)
  255. {
  256. struct dwc3_hwparams *parms = &dwc->hwparams;
  257. dwc->num_in_eps = DWC3_NUM_IN_EPS(parms);
  258. dwc->num_out_eps = DWC3_NUM_EPS(parms) - dwc->num_in_eps;
  259. dev_vdbg(dwc->dev, "found %d IN and %d OUT endpoints\n",
  260. dwc->num_in_eps, dwc->num_out_eps);
  261. }
  262. static void dwc3_cache_hwparams(struct dwc3 *dwc)
  263. {
  264. struct dwc3_hwparams *parms = &dwc->hwparams;
  265. parms->hwparams0 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS0);
  266. parms->hwparams1 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS1);
  267. parms->hwparams2 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS2);
  268. parms->hwparams3 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS3);
  269. parms->hwparams4 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS4);
  270. parms->hwparams5 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS5);
  271. parms->hwparams6 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS6);
  272. parms->hwparams7 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS7);
  273. parms->hwparams8 = dwc3_readl(dwc->regs, DWC3_GHWPARAMS8);
  274. }
  275. /**
  276. * dwc3_phy_setup - Configure USB PHY Interface of DWC3 Core
  277. * @dwc: Pointer to our controller context structure
  278. */
  279. static void dwc3_phy_setup(struct dwc3 *dwc)
  280. {
  281. u32 reg;
  282. reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
  283. /*
  284. * Above 1.94a, it is recommended to set DWC3_GUSB3PIPECTL_SUSPHY
  285. * to '0' during coreConsultant configuration. So default value
  286. * will be '0' when the core is reset. Application needs to set it
  287. * to '1' after the core initialization is completed.
  288. */
  289. if (dwc->revision > DWC3_REVISION_194A)
  290. reg |= DWC3_GUSB3PIPECTL_SUSPHY;
  291. if (dwc->u2ss_inp3_quirk)
  292. reg |= DWC3_GUSB3PIPECTL_U2SSINP3OK;
  293. if (dwc->req_p1p2p3_quirk)
  294. reg |= DWC3_GUSB3PIPECTL_REQP1P2P3;
  295. if (dwc->del_p1p2p3_quirk)
  296. reg |= DWC3_GUSB3PIPECTL_DEP1P2P3_EN;
  297. if (dwc->del_phy_power_chg_quirk)
  298. reg |= DWC3_GUSB3PIPECTL_DEPOCHANGE;
  299. if (dwc->lfps_filter_quirk)
  300. reg |= DWC3_GUSB3PIPECTL_LFPSFILT;
  301. if (dwc->rx_detect_poll_quirk)
  302. reg |= DWC3_GUSB3PIPECTL_RX_DETOPOLL;
  303. if (dwc->tx_de_emphasis_quirk)
  304. reg |= DWC3_GUSB3PIPECTL_TX_DEEPH(dwc->tx_de_emphasis);
  305. if (dwc->dis_u3_susphy_quirk)
  306. reg &= ~DWC3_GUSB3PIPECTL_SUSPHY;
  307. if (dwc->dis_del_phy_power_chg_quirk)
  308. reg &= ~DWC3_GUSB3PIPECTL_DEPOCHANGE;
  309. dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg);
  310. mdelay(100);
  311. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  312. /*
  313. * Above 1.94a, it is recommended to set DWC3_GUSB2PHYCFG_SUSPHY to
  314. * '0' during coreConsultant configuration. So default value will
  315. * be '0' when the core is reset. Application needs to set it to
  316. * '1' after the core initialization is completed.
  317. */
  318. if (dwc->revision > DWC3_REVISION_194A)
  319. reg |= DWC3_GUSB2PHYCFG_SUSPHY;
  320. if (dwc->dis_u2_susphy_quirk)
  321. reg &= ~DWC3_GUSB2PHYCFG_SUSPHY;
  322. if (dwc->dis_enblslpm_quirk)
  323. reg &= ~DWC3_GUSB2PHYCFG_ENBLSLPM;
  324. if (dwc->dis_u2_freeclk_exists_quirk)
  325. reg &= ~DWC3_GUSB2PHYCFG_U2_FREECLK_EXISTS;
  326. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  327. mdelay(100);
  328. }
  329. /**
  330. * dwc3_core_init - Low-level initialization of DWC3 Core
  331. * @dwc: Pointer to our controller context structure
  332. *
  333. * Returns 0 on success otherwise negative errno.
  334. */
  335. static int dwc3_core_init(struct dwc3 *dwc)
  336. {
  337. unsigned long timeout;
  338. u32 hwparams4 = dwc->hwparams.hwparams4;
  339. u32 reg;
  340. int ret;
  341. reg = dwc3_readl(dwc->regs, DWC3_GSNPSID);
  342. /* This should read as U3 followed by revision number */
  343. if ((reg & DWC3_GSNPSID_MASK) != 0x55330000) {
  344. dev_err(dwc->dev, "this is not a DesignWare USB3 DRD Core\n");
  345. ret = -ENODEV;
  346. goto err0;
  347. }
  348. dwc->revision = reg;
  349. /* Handle USB2.0-only core configuration */
  350. if (DWC3_GHWPARAMS3_SSPHY_IFC(dwc->hwparams.hwparams3) ==
  351. DWC3_GHWPARAMS3_SSPHY_IFC_DIS) {
  352. if (dwc->maximum_speed == USB_SPEED_SUPER)
  353. dwc->maximum_speed = USB_SPEED_HIGH;
  354. }
  355. /* issue device SoftReset too */
  356. timeout = 5000;
  357. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_CSFTRST);
  358. while (timeout--) {
  359. reg = dwc3_readl(dwc->regs, DWC3_DCTL);
  360. if (!(reg & DWC3_DCTL_CSFTRST))
  361. break;
  362. };
  363. if (!timeout) {
  364. dev_err(dwc->dev, "Reset Timed Out\n");
  365. ret = -ETIMEDOUT;
  366. goto err0;
  367. }
  368. dwc3_phy_setup(dwc);
  369. ret = dwc3_core_soft_reset(dwc);
  370. if (ret)
  371. goto err0;
  372. reg = dwc3_readl(dwc->regs, DWC3_GCTL);
  373. reg &= ~DWC3_GCTL_SCALEDOWN_MASK;
  374. switch (DWC3_GHWPARAMS1_EN_PWROPT(dwc->hwparams.hwparams1)) {
  375. case DWC3_GHWPARAMS1_EN_PWROPT_CLK:
  376. /**
  377. * WORKAROUND: DWC3 revisions between 2.10a and 2.50a have an
  378. * issue which would cause xHCI compliance tests to fail.
  379. *
  380. * Because of that we cannot enable clock gating on such
  381. * configurations.
  382. *
  383. * Refers to:
  384. *
  385. * STAR#9000588375: Clock Gating, SOF Issues when ref_clk-Based
  386. * SOF/ITP Mode Used
  387. */
  388. if ((dwc->dr_mode == USB_DR_MODE_HOST ||
  389. dwc->dr_mode == USB_DR_MODE_OTG) &&
  390. (dwc->revision >= DWC3_REVISION_210A &&
  391. dwc->revision <= DWC3_REVISION_250A))
  392. reg |= DWC3_GCTL_DSBLCLKGTNG | DWC3_GCTL_SOFITPSYNC;
  393. else
  394. reg &= ~DWC3_GCTL_DSBLCLKGTNG;
  395. break;
  396. case DWC3_GHWPARAMS1_EN_PWROPT_HIB:
  397. /* enable hibernation here */
  398. dwc->nr_scratch = DWC3_GHWPARAMS4_HIBER_SCRATCHBUFS(hwparams4);
  399. /*
  400. * REVISIT Enabling this bit so that host-mode hibernation
  401. * will work. Device-mode hibernation is not yet implemented.
  402. */
  403. reg |= DWC3_GCTL_GBLHIBERNATIONEN;
  404. break;
  405. default:
  406. dev_dbg(dwc->dev, "No power optimization available\n");
  407. }
  408. /* check if current dwc3 is on simulation board */
  409. if (dwc->hwparams.hwparams6 & DWC3_GHWPARAMS6_EN_FPGA) {
  410. dev_dbg(dwc->dev, "it is on FPGA board\n");
  411. dwc->is_fpga = true;
  412. }
  413. if(dwc->disable_scramble_quirk && !dwc->is_fpga)
  414. WARN(true,
  415. "disable_scramble cannot be used on non-FPGA builds\n");
  416. if (dwc->disable_scramble_quirk && dwc->is_fpga)
  417. reg |= DWC3_GCTL_DISSCRAMBLE;
  418. else
  419. reg &= ~DWC3_GCTL_DISSCRAMBLE;
  420. if (dwc->u2exit_lfps_quirk)
  421. reg |= DWC3_GCTL_U2EXIT_LFPS;
  422. /*
  423. * WORKAROUND: DWC3 revisions <1.90a have a bug
  424. * where the device can fail to connect at SuperSpeed
  425. * and falls back to high-speed mode which causes
  426. * the device to enter a Connect/Disconnect loop
  427. */
  428. if (dwc->revision < DWC3_REVISION_190A)
  429. reg |= DWC3_GCTL_U2RSTECN;
  430. dwc3_core_num_eps(dwc);
  431. dwc3_writel(dwc->regs, DWC3_GCTL, reg);
  432. ret = dwc3_alloc_scratch_buffers(dwc);
  433. if (ret)
  434. goto err0;
  435. ret = dwc3_setup_scratch_buffers(dwc);
  436. if (ret)
  437. goto err1;
  438. return 0;
  439. err1:
  440. dwc3_free_scratch_buffers(dwc);
  441. err0:
  442. return ret;
  443. }
  444. static void dwc3_core_exit(struct dwc3 *dwc)
  445. {
  446. dwc3_free_scratch_buffers(dwc);
  447. }
  448. static int dwc3_core_init_mode(struct dwc3 *dwc)
  449. {
  450. int ret;
  451. switch (dwc->dr_mode) {
  452. case USB_DR_MODE_PERIPHERAL:
  453. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  454. ret = dwc3_gadget_init(dwc);
  455. if (ret) {
  456. dev_err(dev, "failed to initialize gadget\n");
  457. return ret;
  458. }
  459. break;
  460. case USB_DR_MODE_HOST:
  461. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_HOST);
  462. ret = dwc3_host_init(dwc);
  463. if (ret) {
  464. dev_err(dev, "failed to initialize host\n");
  465. return ret;
  466. }
  467. break;
  468. case USB_DR_MODE_OTG:
  469. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_OTG);
  470. ret = dwc3_host_init(dwc);
  471. if (ret) {
  472. dev_err(dev, "failed to initialize host\n");
  473. return ret;
  474. }
  475. ret = dwc3_gadget_init(dwc);
  476. if (ret) {
  477. dev_err(dev, "failed to initialize gadget\n");
  478. return ret;
  479. }
  480. break;
  481. default:
  482. dev_err(dev, "Unsupported mode of operation %d\n", dwc->dr_mode);
  483. return -EINVAL;
  484. }
  485. return 0;
  486. }
  487. static void dwc3_gadget_run(struct dwc3 *dwc)
  488. {
  489. dwc3_writel(dwc->regs, DWC3_DCTL, DWC3_DCTL_RUN_STOP);
  490. mdelay(100);
  491. }
  492. static void dwc3_core_exit_mode(struct dwc3 *dwc)
  493. {
  494. switch (dwc->dr_mode) {
  495. case USB_DR_MODE_PERIPHERAL:
  496. dwc3_gadget_exit(dwc);
  497. break;
  498. case USB_DR_MODE_HOST:
  499. dwc3_host_exit(dwc);
  500. break;
  501. case USB_DR_MODE_OTG:
  502. dwc3_host_exit(dwc);
  503. dwc3_gadget_exit(dwc);
  504. break;
  505. default:
  506. /* do nothing */
  507. break;
  508. }
  509. /*
  510. * switch back to peripheral mode
  511. * This enables the phy to enter idle and then, if enabled, suspend.
  512. */
  513. dwc3_set_mode(dwc, DWC3_GCTL_PRTCAP_DEVICE);
  514. dwc3_gadget_run(dwc);
  515. }
  516. static void dwc3_uboot_hsphy_mode(struct dwc3_device *dwc3_dev,
  517. struct dwc3 *dwc)
  518. {
  519. enum usb_phy_interface hsphy_mode = dwc3_dev->hsphy_mode;
  520. u32 reg;
  521. /* Set dwc3 usb2 phy config */
  522. reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0));
  523. switch (hsphy_mode) {
  524. case USBPHY_INTERFACE_MODE_UTMI:
  525. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  526. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  527. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_8_BIT) |
  528. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_8_BIT);
  529. break;
  530. case USBPHY_INTERFACE_MODE_UTMIW:
  531. reg &= ~(DWC3_GUSB2PHYCFG_PHYIF_MASK |
  532. DWC3_GUSB2PHYCFG_USBTRDTIM_MASK);
  533. reg |= DWC3_GUSB2PHYCFG_PHYIF(UTMI_PHYIF_16_BIT) |
  534. DWC3_GUSB2PHYCFG_USBTRDTIM(USBTRDTIM_UTMI_16_BIT);
  535. break;
  536. default:
  537. break;
  538. }
  539. dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
  540. }
  541. #define DWC3_ALIGN_MASK (16 - 1)
  542. /**
  543. * dwc3_uboot_init - dwc3 core uboot initialization code
  544. * @dwc3_dev: struct dwc3_device containing initialization data
  545. *
  546. * Entry point for dwc3 driver (equivalent to dwc3_probe in linux
  547. * kernel driver). Pointer to dwc3_device should be passed containing
  548. * base address and other initialization data. Returns '0' on success and
  549. * a negative value on failure.
  550. *
  551. * Generally called from board_usb_init() implemented in board file.
  552. */
  553. int dwc3_uboot_init(struct dwc3_device *dwc3_dev)
  554. {
  555. struct dwc3 *dwc;
  556. struct device *dev = NULL;
  557. u8 lpm_nyet_threshold;
  558. u8 tx_de_emphasis;
  559. u8 hird_threshold;
  560. int ret;
  561. void *mem;
  562. mem = devm_kzalloc((struct udevice *)dev,
  563. sizeof(*dwc) + DWC3_ALIGN_MASK, GFP_KERNEL);
  564. if (!mem)
  565. return -ENOMEM;
  566. dwc = PTR_ALIGN(mem, DWC3_ALIGN_MASK + 1);
  567. dwc->mem = mem;
  568. dwc->regs = (void *)(uintptr_t)(dwc3_dev->base +
  569. DWC3_GLOBALS_REGS_START);
  570. /* default to highest possible threshold */
  571. lpm_nyet_threshold = 0xff;
  572. /* default to -3.5dB de-emphasis */
  573. tx_de_emphasis = 1;
  574. /*
  575. * default to assert utmi_sleep_n and use maximum allowed HIRD
  576. * threshold value of 0b1100
  577. */
  578. hird_threshold = 12;
  579. dwc->maximum_speed = dwc3_dev->maximum_speed;
  580. dwc->has_lpm_erratum = dwc3_dev->has_lpm_erratum;
  581. if (dwc3_dev->lpm_nyet_threshold)
  582. lpm_nyet_threshold = dwc3_dev->lpm_nyet_threshold;
  583. dwc->is_utmi_l1_suspend = dwc3_dev->is_utmi_l1_suspend;
  584. if (dwc3_dev->hird_threshold)
  585. hird_threshold = dwc3_dev->hird_threshold;
  586. dwc->needs_fifo_resize = dwc3_dev->tx_fifo_resize;
  587. dwc->dr_mode = dwc3_dev->dr_mode;
  588. dwc->disable_scramble_quirk = dwc3_dev->disable_scramble_quirk;
  589. dwc->u2exit_lfps_quirk = dwc3_dev->u2exit_lfps_quirk;
  590. dwc->u2ss_inp3_quirk = dwc3_dev->u2ss_inp3_quirk;
  591. dwc->req_p1p2p3_quirk = dwc3_dev->req_p1p2p3_quirk;
  592. dwc->del_p1p2p3_quirk = dwc3_dev->del_p1p2p3_quirk;
  593. dwc->del_phy_power_chg_quirk = dwc3_dev->del_phy_power_chg_quirk;
  594. dwc->lfps_filter_quirk = dwc3_dev->lfps_filter_quirk;
  595. dwc->rx_detect_poll_quirk = dwc3_dev->rx_detect_poll_quirk;
  596. dwc->dis_u3_susphy_quirk = dwc3_dev->dis_u3_susphy_quirk;
  597. dwc->dis_u2_susphy_quirk = dwc3_dev->dis_u2_susphy_quirk;
  598. dwc->dis_del_phy_power_chg_quirk = dwc3_dev->dis_del_phy_power_chg_quirk;
  599. dwc->dis_enblslpm_quirk = dwc3_dev->dis_enblslpm_quirk;
  600. dwc->dis_u2_freeclk_exists_quirk = dwc3_dev->dis_u2_freeclk_exists_quirk;
  601. dwc->tx_de_emphasis_quirk = dwc3_dev->tx_de_emphasis_quirk;
  602. if (dwc3_dev->tx_de_emphasis)
  603. tx_de_emphasis = dwc3_dev->tx_de_emphasis;
  604. /* default to superspeed if no maximum_speed passed */
  605. if (dwc->maximum_speed == USB_SPEED_UNKNOWN)
  606. dwc->maximum_speed = USB_SPEED_SUPER;
  607. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  608. dwc->tx_de_emphasis = tx_de_emphasis;
  609. dwc->hird_threshold = hird_threshold
  610. | (dwc->is_utmi_l1_suspend << 4);
  611. dwc->index = dwc3_dev->index;
  612. dwc3_cache_hwparams(dwc);
  613. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  614. if (ret) {
  615. dev_err(dwc->dev, "failed to allocate event buffers\n");
  616. return -ENOMEM;
  617. }
  618. if (!IS_ENABLED(CONFIG_USB_DWC3_GADGET))
  619. dwc->dr_mode = USB_DR_MODE_HOST;
  620. else if (!IS_ENABLED(CONFIG_USB_HOST))
  621. dwc->dr_mode = USB_DR_MODE_PERIPHERAL;
  622. if (dwc->dr_mode == USB_DR_MODE_UNKNOWN)
  623. dwc->dr_mode = USB_DR_MODE_OTG;
  624. ret = dwc3_core_init(dwc);
  625. if (ret) {
  626. dev_err(dev, "failed to initialize core\n");
  627. goto err0;
  628. }
  629. dwc3_uboot_hsphy_mode(dwc3_dev, dwc);
  630. ret = dwc3_event_buffers_setup(dwc);
  631. if (ret) {
  632. dev_err(dwc->dev, "failed to setup event buffers\n");
  633. goto err1;
  634. }
  635. ret = dwc3_core_init_mode(dwc);
  636. if (ret)
  637. goto err2;
  638. list_add_tail(&dwc->list, &dwc3_list);
  639. return 0;
  640. err2:
  641. dwc3_event_buffers_cleanup(dwc);
  642. err1:
  643. dwc3_core_exit(dwc);
  644. err0:
  645. dwc3_free_event_buffers(dwc);
  646. return ret;
  647. }
  648. /**
  649. * dwc3_uboot_exit - dwc3 core uboot cleanup code
  650. * @index: index of this controller
  651. *
  652. * Performs cleanup of memory allocated in dwc3_uboot_init and other misc
  653. * cleanups (equivalent to dwc3_remove in linux). index of _this_ controller
  654. * should be passed and should match with the index passed in
  655. * dwc3_device during init.
  656. *
  657. * Generally called from board file.
  658. */
  659. void dwc3_uboot_exit(int index)
  660. {
  661. struct dwc3 *dwc;
  662. list_for_each_entry(dwc, &dwc3_list, list) {
  663. if (dwc->index != index)
  664. continue;
  665. dwc3_core_exit_mode(dwc);
  666. dwc3_event_buffers_cleanup(dwc);
  667. dwc3_free_event_buffers(dwc);
  668. dwc3_core_exit(dwc);
  669. list_del(&dwc->list);
  670. kfree(dwc->mem);
  671. break;
  672. }
  673. }
  674. /**
  675. * dwc3_uboot_handle_interrupt - handle dwc3 core interrupt
  676. * @index: index of this controller
  677. *
  678. * Invokes dwc3 gadget interrupts.
  679. *
  680. * Generally called from board file.
  681. */
  682. void dwc3_uboot_handle_interrupt(int index)
  683. {
  684. struct dwc3 *dwc = NULL;
  685. list_for_each_entry(dwc, &dwc3_list, list) {
  686. if (dwc->index != index)
  687. continue;
  688. dwc3_gadget_uboot_handle_interrupt(dwc);
  689. break;
  690. }
  691. }
  692. MODULE_ALIAS("platform:dwc3");
  693. MODULE_AUTHOR("Felipe Balbi <balbi@ti.com>");
  694. MODULE_LICENSE("GPL v2");
  695. MODULE_DESCRIPTION("DesignWare USB3 DRD Controller Driver");
  696. #if CONFIG_IS_ENABLED(PHY) && CONFIG_IS_ENABLED(DM_USB)
  697. int dwc3_setup_phy(struct udevice *dev, struct phy_bulk *phys)
  698. {
  699. int ret;
  700. ret = generic_phy_get_bulk(dev, phys);
  701. if (ret)
  702. return ret;
  703. ret = generic_phy_init_bulk(phys);
  704. if (ret)
  705. return ret;
  706. ret = generic_phy_power_on_bulk(phys);
  707. if (ret)
  708. generic_phy_exit_bulk(phys);
  709. return ret;
  710. }
  711. int dwc3_shutdown_phy(struct udevice *dev, struct phy_bulk *phys)
  712. {
  713. int ret;
  714. ret = generic_phy_power_off_bulk(phys);
  715. ret |= generic_phy_exit_bulk(phys);
  716. return ret;
  717. }
  718. #endif
  719. #if CONFIG_IS_ENABLED(DM_USB)
  720. void dwc3_of_parse(struct dwc3 *dwc)
  721. {
  722. const u8 *tmp;
  723. struct udevice *dev = dwc->dev;
  724. u8 lpm_nyet_threshold;
  725. u8 tx_de_emphasis;
  726. u8 hird_threshold;
  727. /* default to highest possible threshold */
  728. lpm_nyet_threshold = 0xff;
  729. /* default to -3.5dB de-emphasis */
  730. tx_de_emphasis = 1;
  731. /*
  732. * default to assert utmi_sleep_n and use maximum allowed HIRD
  733. * threshold value of 0b1100
  734. */
  735. hird_threshold = 12;
  736. dwc->has_lpm_erratum = dev_read_bool(dev,
  737. "snps,has-lpm-erratum");
  738. tmp = dev_read_u8_array_ptr(dev, "snps,lpm-nyet-threshold", 1);
  739. if (tmp)
  740. lpm_nyet_threshold = *tmp;
  741. dwc->is_utmi_l1_suspend = dev_read_bool(dev,
  742. "snps,is-utmi-l1-suspend");
  743. tmp = dev_read_u8_array_ptr(dev, "snps,hird-threshold", 1);
  744. if (tmp)
  745. hird_threshold = *tmp;
  746. dwc->disable_scramble_quirk = dev_read_bool(dev,
  747. "snps,disable_scramble_quirk");
  748. dwc->u2exit_lfps_quirk = dev_read_bool(dev,
  749. "snps,u2exit_lfps_quirk");
  750. dwc->u2ss_inp3_quirk = dev_read_bool(dev,
  751. "snps,u2ss_inp3_quirk");
  752. dwc->req_p1p2p3_quirk = dev_read_bool(dev,
  753. "snps,req_p1p2p3_quirk");
  754. dwc->del_p1p2p3_quirk = dev_read_bool(dev,
  755. "snps,del_p1p2p3_quirk");
  756. dwc->del_phy_power_chg_quirk = dev_read_bool(dev,
  757. "snps,del_phy_power_chg_quirk");
  758. dwc->lfps_filter_quirk = dev_read_bool(dev,
  759. "snps,lfps_filter_quirk");
  760. dwc->rx_detect_poll_quirk = dev_read_bool(dev,
  761. "snps,rx_detect_poll_quirk");
  762. dwc->dis_u3_susphy_quirk = dev_read_bool(dev,
  763. "snps,dis_u3_susphy_quirk");
  764. dwc->dis_u2_susphy_quirk = dev_read_bool(dev,
  765. "snps,dis_u2_susphy_quirk");
  766. dwc->dis_del_phy_power_chg_quirk = dev_read_bool(dev,
  767. "snps,dis-del-phy-power-chg-quirk");
  768. dwc->dis_enblslpm_quirk = dev_read_bool(dev,
  769. "snps,dis_enblslpm_quirk");
  770. dwc->dis_u2_freeclk_exists_quirk = dev_read_bool(dev,
  771. "snps,dis-u2-freeclk-exists-quirk");
  772. dwc->tx_de_emphasis_quirk = dev_read_bool(dev,
  773. "snps,tx_de_emphasis_quirk");
  774. tmp = dev_read_u8_array_ptr(dev, "snps,tx_de_emphasis", 1);
  775. if (tmp)
  776. tx_de_emphasis = *tmp;
  777. dwc->lpm_nyet_threshold = lpm_nyet_threshold;
  778. dwc->tx_de_emphasis = tx_de_emphasis;
  779. dwc->hird_threshold = hird_threshold
  780. | (dwc->is_utmi_l1_suspend << 4);
  781. }
  782. int dwc3_init(struct dwc3 *dwc)
  783. {
  784. int ret;
  785. dwc3_cache_hwparams(dwc);
  786. ret = dwc3_alloc_event_buffers(dwc, DWC3_EVENT_BUFFERS_SIZE);
  787. if (ret) {
  788. dev_err(dwc->dev, "failed to allocate event buffers\n");
  789. return -ENOMEM;
  790. }
  791. ret = dwc3_core_init(dwc);
  792. if (ret) {
  793. dev_err(dev, "failed to initialize core\n");
  794. goto core_fail;
  795. }
  796. ret = dwc3_event_buffers_setup(dwc);
  797. if (ret) {
  798. dev_err(dwc->dev, "failed to setup event buffers\n");
  799. goto event_fail;
  800. }
  801. ret = dwc3_core_init_mode(dwc);
  802. if (ret)
  803. goto mode_fail;
  804. return 0;
  805. mode_fail:
  806. dwc3_event_buffers_cleanup(dwc);
  807. event_fail:
  808. dwc3_core_exit(dwc);
  809. core_fail:
  810. dwc3_free_event_buffers(dwc);
  811. return ret;
  812. }
  813. void dwc3_remove(struct dwc3 *dwc)
  814. {
  815. dwc3_core_exit_mode(dwc);
  816. dwc3_event_buffers_cleanup(dwc);
  817. dwc3_free_event_buffers(dwc);
  818. dwc3_core_exit(dwc);
  819. kfree(dwc->mem);
  820. }
  821. #endif