sdram_common.h 4.7 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2018 Rockchip Electronics Co., Ltd
  4. */
  5. #ifndef _ASM_ARCH_SDRAM_COMMON_H
  6. #define _ASM_ARCH_SDRAM_COMMON_H
  7. #ifndef MHZ
  8. #define MHZ (1000 * 1000)
  9. #endif
  10. #define PATTERN (0x5aa5f00f)
  11. #define MIN(a, b) (((a) > (b)) ? (b) : (a))
  12. #define MAX(a, b) (((a) > (b)) ? (a) : (b))
  13. struct sdram_cap_info {
  14. unsigned int rank;
  15. /* dram column number, 0 means this channel is invalid */
  16. unsigned int col;
  17. /* dram bank number, 3:8bank, 2:4bank */
  18. unsigned int bk;
  19. /* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
  20. unsigned int bw;
  21. /* die buswidth, 2:32bit, 1:16bit, 0:8bit */
  22. unsigned int dbw;
  23. /*
  24. * row_3_4 = 1: 6Gb or 12Gb die
  25. * row_3_4 = 0: normal die, power of 2
  26. */
  27. unsigned int row_3_4;
  28. unsigned int cs0_row;
  29. unsigned int cs1_row;
  30. unsigned int cs0_high16bit_row;
  31. unsigned int cs1_high16bit_row;
  32. unsigned int ddrconfig;
  33. };
  34. struct sdram_base_params {
  35. unsigned int ddr_freq;
  36. unsigned int dramtype;
  37. unsigned int num_channels;
  38. unsigned int stride;
  39. unsigned int odt;
  40. };
  41. #define DDR_SYS_REG_VERSION (0x2)
  42. /*
  43. * sys_reg2 bitfield struct
  44. * [31] row_3_4_ch1
  45. * [30] row_3_4_ch0
  46. * [29:28] chinfo
  47. * [27] rank_ch1
  48. * [26:25] col_ch1
  49. * [24] bk_ch1
  50. * [23:22] cs0_row_ch1
  51. * [21:20] cs1_row_ch1
  52. * [19:18] bw_ch1
  53. * [17:16] dbw_ch1;
  54. * [15:13] ddrtype
  55. * [12] channelnum
  56. * [11] rank_ch0
  57. * [10:9] col_ch0
  58. * [8] bk_ch0
  59. * [7:6] cs0_row_ch0
  60. * [5:4] cs1_row_ch0
  61. * [3:2] bw_ch0
  62. * [1:0] dbw_ch0
  63. */
  64. #define SYS_REG_ENC_ROW_3_4(n, ch) ((n) << (30 + (ch)))
  65. #define SYS_REG_DEC_ROW_3_4(n, ch) (((n) >> (30 + (ch))) & 0x1)
  66. #define SYS_REG_ENC_CHINFO(ch) (1 << (28 + (ch)))
  67. #define SYS_REG_ENC_DDRTYPE(n) ((n) << 13)
  68. #define SYS_REG_DEC_DDRTYPE(n) (((n) >> 13) & 0x7)
  69. #define SYS_REG_ENC_NUM_CH(n) (((n) - 1) << 12)
  70. #define SYS_REG_DEC_NUM_CH(n) (1 + (((n) >> 12) & 0x1))
  71. #define SYS_REG_ENC_RANK(n, ch) (((n) - 1) << (11 + ((ch) * 16)))
  72. #define SYS_REG_DEC_RANK(n, ch) (1 + (((n) >> (11 + 16 * (ch))) & 0x1))
  73. #define SYS_REG_ENC_COL(n, ch) (((n) - 9) << (9 + ((ch) * 16)))
  74. #define SYS_REG_DEC_COL(n, ch) (9 + (((n) >> (9 + 16 * (ch))) & 0x3))
  75. #define SYS_REG_ENC_BK(n, ch) (((n) == 3 ? 0 : 1) << \
  76. (8 + ((ch) * 16)))
  77. #define SYS_REG_DEC_BK(n, ch) (3 - (((n) >> (8 + 16 * (ch))) & 0x1))
  78. #define SYS_REG_ENC_BW(n, ch) ((2 >> (n)) << (2 + ((ch) * 16)))
  79. #define SYS_REG_DEC_BW(n, ch) (2 >> (((n) >> (2 + 16 * (ch))) & 0x3))
  80. #define SYS_REG_ENC_DBW(n, ch) ((2 >> (n)) << (0 + ((ch) * 16)))
  81. #define SYS_REG_DEC_DBW(n, ch) (2 >> (((n) >> (0 + 16 * (ch))) & 0x3))
  82. /* sys reg 3 */
  83. #define SYS_REG_ENC_VERSION(n) ((n) << 28)
  84. #define SYS_REG_DEC_VERSION(n) (((n) >> 28) & 0xf)
  85. #define SYS_REG_ENC_CS0_ROW(n, os_reg2, os_reg3, ch) do { \
  86. (os_reg2) |= (((n) - 13) & 0x3) << (6 + 16 * (ch)); \
  87. (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
  88. (5 + 2 * (ch)); \
  89. } while (0)
  90. #define SYS_REG_DEC_CS0_ROW(os_reg2, os_reg3, ch) \
  91. ((((((os_reg2) >> (6 + 16 * (ch)) & 0x3) | \
  92. ((((os_reg3) >> (5 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12)
  93. #define SYS_REG_ENC_CS1_ROW(n, os_reg2, os_reg3, ch) do { \
  94. (os_reg2) &= (~(0x3 << (4 + 16 * (ch)))); \
  95. (os_reg3) &= (~(0x1 << (4 + 2 * (ch)))); \
  96. (os_reg2) |= (((n) - 13) & 0x3) << (4 + 16 * (ch)); \
  97. (os_reg3) |= ((((n) - 13) & 0x4) >> 2) << \
  98. (4 + 2 * (ch)); \
  99. } while (0)
  100. #define SYS_REG_DEC_CS1_ROW(os_reg2, os_reg3, ch) \
  101. ((((((os_reg2) >> (4 + 16 * (ch)) & 0x3) | \
  102. ((((os_reg3) >> (4 + 2 * (ch))) & 0x1) << 2)) + 1) & 0x7) + 12)
  103. #define SYS_REG_ENC_CS1_COL(n, ch) (((n) - 9) << (0 + 2 * (ch)))
  104. #define SYS_REG_DEC_CS1_COL(n, ch) (9 + (((n) >> (0 + 2 * (ch))) & 0x3))
  105. void sdram_print_dram_type(unsigned char dramtype);
  106. void sdram_print_ddr_info(struct sdram_cap_info *cap_info,
  107. struct sdram_base_params *base);
  108. void sdram_print_stride(unsigned int stride);
  109. void sdram_org_config(struct sdram_cap_info *cap_info,
  110. struct sdram_base_params *base,
  111. u32 *p_os_reg2, u32 *p_os_reg3, u32 channel);
  112. int sdram_detect_bw(struct sdram_cap_info *cap_info);
  113. int sdram_detect_cs(struct sdram_cap_info *cap_info);
  114. int sdram_detect_col(struct sdram_cap_info *cap_info,
  115. u32 coltmp);
  116. int sdram_detect_bank(struct sdram_cap_info *cap_info,
  117. u32 coltmp, u32 bktmp);
  118. int sdram_detect_bg(struct sdram_cap_info *cap_info,
  119. u32 coltmp);
  120. int sdram_detect_dbw(struct sdram_cap_info *cap_info, u32 dram_type);
  121. int sdram_detect_row(struct sdram_cap_info *cap_info,
  122. u32 coltmp, u32 bktmp, u32 rowtmp);
  123. int sdram_detect_row_3_4(struct sdram_cap_info *cap_info,
  124. u32 coltmp, u32 bktmp);
  125. int sdram_detect_high_row(struct sdram_cap_info *cap_info);
  126. int sdram_detect_cs1_row(struct sdram_cap_info *cap_info, u32 dram_type);
  127. u64 sdram_get_cs_cap(struct sdram_cap_info *cap_info, u32 cs, u32 dram_type);
  128. void sdram_copy_to_reg(u32 *dest, const u32 *src, u32 n);
  129. #endif