phy-bcm-sr-pcie.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) 2019 Broadcom
  4. */
  5. #include <common.h>
  6. #include <dm.h>
  7. #include <generic-phy.h>
  8. #include <asm/io.h>
  9. #include <linux/bitops.h>
  10. /* we have up to 8 PAXB based RC. The 9th one is always PAXC */
  11. #define SR_NR_PCIE_PHYS 8
  12. #define PCIE_PIPEMUX_CFG_OFFSET 0x10c
  13. #define PCIE_PIPEMUX_SELECT_STRAP GENMASK(3, 0)
  14. #define CDRU_STRAP_DATA_LSW_OFFSET 0x5c
  15. #define PCIE_PIPEMUX_SHIFT 19
  16. #define PCIE_PIPEMUX_MASK GENMASK(3, 0)
  17. /**
  18. * struct sr_pcie_phy_core - Stingray PCIe PHY core control
  19. *
  20. * @dev: pointer to device
  21. * @base: base register of PCIe SS
  22. * @cdru: CDRU base address
  23. * @pipemux: pipemuex strap
  24. */
  25. struct sr_pcie_phy_core {
  26. struct udevice *dev;
  27. void __iomem *base;
  28. void __iomem *cdru;
  29. u32 pipemux;
  30. };
  31. /*
  32. * PCIe PIPEMUX lookup table
  33. *
  34. * Each array index represents a PIPEMUX strap setting
  35. * The array element represents a bitmap where a set bit means the PCIe
  36. * core and associated serdes has been enabled as RC and is available for use
  37. */
  38. static const u8 pipemux_table[] = {
  39. /* PIPEMUX = 0, EP 1x16 */
  40. 0x00,
  41. /* PIPEMUX = 1, EP 1x8 + RC 1x8, core 7 */
  42. 0x80,
  43. /* PIPEMUX = 2, EP 4x4 */
  44. 0x00,
  45. /* PIPEMUX = 3, RC 2x8, cores 0, 7 */
  46. 0x81,
  47. /* PIPEMUX = 4, RC 4x4, cores 0, 1, 6, 7 */
  48. 0xc3,
  49. /* PIPEMUX = 5, RC 8x2, all 8 cores */
  50. 0xff,
  51. /* PIPEMUX = 6, RC 3x4 + 2x2, cores 0, 2, 3, 6, 7 */
  52. 0xcd,
  53. /* PIPEMUX = 7, RC 1x4 + 6x2, cores 0, 2, 3, 4, 5, 6, 7 */
  54. 0xfd,
  55. /* PIPEMUX = 8, EP 1x8 + RC 4x2, cores 4, 5, 6, 7 */
  56. 0xf0,
  57. /* PIPEMUX = 9, EP 1x8 + RC 2x4, cores 6, 7 */
  58. 0xc0,
  59. /* PIPEMUX = 10, EP 2x4 + RC 2x4, cores 1, 6 */
  60. 0x42,
  61. /* PIPEMUX = 11, EP 2x4 + RC 4x2, cores 2, 3, 4, 5 */
  62. 0x3c,
  63. /* PIPEMUX = 12, EP 1x4 + RC 6x2, cores 2, 3, 4, 5, 6, 7 */
  64. 0xfc,
  65. /* PIPEMUX = 13, RC 2x4 + RC 1x4 + 2x2, cores 2, 3, 6 */
  66. 0x4c,
  67. };
  68. /*
  69. * Return true if the strap setting is valid
  70. */
  71. static bool pipemux_strap_is_valid(u32 pipemux)
  72. {
  73. return !!(pipemux < ARRAY_SIZE(pipemux_table));
  74. }
  75. /*
  76. * Read the PCIe PIPEMUX from strap
  77. */
  78. static u32 pipemux_strap_read(struct sr_pcie_phy_core *core)
  79. {
  80. u32 pipemux;
  81. /*
  82. * Read PIPEMUX configuration register to determine the pipemux setting
  83. *
  84. * In the case when the value indicates using HW strap, fall back to
  85. * use HW strap
  86. */
  87. pipemux = readl(core->base + PCIE_PIPEMUX_CFG_OFFSET);
  88. pipemux &= PCIE_PIPEMUX_MASK;
  89. if (pipemux == PCIE_PIPEMUX_SELECT_STRAP) {
  90. pipemux = readl(core->cdru + CDRU_STRAP_DATA_LSW_OFFSET);
  91. pipemux >>= PCIE_PIPEMUX_SHIFT;
  92. pipemux &= PCIE_PIPEMUX_MASK;
  93. }
  94. return pipemux;
  95. }
  96. static int sr_pcie_phy_init(struct phy *phy)
  97. {
  98. struct sr_pcie_phy_core *core = dev_get_priv(phy->dev);
  99. unsigned int core_idx = phy->id;
  100. debug("%s %lx\n", __func__, phy->id);
  101. /*
  102. * Check whether this PHY is for root complex or not. If yes, return
  103. * zero so the host driver can proceed to enumeration. If not, return
  104. * an error and that will force the host driver to bail out
  105. */
  106. if (!!((pipemux_table[core->pipemux] >> core_idx) & 0x1))
  107. return 0;
  108. return -ENODEV;
  109. }
  110. static int sr_pcie_phy_xlate(struct phy *phy, struct ofnode_phandle_args *args)
  111. {
  112. debug("%s %d\n", __func__, args->args[0]);
  113. if (args->args_count && args->args[0] < SR_NR_PCIE_PHYS)
  114. phy->id = args->args[0];
  115. else
  116. return -ENODEV;
  117. return 0;
  118. }
  119. static const struct phy_ops sr_pcie_phy_ops = {
  120. .of_xlate = sr_pcie_phy_xlate,
  121. .init = sr_pcie_phy_init,
  122. };
  123. static int sr_pcie_phy_probe(struct udevice *dev)
  124. {
  125. struct sr_pcie_phy_core *core = dev_get_priv(dev);
  126. core->dev = dev;
  127. core->base = (void __iomem *)devfdt_get_addr_name(dev, "reg_base");
  128. core->cdru = (void __iomem *)devfdt_get_addr_name(dev, "cdru_base");
  129. debug("ip base %p\n", core->base);
  130. debug("cdru base %p\n", core->cdru);
  131. /* read the PCIe PIPEMUX strap setting */
  132. core->pipemux = pipemux_strap_read(core);
  133. if (!pipemux_strap_is_valid(core->pipemux)) {
  134. pr_err("invalid PCIe PIPEMUX strap %u\n", core->pipemux);
  135. return -EIO;
  136. }
  137. debug("%s %#x\n", __func__, core->pipemux);
  138. pr_info("Stingray PCIe PHY driver initialized\n");
  139. return 0;
  140. }
  141. static const struct udevice_id sr_pcie_phy_match_table[] = {
  142. { .compatible = "brcm,sr-pcie-phy" },
  143. { }
  144. };
  145. U_BOOT_DRIVER(sr_pcie_phy) = {
  146. .name = "sr-pcie-phy",
  147. .id = UCLASS_PHY,
  148. .probe = sr_pcie_phy_probe,
  149. .of_match = sr_pcie_phy_match_table,
  150. .ops = &sr_pcie_phy_ops,
  151. .platdata_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
  152. .priv_auto_alloc_size = sizeof(struct sr_pcie_phy_core),
  153. };