meson-gxl-usb3.c 6.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson GXL USB3 PHY driver
  4. *
  5. * Copyright (C) 2018 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2018 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstron@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <asm/io.h>
  12. #include <bitfield.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <generic-phy.h>
  16. #include <regmap.h>
  17. #include <clk.h>
  18. #include <linux/usb/otg.h>
  19. #include <asm/arch/usb-gx.h>
  20. #include <linux/bitops.h>
  21. #include <linux/compat.h>
  22. #include <linux/bitfield.h>
  23. #define USB_R0 0x00
  24. #define USB_R0_P30_FSEL_MASK GENMASK(5, 0)
  25. #define USB_R0_P30_PHY_RESET BIT(6)
  26. #define USB_R0_P30_TEST_POWERDOWN_HSP BIT(7)
  27. #define USB_R0_P30_TEST_POWERDOWN_SSP BIT(8)
  28. #define USB_R0_P30_ACJT_LEVEL_MASK GENMASK(13, 9)
  29. #define USB_R0_P30_TX_BOOST_LEVEL_MASK GENMASK(16, 14)
  30. #define USB_R0_P30_LANE0_TX2RX_LOOPBACK BIT(17)
  31. #define USB_R0_P30_LANE0_EXT_PCLK_REQ BIT(18)
  32. #define USB_R0_P30_PCS_RX_LOS_MASK_VAL_MASK GENMASK(28, 19)
  33. #define USB_R0_U2D_SS_SCALEDOWN_MODE_MASK GENMASK(30, 29)
  34. #define USB_R0_U2D_ACT BIT(31)
  35. #define USB_R1 0x04
  36. #define USB_R1_U3H_BIGENDIAN_GS BIT(0)
  37. #define USB_R1_U3H_PME_ENABLE BIT(1)
  38. #define USB_R1_U3H_HUB_PORT_OVERCURRENT_MASK GENMASK(6, 2)
  39. #define USB_R1_U3H_HUB_PORT_PERM_ATTACH_MASK GENMASK(11, 7)
  40. #define USB_R1_U3H_HOST_U2_PORT_DISABLE_MASK GENMASK(15, 12)
  41. #define USB_R1_U3H_HOST_U3_PORT_DISABLE BIT(16)
  42. #define USB_R1_U3H_HOST_PORT_POWER_CONTROL_PRESENT BIT(17)
  43. #define USB_R1_U3H_HOST_MSI_ENABLE BIT(18)
  44. #define USB_R1_U3H_FLADJ_30MHZ_REG_MASK GENMASK(24, 19)
  45. #define USB_R1_P30_PCS_TX_SWING_FULL_MASK GENMASK(31, 25)
  46. #define USB_R2 0x08
  47. #define USB_R2_P30_CR_DATA_IN_MASK GENMASK(15, 0)
  48. #define USB_R2_P30_CR_READ BIT(16)
  49. #define USB_R2_P30_CR_WRITE BIT(17)
  50. #define USB_R2_P30_CR_CAP_ADDR BIT(18)
  51. #define USB_R2_P30_CR_CAP_DATA BIT(19)
  52. #define USB_R2_P30_PCS_TX_DEEMPH_3P5DB_MASK GENMASK(25, 20)
  53. #define USB_R2_P30_PCS_TX_DEEMPH_6DB_MASK GENMASK(31, 26)
  54. #define USB_R3 0x0c
  55. #define USB_R3_P30_SSC_ENABLE BIT(0)
  56. #define USB_R3_P30_SSC_RANGE_MASK GENMASK(3, 1)
  57. #define USB_R3_P30_SSC_REF_CLK_SEL_MASK GENMASK(12, 4)
  58. #define USB_R3_P30_REF_SSP_EN BIT(13)
  59. #define USB_R3_P30_LOS_BIAS_MASK GENMASK(18, 16)
  60. #define USB_R3_P30_LOS_LEVEL_MASK GENMASK(23, 19)
  61. #define USB_R3_P30_MPLL_MULTIPLIER_MASK GENMASK(30, 24)
  62. #define USB_R4 0x10
  63. #define USB_R4_P21_PORT_RESET_0 BIT(0)
  64. #define USB_R4_P21_SLEEP_M0 BIT(1)
  65. #define USB_R4_MEM_PD_MASK GENMASK(3, 2)
  66. #define USB_R4_P21_ONLY BIT(4)
  67. #define USB_R5 0x14
  68. #define USB_R5_ID_DIG_SYNC BIT(0)
  69. #define USB_R5_ID_DIG_REG BIT(1)
  70. #define USB_R5_ID_DIG_CFG_MASK GENMASK(3, 2)
  71. #define USB_R5_ID_DIG_EN_0 BIT(4)
  72. #define USB_R5_ID_DIG_EN_1 BIT(5)
  73. #define USB_R5_ID_DIG_CURR BIT(6)
  74. #define USB_R5_ID_DIG_IRQ BIT(7)
  75. #define USB_R5_ID_DIG_TH_MASK GENMASK(15, 8)
  76. #define USB_R5_ID_DIG_CNT_MASK GENMASK(23, 16)
  77. /* read-only register */
  78. #define USB_R6 0x18
  79. #define USB_R6_P30_CR_DATA_OUT_MASK GENMASK(15, 0)
  80. #define USB_R6_P30_CR_ACK BIT(16)
  81. struct phy_meson_gxl_usb3_priv {
  82. struct regmap *regmap;
  83. #if CONFIG_IS_ENABLED(CLK)
  84. struct clk clk;
  85. #endif
  86. };
  87. void phy_meson_gxl_usb3_set_mode(struct phy *phy, enum usb_dr_mode mode)
  88. {
  89. struct udevice *dev = phy->dev;
  90. struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
  91. uint val;
  92. switch (mode) {
  93. case USB_DR_MODE_UNKNOWN:
  94. case USB_DR_MODE_HOST:
  95. case USB_DR_MODE_OTG:
  96. regmap_read(priv->regmap, USB_R0, &val);
  97. val &= ~USB_R0_U2D_ACT;
  98. regmap_write(priv->regmap, USB_R0, val);
  99. regmap_read(priv->regmap, USB_R4, &val);
  100. val &= ~USB_R4_P21_SLEEP_M0;
  101. regmap_write(priv->regmap, USB_R4, val);
  102. break;
  103. case USB_DR_MODE_PERIPHERAL:
  104. regmap_read(priv->regmap, USB_R0, &val);
  105. val |= USB_R0_U2D_ACT;
  106. regmap_write(priv->regmap, USB_R0, val);
  107. regmap_read(priv->regmap, USB_R4, &val);
  108. val |= USB_R4_P21_SLEEP_M0;
  109. regmap_write(priv->regmap, USB_R4, val);
  110. break;
  111. }
  112. }
  113. static int phy_meson_gxl_usb3_power_on(struct phy *phy)
  114. {
  115. struct udevice *dev = phy->dev;
  116. struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
  117. uint val;
  118. regmap_read(priv->regmap, USB_R5, &val);
  119. val |= USB_R5_ID_DIG_EN_0;
  120. val |= USB_R5_ID_DIG_EN_1;
  121. val &= ~USB_R5_ID_DIG_TH_MASK;
  122. val |= FIELD_PREP(USB_R5_ID_DIG_TH_MASK, 0xff);
  123. regmap_write(priv->regmap, USB_R5, val);
  124. phy_meson_gxl_usb3_set_mode(phy, USB_DR_MODE_HOST);
  125. return 0;
  126. }
  127. static int phy_meson_gxl_usb3_power_off(struct phy *phy)
  128. {
  129. struct udevice *dev = phy->dev;
  130. struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
  131. uint val;
  132. regmap_read(priv->regmap, USB_R5, &val);
  133. val &= ~USB_R5_ID_DIG_EN_0;
  134. val &= ~USB_R5_ID_DIG_EN_1;
  135. regmap_write(priv->regmap, USB_R5, val);
  136. return 0;
  137. }
  138. static int phy_meson_gxl_usb3_init(struct phy *phy)
  139. {
  140. struct udevice *dev = phy->dev;
  141. struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
  142. uint val;
  143. regmap_read(priv->regmap, USB_R1, &val);
  144. val &= ~USB_R1_U3H_FLADJ_30MHZ_REG_MASK;
  145. val |= FIELD_PREP(USB_R1_U3H_FLADJ_30MHZ_REG_MASK, 0x20);
  146. regmap_write(priv->regmap, USB_R1, val);
  147. return 0;
  148. }
  149. struct phy_ops meson_gxl_usb3_phy_ops = {
  150. .init = phy_meson_gxl_usb3_init,
  151. .power_on = phy_meson_gxl_usb3_power_on,
  152. .power_off = phy_meson_gxl_usb3_power_off,
  153. };
  154. int meson_gxl_usb3_phy_probe(struct udevice *dev)
  155. {
  156. struct phy_meson_gxl_usb3_priv *priv = dev_get_priv(dev);
  157. int ret;
  158. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  159. if (ret)
  160. return ret;
  161. #if CONFIG_IS_ENABLED(CLK)
  162. ret = clk_get_by_index(dev, 0, &priv->clk);
  163. if (ret < 0)
  164. return ret;
  165. ret = clk_enable(&priv->clk);
  166. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  167. pr_err("failed to enable PHY clock\n");
  168. clk_free(&priv->clk);
  169. return ret;
  170. }
  171. #endif
  172. return 0;
  173. }
  174. static const struct udevice_id meson_gxl_usb3_phy_ids[] = {
  175. { .compatible = "amlogic,meson-gxl-usb3-phy" },
  176. { }
  177. };
  178. U_BOOT_DRIVER(meson_gxl_usb3_phy) = {
  179. .name = "meson_gxl_usb3_phy",
  180. .id = UCLASS_PHY,
  181. .of_match = meson_gxl_usb3_phy_ids,
  182. .probe = meson_gxl_usb3_phy_probe,
  183. .ops = &meson_gxl_usb3_phy_ops,
  184. .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb3_priv),
  185. };