meson-gxl-usb2.c 6.8 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Meson GXL and GXM USB2 PHY driver
  4. *
  5. * Copyright (C) 2017 Martin Blumenstingl <martin.blumenstingl@googlemail.com>
  6. * Copyright (C) 2018 BayLibre, SAS
  7. * Author: Neil Armstrong <narmstron@baylibre.com>
  8. */
  9. #include <common.h>
  10. #include <malloc.h>
  11. #include <asm/io.h>
  12. #include <bitfield.h>
  13. #include <dm.h>
  14. #include <errno.h>
  15. #include <generic-phy.h>
  16. #include <regmap.h>
  17. #include <linux/delay.h>
  18. #include <power/regulator.h>
  19. #include <clk.h>
  20. #include <linux/usb/otg.h>
  21. #include <asm/arch/usb-gx.h>
  22. #include <linux/bitops.h>
  23. #include <linux/compat.h>
  24. /* bits [31:27] are read-only */
  25. #define U2P_R0 0x0
  26. #define U2P_R0_BYPASS_SEL BIT(0)
  27. #define U2P_R0_BYPASS_DM_EN BIT(1)
  28. #define U2P_R0_BYPASS_DP_EN BIT(2)
  29. #define U2P_R0_TXBITSTUFF_ENH BIT(3)
  30. #define U2P_R0_TXBITSTUFF_EN BIT(4)
  31. #define U2P_R0_DM_PULLDOWN BIT(5)
  32. #define U2P_R0_DP_PULLDOWN BIT(6)
  33. #define U2P_R0_DP_VBUS_VLD_EXT_SEL BIT(7)
  34. #define U2P_R0_DP_VBUS_VLD_EXT BIT(8)
  35. #define U2P_R0_ADP_PRB_EN BIT(9)
  36. #define U2P_R0_ADP_DISCHARGE BIT(10)
  37. #define U2P_R0_ADP_CHARGE BIT(11)
  38. #define U2P_R0_DRV_VBUS BIT(12)
  39. #define U2P_R0_ID_PULLUP BIT(13)
  40. #define U2P_R0_LOOPBACK_EN_B BIT(14)
  41. #define U2P_R0_OTG_DISABLE BIT(15)
  42. #define U2P_R0_COMMON_ONN BIT(16)
  43. #define U2P_R0_FSEL_MASK GENMASK(19, 17)
  44. #define U2P_R0_REF_CLK_SEL_MASK GENMASK(21, 20)
  45. #define U2P_R0_POWER_ON_RESET BIT(22)
  46. #define U2P_R0_V_ATE_TEST_EN_B_MASK GENMASK(24, 23)
  47. #define U2P_R0_ID_SET_ID_DQ BIT(25)
  48. #define U2P_R0_ATE_RESET BIT(26)
  49. #define U2P_R0_FSV_MINUS BIT(27)
  50. #define U2P_R0_FSV_PLUS BIT(28)
  51. #define U2P_R0_BYPASS_DM_DATA BIT(29)
  52. #define U2P_R0_BYPASS_DP_DATA BIT(30)
  53. #define U2P_R1 0x4
  54. #define U2P_R1_BURN_IN_TEST BIT(0)
  55. #define U2P_R1_ACA_ENABLE BIT(1)
  56. #define U2P_R1_DCD_ENABLE BIT(2)
  57. #define U2P_R1_VDAT_SRC_EN_B BIT(3)
  58. #define U2P_R1_VDAT_DET_EN_B BIT(4)
  59. #define U2P_R1_CHARGES_SEL BIT(5)
  60. #define U2P_R1_TX_PREEMP_PULSE_TUNE BIT(6)
  61. #define U2P_R1_TX_PREEMP_AMP_TUNE_MASK GENMASK(8, 7)
  62. #define U2P_R1_TX_RES_TUNE_MASK GENMASK(10, 9)
  63. #define U2P_R1_TX_RISE_TUNE_MASK GENMASK(12, 11)
  64. #define U2P_R1_TX_VREF_TUNE_MASK GENMASK(16, 13)
  65. #define U2P_R1_TX_FSLS_TUNE_MASK GENMASK(20, 17)
  66. #define U2P_R1_TX_HSXV_TUNE_MASK GENMASK(22, 21)
  67. #define U2P_R1_OTG_TUNE_MASK GENMASK(25, 23)
  68. #define U2P_R1_SQRX_TUNE_MASK GENMASK(28, 26)
  69. #define U2P_R1_COMP_DIS_TUNE_MASK GENMASK(31, 29)
  70. /* bits [31:14] are read-only */
  71. #define U2P_R2 0x8
  72. #define U2P_R2_TESTDATA_IN_MASK GENMASK(7, 0)
  73. #define U2P_R2_TESTADDR_MASK GENMASK(11, 8)
  74. #define U2P_R2_TESTDATA_OUT_SEL BIT(12)
  75. #define U2P_R2_TESTCLK BIT(13)
  76. #define U2P_R2_TESTDATA_OUT_MASK GENMASK(17, 14)
  77. #define U2P_R2_ACA_PIN_RANGE_C BIT(18)
  78. #define U2P_R2_ACA_PIN_RANGE_B BIT(19)
  79. #define U2P_R2_ACA_PIN_RANGE_A BIT(20)
  80. #define U2P_R2_ACA_PIN_GND BIT(21)
  81. #define U2P_R2_ACA_PIN_FLOAT BIT(22)
  82. #define U2P_R2_CHARGE_DETECT BIT(23)
  83. #define U2P_R2_DEVICE_SESSION_VALID BIT(24)
  84. #define U2P_R2_ADP_PROBE BIT(25)
  85. #define U2P_R2_ADP_SENSE BIT(26)
  86. #define U2P_R2_SESSION_END BIT(27)
  87. #define U2P_R2_VBUS_VALID BIT(28)
  88. #define U2P_R2_B_VALID BIT(29)
  89. #define U2P_R2_A_VALID BIT(30)
  90. #define U2P_R2_ID_DIG BIT(31)
  91. #define U2P_R3 0xc
  92. #define RESET_COMPLETE_TIME 500
  93. struct phy_meson_gxl_usb2_priv {
  94. struct regmap *regmap;
  95. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  96. struct udevice *phy_supply;
  97. #endif
  98. #if CONFIG_IS_ENABLED(CLK)
  99. struct clk clk;
  100. #endif
  101. };
  102. static void phy_meson_gxl_usb2_reset(struct phy_meson_gxl_usb2_priv *priv)
  103. {
  104. uint val;
  105. regmap_read(priv->regmap, U2P_R0, &val);
  106. /* reset the PHY and wait until settings are stabilized */
  107. val |= U2P_R0_POWER_ON_RESET;
  108. regmap_write(priv->regmap, U2P_R0, val);
  109. udelay(RESET_COMPLETE_TIME);
  110. val &= ~U2P_R0_POWER_ON_RESET;
  111. regmap_write(priv->regmap, U2P_R0, val);
  112. udelay(RESET_COMPLETE_TIME);
  113. }
  114. void phy_meson_gxl_usb2_set_mode(struct phy *phy, enum usb_dr_mode mode)
  115. {
  116. struct udevice *dev = phy->dev;
  117. struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
  118. uint val;
  119. regmap_read(priv->regmap, U2P_R0, &val);
  120. switch (mode) {
  121. case USB_DR_MODE_UNKNOWN:
  122. case USB_DR_MODE_HOST:
  123. case USB_DR_MODE_OTG:
  124. val |= U2P_R0_DM_PULLDOWN;
  125. val |= U2P_R0_DP_PULLDOWN;
  126. val &= ~U2P_R0_ID_PULLUP;
  127. break;
  128. case USB_DR_MODE_PERIPHERAL:
  129. val &= ~U2P_R0_DM_PULLDOWN;
  130. val &= ~U2P_R0_DP_PULLDOWN;
  131. val |= U2P_R0_ID_PULLUP;
  132. break;
  133. }
  134. regmap_write(priv->regmap, U2P_R0, val);
  135. phy_meson_gxl_usb2_reset(priv);
  136. }
  137. static int phy_meson_gxl_usb2_power_on(struct phy *phy)
  138. {
  139. struct udevice *dev = phy->dev;
  140. struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
  141. uint val;
  142. regmap_read(priv->regmap, U2P_R0, &val);
  143. /* power on the PHY by taking it out of reset mode */
  144. val &= ~U2P_R0_POWER_ON_RESET;
  145. regmap_write(priv->regmap, U2P_R0, val);
  146. phy_meson_gxl_usb2_set_mode(phy, USB_DR_MODE_HOST);
  147. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  148. if (priv->phy_supply) {
  149. int ret = regulator_set_enable(priv->phy_supply, true);
  150. if (ret)
  151. return ret;
  152. }
  153. #endif
  154. return 0;
  155. }
  156. static int phy_meson_gxl_usb2_power_off(struct phy *phy)
  157. {
  158. struct udevice *dev = phy->dev;
  159. struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
  160. uint val;
  161. regmap_read(priv->regmap, U2P_R0, &val);
  162. /* power off the PHY by putting it into reset mode */
  163. val |= U2P_R0_POWER_ON_RESET;
  164. regmap_write(priv->regmap, U2P_R0, val);
  165. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  166. if (priv->phy_supply) {
  167. int ret = regulator_set_enable(priv->phy_supply, false);
  168. if (ret) {
  169. pr_err("Error disabling PHY supply\n");
  170. return ret;
  171. }
  172. }
  173. #endif
  174. return 0;
  175. }
  176. struct phy_ops meson_gxl_usb2_phy_ops = {
  177. .power_on = phy_meson_gxl_usb2_power_on,
  178. .power_off = phy_meson_gxl_usb2_power_off,
  179. };
  180. int meson_gxl_usb2_phy_probe(struct udevice *dev)
  181. {
  182. struct phy_meson_gxl_usb2_priv *priv = dev_get_priv(dev);
  183. int ret;
  184. ret = regmap_init_mem(dev_ofnode(dev), &priv->regmap);
  185. if (ret)
  186. return ret;
  187. #if CONFIG_IS_ENABLED(CLK)
  188. ret = clk_get_by_index(dev, 0, &priv->clk);
  189. if (ret < 0)
  190. return ret;
  191. ret = clk_enable(&priv->clk);
  192. if (ret && ret != -ENOSYS && ret != -ENOTSUPP) {
  193. pr_err("failed to enable PHY clock\n");
  194. clk_free(&priv->clk);
  195. return ret;
  196. }
  197. #endif
  198. #if CONFIG_IS_ENABLED(DM_REGULATOR)
  199. ret = device_get_supply_regulator(dev, "phy-supply", &priv->phy_supply);
  200. if (ret && ret != -ENOENT) {
  201. pr_err("Failed to get PHY regulator\n");
  202. return ret;
  203. }
  204. #endif
  205. return 0;
  206. }
  207. static const struct udevice_id meson_gxl_usb2_phy_ids[] = {
  208. { .compatible = "amlogic,meson-gxl-usb2-phy" },
  209. { }
  210. };
  211. U_BOOT_DRIVER(meson_gxl_usb2_phy) = {
  212. .name = "meson_gxl_usb2_phy",
  213. .id = UCLASS_PHY,
  214. .of_match = meson_gxl_usb2_phy_ids,
  215. .probe = meson_gxl_usb2_phy_probe,
  216. .ops = &meson_gxl_usb2_phy_ops,
  217. .priv_auto_alloc_size = sizeof(struct phy_meson_gxl_usb2_priv),
  218. };