imximage.cfg 5.5 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175
  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de>
  4. *
  5. * Refer doc/imx/mkimage/imximage.txt for more details about how-to configure
  6. * and create imximage boot image
  7. *
  8. * The syntax is taken as close as possible with the kwbimage
  9. */
  10. /* image version */
  11. IMAGE_VERSION 2
  12. /*
  13. * Boot Device : one of
  14. * sd, nand
  15. */
  16. BOOT_FROM sd
  17. /*
  18. * Device Configuration Data (DCD)
  19. *
  20. * Each entry must have the format:
  21. * Addr-type Address Value
  22. *
  23. * where:
  24. * Addr-type register length (1,2 or 4 bytes)
  25. * Address absolute address of the register
  26. * value value to be stored in the register
  27. */
  28. #define __ASSEMBLY__
  29. #include <config.h>
  30. /* Enable all clocks */
  31. DATA 4 0x020c4068 0xffffffff
  32. DATA 4 0x020c406c 0xffffffff
  33. DATA 4 0x020c4070 0xffffffff
  34. DATA 4 0x020c4074 0xffffffff
  35. DATA 4 0x020c4078 0xffffffff
  36. DATA 4 0x020c407c 0xffffffff
  37. DATA 4 0x020c4080 0xffffffff
  38. DATA 4 0x020c4084 0xffffffff
  39. /* ddr io type */
  40. DATA 4 0x020e04b4 0x000C0000 /* IOMUXC_SW_PAD_CTL_GRP_DDR_TYPE */
  41. DATA 4 0x020e04ac 0x00000000 /* IOMUXC_SW_PAD_CTL_GRP_DDRPKE */
  42. /* clock */
  43. DATA 4 0x020e027c 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDCLK0_P */
  44. /* control and address */
  45. DATA 4 0x020E0250 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_CAS */
  46. DATA 4 0x020E024C 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RAS */
  47. DATA 4 0x020E0490 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_ADDDS */
  48. DATA 4 0x020E0288 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_RESET */
  49. DATA 4 0x020E0270 0x00000000 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDBA2 - DSE can be
  50. configured using Group Control Register:
  51. IOMUXC_SW_PAD_CTL_GRP_CTLDS */
  52. DATA 4 0x020E0260 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT0 */
  53. DATA 4 0x020E0264 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_ODT1 */
  54. DATA 4 0x020E04A0 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_CTLDS */
  55. /* data strobes */
  56. DATA 4 0x020e0494 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE_CTL */
  57. DATA 4 0x020e0280 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS0_P */
  58. DATA 4 0x020e0284 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_SDQS1_P */
  59. /* data */
  60. DATA 4 0x020E04B0 0x00020000 /* IOMUXC_SW_PAD_CTL_GRP_DDRMODE */
  61. DATA 4 0x020E0498 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B0DS */
  62. DATA 4 0x020E04A4 0x00000030 /* IOMUXC_SW_PAD_CTL_GRP_B1DS */
  63. DATA 4 0x020E0244 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM0 */
  64. DATA 4 0x020E0248 0x00000030 /* IOMUXC_SW_PAD_CTL_PAD_DRAM_DQM1 */
  65. /*
  66. * DDR Controller Registers
  67. *
  68. * Manufacturer: IM
  69. * Device Part Number: IME1G16D3EEBG-15EI
  70. * Clock Freq.: 400MHz
  71. * Density per CS in Gb: 1
  72. * Chip Selects used: 1
  73. * Number of Banks: 8
  74. * Row address: 13
  75. * Column address: 10
  76. * Data bus width 16
  77. */
  78. DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
  79. during MMDC set up */
  80. /*
  81. * Calibration setup
  82. */
  83. DATA 4 0x021b0800 0xA1390003 /* DDR_PHY_P0_MPZQHWCTRL, enable both one-time &
  84. periodic HW ZQ calibration. */
  85. /*
  86. * For target board, may need to run write leveling calibration to fine tune
  87. * these settings.
  88. */
  89. DATA 4 0x021b080c 0x00000000
  90. /* Read DQS Gating calibration */
  91. DATA 4 0x021b083c 0x4164015C /* MPDGCTRL0 PHY0 */
  92. /* Read calibration */
  93. DATA 4 0x021b0848 0x40404446 /* MPRDDLCTL PHY0 */
  94. /* Write calibration */
  95. DATA 4 0x021b0850 0x40405A52 /* MPWRDLCTL PHY0 */
  96. /*
  97. * read data bit delay: (3 is the reccommended default value, although out of
  98. * reset value is 0)
  99. */
  100. DATA 4 0x021b081c 0x33333333 /* DDR_PHY_P0_MPREDQBY0DL3 */
  101. DATA 4 0x021b0820 0x33333333 /* DDR_PHY_P0_MPREDQBY1DL3 */
  102. DATA 4 0x021b082c 0xF3333333
  103. DATA 4 0x021b0830 0xF3333333
  104. DATA 4 0x021b08c0 0x00921012
  105. /* Clock Fine Tuning */
  106. DATA 4 0x021B0858 0x00000F00 /* [MMDC_MPSDCTRL] MMDC PHY CK Control Register */
  107. /* Complete calibration by forced measurement: */
  108. DATA 4 0x021b08b8 0x00000800 /* DDR_PHY_P0_MPMUR0, frc_msr */
  109. /*
  110. * Calibration setup end
  111. */
  112. /* MMDC init: */
  113. DATA 4 0x021b0004 0x0002002D /* MMDC0_MDPDC */
  114. DATA 4 0x021b0008 0x1B333030 /* MMDC0_MDOTC */
  115. DATA 4 0x021b000c 0x3F4352F3 /* MMDC0_MDCFG0 */
  116. DATA 4 0x021b0010 0xB66D0B63 /* MMDC0_MDCFG1 */
  117. DATA 4 0x021b0014 0x01FF00DB /* MMDC0_MDCFG2 */
  118. /*
  119. * MDMISC: RALAT kept to the high level of 5.
  120. * MDMISC: consider reducing RALAT if your 528MHz board design allow that.
  121. * Lower RALAT benefits:
  122. * a. better operation at low frequency, for LPDDR2 freq < 100MHz, change RALAT
  123. * to 3
  124. * b. Small performence improvment
  125. */
  126. DATA 4 0x021b0018 0x00201740 /* MMDC0_MDMISC */
  127. DATA 4 0x021b001c 0x00008000 /* MMDC0_MDSCR, set the Configuration request bit
  128. during MMDC set up */
  129. DATA 4 0x021b002c 0x000026D2 /* MMDC0_MDRWD */
  130. DATA 4 0x021b0030 0x00431023 /* MMDC0_MDOR */
  131. DATA 4 0x021b0040 0x00000047 /* Chan0 CS0_END */
  132. DATA 4 0x021b0000 0x82180000 /* MMDC0_MDCTL */
  133. /* Mode register writes */
  134. DATA 4 0x021b001c 0x02008032 /* MMDC0_MDSCR, MR2 write, CS0 */
  135. DATA 4 0x021b001c 0x00008033 /* MMDC0_MDSCR, MR3 write, CS0 */
  136. DATA 4 0x021b001c 0x00048031 /* MMDC0_MDSCR, MR1 write, CS0 */
  137. DATA 4 0x021b001c 0x15208030 /* MMDC0_MDSCR, MR0 write, CS0 */
  138. DATA 4 0x021b001c 0x04008040 /* MMDC0_MDSCR, ZQ calibration command sent to
  139. device on CS0 */
  140. DATA 4 0x021b0020 0x00000800 /* MMDC0_MDREF */
  141. DATA 4 0x021b0818 0x00000227 /* DDR_PHY_P0_MPODTCTRL */
  142. DATA 4 0x021b0004 0x0002556D /* MMDC0_MDPDC now SDCTL power down enabled */
  143. DATA 4 0x021b0404 0x00011006 /* MMDC0_MAPSR ADOPT power down enabled, MMDC will
  144. enter automatically to self-refresh while the
  145. number of idle cycle reached. */
  146. DATA 4 0x021b001c 0x00000000 /* MMDC0_MDSCR, clear this register (especially
  147. the configuration bit as initialization is
  148. complete) */