evm.c 7.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2004-2011
  4. * Texas Instruments, <www.ti.com>
  5. *
  6. * Author :
  7. * Manikandan Pillai <mani.pillai@ti.com>
  8. *
  9. * Derived from Beagle Board and 3430 SDP code by
  10. * Richard Woodruff <r-woodruff2@ti.com>
  11. * Syed Mohammed Khasim <khasim@ti.com>
  12. */
  13. #include <common.h>
  14. #include <dm.h>
  15. #include <env.h>
  16. #include <ns16550.h>
  17. #include <netdev.h>
  18. #include <serial.h>
  19. #include <asm/io.h>
  20. #include <asm/arch/mem.h>
  21. #include <asm/arch/mux.h>
  22. #include <asm/arch/sys_proto.h>
  23. #include <asm/arch/mmc_host_def.h>
  24. #include <asm/gpio.h>
  25. #include <i2c.h>
  26. #include <twl4030.h>
  27. #include <asm/mach-types.h>
  28. #include <asm/omap_musb.h>
  29. #include <linux/mtd/rawnand.h>
  30. #include <linux/usb/ch9.h>
  31. #include <linux/usb/gadget.h>
  32. #include <linux/usb/musb.h>
  33. #include "evm.h"
  34. #define OMAP3EVM_GPIO_ETH_RST_GEN1 64
  35. #define OMAP3EVM_GPIO_ETH_RST_GEN2 7
  36. DECLARE_GLOBAL_DATA_PTR;
  37. static u32 omap3_evm_version;
  38. u32 get_omap3_evm_rev(void)
  39. {
  40. return omap3_evm_version;
  41. }
  42. static void omap3_evm_get_revision(void)
  43. {
  44. #if defined(CONFIG_CMD_NET)
  45. /*
  46. * Board revision can be ascertained only by identifying
  47. * the Ethernet chipset.
  48. */
  49. unsigned int smsc_id;
  50. /* Ethernet PHY ID is stored at ID_REV register */
  51. smsc_id = readl(CONFIG_SMC911X_BASE + 0x50) & 0xFFFF0000;
  52. printf("Read back SMSC id 0x%x\n", smsc_id);
  53. switch (smsc_id) {
  54. /* SMSC9115 chipset */
  55. case 0x01150000:
  56. omap3_evm_version = OMAP3EVM_BOARD_GEN_1;
  57. break;
  58. /* SMSC 9220 chipset */
  59. case 0x92200000:
  60. default:
  61. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  62. }
  63. #else /* !CONFIG_CMD_NET */
  64. #if defined(CONFIG_STATIC_BOARD_REV)
  65. /* Look for static defintion of the board revision */
  66. omap3_evm_version = CONFIG_STATIC_BOARD_REV;
  67. #else
  68. /* Fallback to the default above */
  69. omap3_evm_version = OMAP3EVM_BOARD_GEN_2;
  70. #endif /* CONFIG_STATIC_BOARD_REV */
  71. #endif /* CONFIG_CMD_NET */
  72. }
  73. #if defined(CONFIG_USB_MUSB_GADGET) || defined(CONFIG_USB_MUSB_HOST)
  74. /* MUSB port on OMAP3EVM Rev >= E requires extvbus programming. */
  75. u8 omap3_evm_need_extvbus(void)
  76. {
  77. u8 retval = 0;
  78. if (get_omap3_evm_rev() >= OMAP3EVM_BOARD_GEN_2)
  79. retval = 1;
  80. return retval;
  81. }
  82. #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
  83. /*
  84. * Routine: board_init
  85. * Description: Early hardware init.
  86. */
  87. int board_init(void)
  88. {
  89. gpmc_init(); /* in SRAM or SDRAM, finish GPMC */
  90. /* board id for Linux */
  91. gd->bd->bi_arch_number = MACH_TYPE_OMAP3EVM;
  92. /* boot param addr */
  93. gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100);
  94. return 0;
  95. }
  96. #if defined(CONFIG_SPL_OS_BOOT)
  97. int spl_start_uboot(void)
  98. {
  99. /* break into full u-boot on 'c' */
  100. if (serial_tstc() && serial_getc() == 'c')
  101. return 1;
  102. return 0;
  103. }
  104. #endif /* CONFIG_SPL_OS_BOOT */
  105. #if defined(CONFIG_SPL_BUILD)
  106. /*
  107. * Routine: get_board_mem_timings
  108. * Description: If we use SPL then there is no x-loader nor config header
  109. * so we have to setup the DDR timings ourself on the first bank. This
  110. * provides the timing values back to the function that configures
  111. * the memory.
  112. */
  113. void get_board_mem_timings(struct board_sdrc_timings *timings)
  114. {
  115. int pop_mfr, pop_id;
  116. /*
  117. * We need to identify what PoP memory is on the board so that
  118. * we know what timings to use. To map the ID values please see
  119. * nand_ids.c
  120. */
  121. identify_nand_chip(&pop_mfr, &pop_id);
  122. if (pop_mfr == NAND_MFR_HYNIX && pop_id == 0xbc) {
  123. /* 256MB DDR */
  124. timings->mcfg = HYNIX_V_MCFG_200(256 << 20);
  125. timings->ctrla = HYNIX_V_ACTIMA_200;
  126. timings->ctrlb = HYNIX_V_ACTIMB_200;
  127. } else {
  128. /* 128MB DDR */
  129. timings->mcfg = MICRON_V_MCFG_165(128 << 20);
  130. timings->ctrla = MICRON_V_ACTIMA_165;
  131. timings->ctrlb = MICRON_V_ACTIMB_165;
  132. }
  133. timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz;
  134. timings->mr = MICRON_V_MR_165;
  135. }
  136. #endif /* CONFIG_SPL_BUILD */
  137. #if defined(CONFIG_USB_MUSB_OMAP2PLUS)
  138. static struct musb_hdrc_config musb_config = {
  139. .multipoint = 1,
  140. .dyn_fifo = 1,
  141. .num_eps = 16,
  142. .ram_bits = 12,
  143. };
  144. static struct omap_musb_board_data musb_board_data = {
  145. .interface_type = MUSB_INTERFACE_ULPI,
  146. };
  147. static struct musb_hdrc_platform_data musb_plat = {
  148. #if defined(CONFIG_USB_MUSB_HOST)
  149. .mode = MUSB_HOST,
  150. #elif defined(CONFIG_USB_MUSB_GADGET)
  151. .mode = MUSB_PERIPHERAL,
  152. #else
  153. #error "Please define either CONFIG_USB_MUSB_HOST or CONFIG_USB_MUSB_GADGET"
  154. #endif /* CONFIG_USB_MUSB_{GADGET,HOST} */
  155. .config = &musb_config,
  156. .power = 100,
  157. .platform_ops = &omap2430_ops,
  158. .board_data = &musb_board_data,
  159. };
  160. #endif /* CONFIG_USB_MUSB_OMAP2PLUS */
  161. /*
  162. * Routine: misc_init_r
  163. * Description: Init ethernet (done here so udelay works)
  164. */
  165. int misc_init_r(void)
  166. {
  167. twl4030_power_init();
  168. #ifdef CONFIG_SYS_I2C_OMAP24XX
  169. i2c_init(CONFIG_SYS_OMAP24_I2C_SPEED, CONFIG_SYS_OMAP24_I2C_SLAVE);
  170. #endif
  171. #if defined(CONFIG_CMD_NET)
  172. setup_net_chip();
  173. #endif
  174. omap3_evm_get_revision();
  175. #if defined(CONFIG_CMD_NET)
  176. reset_net_chip();
  177. #endif
  178. omap_die_id_display();
  179. #if defined(CONFIG_USB_MUSB_OMAP2PLUS)
  180. musb_register(&musb_plat, &musb_board_data, (void *)MUSB_BASE);
  181. #endif
  182. #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET)
  183. omap_die_id_usbethaddr();
  184. #endif
  185. return 0;
  186. }
  187. /*
  188. * Routine: set_muxconf_regs
  189. * Description: Setting up the configuration Mux registers specific to the
  190. * hardware. Many pins need to be moved from protect to primary
  191. * mode.
  192. */
  193. void set_muxconf_regs(void)
  194. {
  195. MUX_EVM();
  196. }
  197. #if defined(CONFIG_CMD_NET)
  198. /*
  199. * Routine: setup_net_chip
  200. * Description: Setting up the configuration GPMC registers specific to the
  201. * Ethernet hardware.
  202. */
  203. static void setup_net_chip(void)
  204. {
  205. struct ctrl *ctrl_base = (struct ctrl *)OMAP34XX_CTRL_BASE;
  206. /* Configure GPMC registers */
  207. writel(NET_GPMC_CONFIG1, &gpmc_cfg->cs[5].config1);
  208. writel(NET_GPMC_CONFIG2, &gpmc_cfg->cs[5].config2);
  209. writel(NET_GPMC_CONFIG3, &gpmc_cfg->cs[5].config3);
  210. writel(NET_GPMC_CONFIG4, &gpmc_cfg->cs[5].config4);
  211. writel(NET_GPMC_CONFIG5, &gpmc_cfg->cs[5].config5);
  212. writel(NET_GPMC_CONFIG6, &gpmc_cfg->cs[5].config6);
  213. writel(NET_GPMC_CONFIG7, &gpmc_cfg->cs[5].config7);
  214. /* Enable off mode for NWE in PADCONF_GPMC_NWE register */
  215. writew(readw(&ctrl_base ->gpmc_nwe) | 0x0E00, &ctrl_base->gpmc_nwe);
  216. /* Enable off mode for NOE in PADCONF_GPMC_NADV_ALE register */
  217. writew(readw(&ctrl_base->gpmc_noe) | 0x0E00, &ctrl_base->gpmc_noe);
  218. /* Enable off mode for ALE in PADCONF_GPMC_NADV_ALE register */
  219. writew(readw(&ctrl_base->gpmc_nadv_ale) | 0x0E00,
  220. &ctrl_base->gpmc_nadv_ale);
  221. }
  222. /**
  223. * Reset the ethernet chip.
  224. */
  225. static void reset_net_chip(void)
  226. {
  227. int ret;
  228. int rst_gpio;
  229. if (get_omap3_evm_rev() == OMAP3EVM_BOARD_GEN_1) {
  230. rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN1;
  231. } else {
  232. rst_gpio = OMAP3EVM_GPIO_ETH_RST_GEN2;
  233. }
  234. ret = gpio_request(rst_gpio, "");
  235. if (ret < 0) {
  236. printf("Unable to get GPIO %d\n", rst_gpio);
  237. return ;
  238. }
  239. /* Configure as output */
  240. gpio_direction_output(rst_gpio, 0);
  241. /* Send a pulse on the GPIO pin */
  242. gpio_set_value(rst_gpio, 1);
  243. udelay(1);
  244. gpio_set_value(rst_gpio, 0);
  245. udelay(1);
  246. gpio_set_value(rst_gpio, 1);
  247. }
  248. int board_eth_init(bd_t *bis)
  249. {
  250. #if defined(CONFIG_SMC911X)
  251. env_set("ethaddr", NULL);
  252. return smc911x_initialize(0, CONFIG_SMC911X_BASE);
  253. #else
  254. return 0;
  255. #endif
  256. }
  257. #endif /* CONFIG_CMD_NET */
  258. #if defined(CONFIG_MMC)
  259. int board_mmc_init(bd_t *bis)
  260. {
  261. return omap_mmc_init(0, 0, 0, -1, -1);
  262. }
  263. void board_mmc_power_init(void)
  264. {
  265. twl4030_power_mmc_init(0);
  266. }
  267. #endif /* CONFIG_MMC */
  268. #if defined(CONFIG_USB_ETHER) && defined(CONFIG_USB_MUSB_GADGET) && !defined(CONFIG_CMD_NET)
  269. int board_eth_init(bd_t *bis)
  270. {
  271. return usb_eth_initialize(bis);
  272. }
  273. #endif /* CONFIG_USB_ETHER */