imx6logic.c 7.6 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2017 Logic PD, Inc.
  4. *
  5. * Author: Adam Ford <aford173@gmail.com>
  6. *
  7. * Based on SabreSD by Fabio Estevam <fabio.estevam@nxp.com>
  8. * and updates by Jagan Teki <jagan@amarulasolutions.com>
  9. */
  10. #include <common.h>
  11. #include <env.h>
  12. #include <miiphy.h>
  13. #include <input.h>
  14. #include <mmc.h>
  15. #include <fsl_esdhc_imx.h>
  16. #include <serial.h>
  17. #include <asm/io.h>
  18. #include <asm/gpio.h>
  19. #include <linux/sizes.h>
  20. #include <asm/arch/clock.h>
  21. #include <asm/arch/crm_regs.h>
  22. #include <asm/arch/iomux.h>
  23. #include <asm/arch/mxc_hdmi.h>
  24. #include <asm/arch/mx6-pins.h>
  25. #include <asm/arch/sys_proto.h>
  26. #include <asm/mach-imx/boot_mode.h>
  27. #include <asm/mach-imx/iomux-v3.h>
  28. DECLARE_GLOBAL_DATA_PTR;
  29. #define UART_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  30. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  31. PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
  32. #define NAND_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \
  33. PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \
  34. PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
  35. int dram_init(void)
  36. {
  37. gd->ram_size = imx_ddr_size();
  38. return 0;
  39. }
  40. static iomux_v3_cfg_t const nand_pads[] = {
  41. MX6_PAD_NANDF_CS0__NAND_CE0_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  42. MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  43. MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NAND_PAD_CTRL),
  44. MX6_PAD_NANDF_WP_B__NAND_WP_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  45. MX6_PAD_NANDF_RB0__NAND_READY_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  46. MX6_PAD_NANDF_D0__NAND_DATA00 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  47. MX6_PAD_NANDF_D1__NAND_DATA01 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  48. MX6_PAD_NANDF_D2__NAND_DATA02 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  49. MX6_PAD_NANDF_D3__NAND_DATA03 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  50. MX6_PAD_NANDF_D4__NAND_DATA04 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  51. MX6_PAD_NANDF_D5__NAND_DATA05 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  52. MX6_PAD_NANDF_D6__NAND_DATA06 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  53. MX6_PAD_NANDF_D7__NAND_DATA07 | MUX_PAD_CTRL(NAND_PAD_CTRL),
  54. MX6_PAD_SD4_CLK__NAND_WE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  55. MX6_PAD_SD4_CMD__NAND_RE_B | MUX_PAD_CTRL(NAND_PAD_CTRL),
  56. };
  57. static void setup_nand_pins(void)
  58. {
  59. imx_iomux_v3_setup_multiple_pads(nand_pads, ARRAY_SIZE(nand_pads));
  60. }
  61. static int ar8031_phy_fixup(struct phy_device *phydev)
  62. {
  63. unsigned short val;
  64. /* To enable AR8031 output a 125MHz clk from CLK_25M */
  65. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7);
  66. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016);
  67. phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007);
  68. val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe);
  69. val &= 0xffe3;
  70. val |= 0x18;
  71. phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val);
  72. /* introduce tx clock delay */
  73. phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5);
  74. val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e);
  75. val |= 0x0100;
  76. phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val);
  77. return 0;
  78. }
  79. int board_phy_config(struct phy_device *phydev)
  80. {
  81. ar8031_phy_fixup(phydev);
  82. if (phydev->drv->config)
  83. phydev->drv->config(phydev);
  84. return 0;
  85. }
  86. /*
  87. * Do not overwrite the console
  88. * Use always serial for U-Boot console
  89. */
  90. int overwrite_console(void)
  91. {
  92. return 1;
  93. }
  94. int board_early_init_f(void)
  95. {
  96. setup_nand_pins();
  97. return 0;
  98. }
  99. int board_init(void)
  100. {
  101. /* address of boot parameters */
  102. gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
  103. return 0;
  104. }
  105. int board_late_init(void)
  106. {
  107. env_set("board_name", "imx6logic");
  108. if (is_mx6dq()) {
  109. env_set("board_rev", "MX6DQ");
  110. if (!env_get("fdt_file"))
  111. env_set("fdt_file", "imx6q-logicpd.dtb");
  112. }
  113. return 0;
  114. }
  115. #ifdef CONFIG_SPL_BUILD
  116. #include <asm/arch/mx6-ddr.h>
  117. #include <asm/arch/mx6q-ddr.h>
  118. #include <spl.h>
  119. #include <linux/libfdt.h>
  120. #ifdef CONFIG_SPL_OS_BOOT
  121. int spl_start_uboot(void)
  122. {
  123. /* break into full u-boot on 'c' */
  124. if (serial_tstc() && serial_getc() == 'c')
  125. return 1;
  126. return 0;
  127. }
  128. #endif
  129. void board_boot_order(u32 *spl_boot_list)
  130. {
  131. struct src *psrc = (struct src *)SRC_BASE_ADDR;
  132. unsigned int reg = readl(&psrc->sbmr1) >> 11;
  133. /*
  134. * Upon reading BOOT_CFG register the following map is done:
  135. * Bit 11 and 12 of BOOT_CFG register can determine the current
  136. * mmc port
  137. * 0x1 SD1-SOM
  138. * 0x2 SD2-Baseboard
  139. */
  140. reg &= 0x3; /* Only care about bottom 2 bits */
  141. switch (reg) {
  142. case 0:
  143. spl_boot_list[0] = BOOT_DEVICE_MMC1;
  144. break;
  145. case 1:
  146. spl_boot_list[0] = BOOT_DEVICE_MMC2;
  147. break;
  148. }
  149. /* If we cannot find a valid MMC/SD card, try NAND */
  150. spl_boot_list[1] = BOOT_DEVICE_NAND;
  151. /* As a last resort, use serial downloader */
  152. spl_boot_list[2] = BOOT_DEVICE_BOARD;
  153. }
  154. static void ccgr_init(void)
  155. {
  156. struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR;
  157. writel(0x00C03F3F, &ccm->CCGR0);
  158. writel(0x0030FC03, &ccm->CCGR1);
  159. writel(0x0FFFC000, &ccm->CCGR2);
  160. writel(0x3FF00000, &ccm->CCGR3);
  161. writel(0xFFFFF300, &ccm->CCGR4);
  162. writel(0x0F0000F3, &ccm->CCGR5);
  163. writel(0x00000FFF, &ccm->CCGR6);
  164. }
  165. static int mx6q_dcd_table[] = {
  166. MX6_IOM_GRP_DDR_TYPE, 0x000C0000,
  167. MX6_IOM_GRP_DDRPKE, 0x00000000,
  168. MX6_IOM_DRAM_SDCLK_0, 0x00000030,
  169. MX6_IOM_DRAM_SDCLK_1, 0x00000030,
  170. MX6_IOM_DRAM_CAS, 0x00000030,
  171. MX6_IOM_DRAM_RAS, 0x00000030,
  172. MX6_IOM_GRP_ADDDS, 0x00000030,
  173. MX6_IOM_DRAM_RESET, 0x00000030,
  174. MX6_IOM_DRAM_SDBA2, 0x00000000,
  175. MX6_IOM_DRAM_SDODT0, 0x00000030,
  176. MX6_IOM_DRAM_SDODT1, 0x00000030,
  177. MX6_IOM_GRP_CTLDS, 0x00000030,
  178. MX6_IOM_DDRMODE_CTL, 0x00020000,
  179. MX6_IOM_DRAM_SDQS0, 0x00000030,
  180. MX6_IOM_DRAM_SDQS1, 0x00000030,
  181. MX6_IOM_DRAM_SDQS2, 0x00000030,
  182. MX6_IOM_DRAM_SDQS3, 0x00000030,
  183. MX6_IOM_GRP_DDRMODE, 0x00020000,
  184. MX6_IOM_GRP_B0DS, 0x00000030,
  185. MX6_IOM_GRP_B1DS, 0x00000030,
  186. MX6_IOM_GRP_B2DS, 0x00000030,
  187. MX6_IOM_GRP_B3DS, 0x00000030,
  188. MX6_IOM_DRAM_DQM0, 0x00000030,
  189. MX6_IOM_DRAM_DQM1, 0x00000030,
  190. MX6_IOM_DRAM_DQM2, 0x00000030,
  191. MX6_IOM_DRAM_DQM3, 0x00000030,
  192. MX6_MMDC_P0_MDSCR, 0x00008000,
  193. MX6_MMDC_P0_MPZQHWCTRL, 0xA1390003,
  194. MX6_MMDC_P0_MPWLDECTRL0, 0x002D003A,
  195. MX6_MMDC_P0_MPWLDECTRL1, 0x0038002B,
  196. MX6_MMDC_P0_MPDGCTRL0, 0x03340338,
  197. MX6_MMDC_P0_MPDGCTRL1, 0x0334032C,
  198. MX6_MMDC_P0_MPRDDLCTL, 0x4036383C,
  199. MX6_MMDC_P0_MPWRDLCTL, 0x2E384038,
  200. MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333,
  201. MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333,
  202. MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333,
  203. MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333,
  204. MX6_MMDC_P0_MPMUR0, 0x00000800,
  205. MX6_MMDC_P0_MDPDC, 0x00020036,
  206. MX6_MMDC_P0_MDOTC, 0x09444040,
  207. MX6_MMDC_P0_MDCFG0, 0xB8BE7955,
  208. MX6_MMDC_P0_MDCFG1, 0xFF328F64,
  209. MX6_MMDC_P0_MDCFG2, 0x01FF00DB,
  210. MX6_MMDC_P0_MDMISC, 0x00011740,
  211. MX6_MMDC_P0_MDSCR, 0x00008000,
  212. MX6_MMDC_P0_MDRWD, 0x000026D2,
  213. MX6_MMDC_P0_MDOR, 0x00BE1023,
  214. MX6_MMDC_P0_MDASP, 0x00000047,
  215. MX6_MMDC_P0_MDCTL, 0x85190000,
  216. MX6_MMDC_P0_MDSCR, 0x00888032,
  217. MX6_MMDC_P0_MDSCR, 0x00008033,
  218. MX6_MMDC_P0_MDSCR, 0x00008031,
  219. MX6_MMDC_P0_MDSCR, 0x19408030,
  220. MX6_MMDC_P0_MDSCR, 0x04008040,
  221. MX6_MMDC_P0_MDREF, 0x00007800,
  222. MX6_MMDC_P0_MPODTCTRL, 0x00000007,
  223. MX6_MMDC_P0_MDPDC, 0x00025576,
  224. MX6_MMDC_P0_MAPSR, 0x00011006,
  225. MX6_MMDC_P0_MDSCR, 0x00000000,
  226. /* enable AXI cache for VDOA/VPU/IPU */
  227. MX6_IOMUXC_GPR4, 0xF00000CF,
  228. /* set IPU AXI-id0 Qos=0xf(bypass) AXI-id1 Qos=0x7 */
  229. MX6_IOMUXC_GPR6, 0x007F007F,
  230. MX6_IOMUXC_GPR7, 0x007F007F,
  231. };
  232. static void ddr_init(int *table, int size)
  233. {
  234. int i;
  235. for (i = 0; i < size / 2 ; i++)
  236. writel(table[2 * i + 1], table[2 * i]);
  237. }
  238. static void spl_dram_init(void)
  239. {
  240. if (is_mx6dq())
  241. ddr_init(mx6q_dcd_table, ARRAY_SIZE(mx6q_dcd_table));
  242. }
  243. void board_init_f(ulong dummy)
  244. {
  245. /* DDR initialization */
  246. spl_dram_init();
  247. /* setup AIPS and disable watchdog */
  248. arch_cpu_init();
  249. ccgr_init();
  250. gpr_init();
  251. /* iomux and setup of uart and NAND pins */
  252. board_early_init_f();
  253. /* setup GP timer */
  254. timer_init();
  255. /* Enable device tree and early DM support*/
  256. spl_early_init();
  257. /* UART clocks enabled and gd valid - init serial console */
  258. preloader_console_init();
  259. }
  260. #endif