board.c 7.2 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for IGEP COM AQUILA and SMARC AM335x based boards
  4. *
  5. * Copyright (C) 2013-2017, ISEE 2007 SL - http://www.isee.biz/
  6. */
  7. #include <common.h>
  8. #include <env.h>
  9. #include <errno.h>
  10. #include <serial.h>
  11. #include <spl.h>
  12. #include <asm/arch/cpu.h>
  13. #include <asm/arch/hardware.h>
  14. #include <asm/arch/omap.h>
  15. #include <asm/arch/ddr_defs.h>
  16. #include <asm/arch/clock.h>
  17. #include <asm/arch/gpio.h>
  18. #include <asm/arch/mmc_host_def.h>
  19. #include <asm/arch/sys_proto.h>
  20. #include <asm/io.h>
  21. #include <asm/emif.h>
  22. #include <asm/gpio.h>
  23. #include <i2c.h>
  24. #include <miiphy.h>
  25. #include <cpsw.h>
  26. #include <fdt_support.h>
  27. #include <mtd_node.h>
  28. #include <jffs2/load_kernel.h>
  29. #include "board.h"
  30. DECLARE_GLOBAL_DATA_PTR;
  31. /* GPIO0_27 and GPIO0_26 are used to read board revision from IGEP003x boards
  32. * and control IGEP0034 green and red LEDs.
  33. * U-boot configures these pins as input pullup to detect board revision:
  34. * IGEP0034-LITE = 0b00
  35. * IGEP0034 (FULL) = 0b01
  36. * IGEP0033 = 0b1X
  37. */
  38. #define GPIO_GREEN_REVISION 27
  39. #define GPIO_RED_REVISION 26
  40. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  41. /*
  42. * Routine: get_board_revision
  43. * Description: Returns the board revision
  44. */
  45. static int get_board_revision(void)
  46. {
  47. int revision;
  48. gpio_request(GPIO_GREEN_REVISION, "green_revision");
  49. gpio_direction_input(GPIO_GREEN_REVISION);
  50. revision = 2 * gpio_get_value(GPIO_GREEN_REVISION);
  51. gpio_free(GPIO_GREEN_REVISION);
  52. gpio_request(GPIO_RED_REVISION, "red_revision");
  53. gpio_direction_input(GPIO_RED_REVISION);
  54. revision = revision + gpio_get_value(GPIO_RED_REVISION);
  55. gpio_free(GPIO_RED_REVISION);
  56. return revision;
  57. }
  58. #ifdef CONFIG_SPL_BUILD
  59. /* PN H5TQ4G63AFR is equivalent to MT41K256M16HA125*/
  60. static const struct ddr_data ddr3_igep0034_data = {
  61. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  62. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  63. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  64. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  65. };
  66. static const struct ddr_data ddr3_igep0034_lite_data = {
  67. .datardsratio0 = K4B2G1646EBIH9_RD_DQS,
  68. .datawdsratio0 = K4B2G1646EBIH9_WR_DQS,
  69. .datafwsratio0 = K4B2G1646EBIH9_PHY_FIFO_WE,
  70. .datawrsratio0 = K4B2G1646EBIH9_PHY_WR_DATA,
  71. };
  72. static const struct cmd_control ddr3_igep0034_cmd_ctrl_data = {
  73. .cmd0csratio = MT41K256M16HA125E_RATIO,
  74. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  75. .cmd1csratio = MT41K256M16HA125E_RATIO,
  76. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  77. .cmd2csratio = MT41K256M16HA125E_RATIO,
  78. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  79. };
  80. static const struct cmd_control ddr3_igep0034_lite_cmd_ctrl_data = {
  81. .cmd0csratio = K4B2G1646EBIH9_RATIO,
  82. .cmd0iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  83. .cmd1csratio = K4B2G1646EBIH9_RATIO,
  84. .cmd1iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  85. .cmd2csratio = K4B2G1646EBIH9_RATIO,
  86. .cmd2iclkout = K4B2G1646EBIH9_INVERT_CLKOUT,
  87. };
  88. static struct emif_regs ddr3_igep0034_emif_reg_data = {
  89. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  90. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  91. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  92. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  93. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  94. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  95. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  96. };
  97. static struct emif_regs ddr3_igep0034_lite_emif_reg_data = {
  98. .sdram_config = K4B2G1646EBIH9_EMIF_SDCFG,
  99. .ref_ctrl = K4B2G1646EBIH9_EMIF_SDREF,
  100. .sdram_tim1 = K4B2G1646EBIH9_EMIF_TIM1,
  101. .sdram_tim2 = K4B2G1646EBIH9_EMIF_TIM2,
  102. .sdram_tim3 = K4B2G1646EBIH9_EMIF_TIM3,
  103. .zq_config = K4B2G1646EBIH9_ZQ_CFG,
  104. .emif_ddr_phy_ctlr_1 = K4B2G1646EBIH9_EMIF_READ_LATENCY,
  105. };
  106. const struct ctrl_ioregs ioregs_igep0034 = {
  107. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  108. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  109. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  110. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  111. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  112. };
  113. const struct ctrl_ioregs ioregs_igep0034_lite = {
  114. .cm0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  115. .cm1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  116. .cm2ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  117. .dt0ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  118. .dt1ioctl = K4B2G1646EBIH9_IOCTRL_VALUE,
  119. };
  120. #define OSC (V_OSCK/1000000)
  121. const struct dpll_params dpll_ddr = {
  122. 400, OSC-1, 1, -1, -1, -1, -1};
  123. const struct dpll_params *get_dpll_ddr_params(void)
  124. {
  125. return &dpll_ddr;
  126. }
  127. void set_uart_mux_conf(void)
  128. {
  129. enable_uart0_pin_mux();
  130. }
  131. void set_mux_conf_regs(void)
  132. {
  133. enable_board_pin_mux();
  134. }
  135. void sdram_init(void)
  136. {
  137. if (get_board_revision() == 1)
  138. config_ddr(400, &ioregs_igep0034, &ddr3_igep0034_data,
  139. &ddr3_igep0034_cmd_ctrl_data, &ddr3_igep0034_emif_reg_data, 0);
  140. else
  141. config_ddr(400, &ioregs_igep0034_lite, &ddr3_igep0034_lite_data,
  142. &ddr3_igep0034_lite_cmd_ctrl_data, &ddr3_igep0034_lite_emif_reg_data, 0);
  143. }
  144. #ifdef CONFIG_SPL_OS_BOOT
  145. int spl_start_uboot(void)
  146. {
  147. /* break into full u-boot on 'c' */
  148. return serial_tstc() && serial_getc() == 'c';
  149. }
  150. #endif
  151. #endif
  152. /*
  153. * Basic board specific setup. Pinmux has been handled already.
  154. */
  155. int board_init(void)
  156. {
  157. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  158. gpmc_init();
  159. return 0;
  160. }
  161. #ifdef CONFIG_BOARD_LATE_INIT
  162. int board_late_init(void)
  163. {
  164. #ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
  165. switch (get_board_revision()) {
  166. case 0:
  167. env_set("board_name", "igep0034-lite");
  168. break;
  169. case 1:
  170. env_set("board_name", "igep0034");
  171. break;
  172. default:
  173. env_set("board_name", "igep0033");
  174. break;
  175. }
  176. #endif
  177. return 0;
  178. }
  179. #endif
  180. #ifdef CONFIG_OF_BOARD_SETUP
  181. int ft_board_setup(void *blob, bd_t *bd)
  182. {
  183. #ifdef CONFIG_FDT_FIXUP_PARTITIONS
  184. static const struct node_info nodes[] = {
  185. { "ti,omap2-nand", MTD_DEV_TYPE_NAND, },
  186. };
  187. fdt_fixup_mtdparts(blob, nodes, ARRAY_SIZE(nodes));
  188. #endif
  189. return 0;
  190. }
  191. #endif
  192. #if defined(CONFIG_DRIVER_TI_CPSW)
  193. static void cpsw_control(int enabled)
  194. {
  195. /* VTP can be added here */
  196. return;
  197. }
  198. static struct cpsw_slave_data cpsw_slaves[] = {
  199. {
  200. .slave_reg_ofs = 0x208,
  201. .sliver_reg_ofs = 0xd80,
  202. .phy_addr = 0,
  203. .phy_if = PHY_INTERFACE_MODE_RMII,
  204. },
  205. };
  206. static struct cpsw_platform_data cpsw_data = {
  207. .mdio_base = CPSW_MDIO_BASE,
  208. .cpsw_base = CPSW_BASE,
  209. .mdio_div = 0xff,
  210. .channels = 8,
  211. .cpdma_reg_ofs = 0x800,
  212. .slaves = 1,
  213. .slave_data = cpsw_slaves,
  214. .ale_reg_ofs = 0xd00,
  215. .ale_entries = 1024,
  216. .host_port_reg_ofs = 0x108,
  217. .hw_stats_reg_ofs = 0x900,
  218. .bd_ram_ofs = 0x2000,
  219. .mac_control = (1 << 5),
  220. .control = cpsw_control,
  221. .host_port_num = 0,
  222. .version = CPSW_CTRL_VERSION_2,
  223. };
  224. int board_eth_init(bd_t *bis)
  225. {
  226. int rv, ret = 0;
  227. uint8_t mac_addr[6];
  228. uint32_t mac_hi, mac_lo;
  229. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  230. /* try reading mac address from efuse */
  231. mac_lo = readl(&cdev->macid0l);
  232. mac_hi = readl(&cdev->macid0h);
  233. mac_addr[0] = mac_hi & 0xFF;
  234. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  235. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  236. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  237. mac_addr[4] = mac_lo & 0xFF;
  238. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  239. if (is_valid_ethaddr(mac_addr))
  240. eth_env_set_enetaddr("ethaddr", mac_addr);
  241. }
  242. writel((GMII1_SEL_RMII | RMII1_IO_CLK_EN),
  243. &cdev->miisel);
  244. if (get_board_revision() == 1)
  245. cpsw_slaves[0].phy_addr = 1;
  246. rv = cpsw_register(&cpsw_data);
  247. if (rv < 0)
  248. printf("Error %d registering CPSW switch\n", rv);
  249. else
  250. ret += rv;
  251. return ret;
  252. }
  253. #endif