board.c 7.0 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Board functions for Gumstix Pepper and AM335x-based boards
  4. *
  5. * Copyright (C) 2014, Gumstix, Incorporated - http://www.gumstix.com/
  6. * Based on board/ti/am335x/board.c from Texas Instruments, Inc.
  7. */
  8. #include <common.h>
  9. #include <env.h>
  10. #include <errno.h>
  11. #include <serial.h>
  12. #include <spl.h>
  13. #include <asm/arch/cpu.h>
  14. #include <asm/arch/hardware.h>
  15. #include <asm/arch/omap.h>
  16. #include <asm/arch/ddr_defs.h>
  17. #include <asm/arch/clock.h>
  18. #include <asm/arch/gpio.h>
  19. #include <asm/arch/mmc_host_def.h>
  20. #include <asm/arch/sys_proto.h>
  21. #include <asm/arch/mem.h>
  22. #include <asm/io.h>
  23. #include <asm/emif.h>
  24. #include <asm/gpio.h>
  25. #include <i2c.h>
  26. #include <miiphy.h>
  27. #include <cpsw.h>
  28. #include <power/tps65217.h>
  29. #include <watchdog.h>
  30. #include "board.h"
  31. DECLARE_GLOBAL_DATA_PTR;
  32. #ifdef CONFIG_SPL_BUILD
  33. #define OSC (V_OSCK/1000000)
  34. static const struct ddr_data ddr3_data = {
  35. .datardsratio0 = MT41K256M16HA125E_RD_DQS,
  36. .datawdsratio0 = MT41K256M16HA125E_WR_DQS,
  37. .datafwsratio0 = MT41K256M16HA125E_PHY_FIFO_WE,
  38. .datawrsratio0 = MT41K256M16HA125E_PHY_WR_DATA,
  39. };
  40. static const struct cmd_control ddr3_cmd_ctrl_data = {
  41. .cmd0csratio = MT41K256M16HA125E_RATIO,
  42. .cmd0iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  43. .cmd1csratio = MT41K256M16HA125E_RATIO,
  44. .cmd1iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  45. .cmd2csratio = MT41K256M16HA125E_RATIO,
  46. .cmd2iclkout = MT41K256M16HA125E_INVERT_CLKOUT,
  47. };
  48. static struct emif_regs ddr3_emif_reg_data = {
  49. .sdram_config = MT41K256M16HA125E_EMIF_SDCFG,
  50. .ref_ctrl = MT41K256M16HA125E_EMIF_SDREF,
  51. .sdram_tim1 = MT41K256M16HA125E_EMIF_TIM1,
  52. .sdram_tim2 = MT41K256M16HA125E_EMIF_TIM2,
  53. .sdram_tim3 = MT41K256M16HA125E_EMIF_TIM3,
  54. .zq_config = MT41K256M16HA125E_ZQ_CFG,
  55. .emif_ddr_phy_ctlr_1 = MT41K256M16HA125E_EMIF_READ_LATENCY,
  56. };
  57. const struct dpll_params dpll_ddr3 = {400, OSC-1, 1, -1, -1, -1, -1};
  58. const struct ctrl_ioregs ioregs_ddr3 = {
  59. .cm0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  60. .cm1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  61. .cm2ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  62. .dt0ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  63. .dt1ioctl = MT41K256M16HA125E_IOCTRL_VALUE,
  64. };
  65. static const struct ddr_data ddr2_data = {
  66. .datardsratio0 = MT47H128M16RT25E_RD_DQS,
  67. .datafwsratio0 = MT47H128M16RT25E_PHY_FIFO_WE,
  68. .datawrsratio0 = MT47H128M16RT25E_PHY_WR_DATA,
  69. };
  70. static const struct cmd_control ddr2_cmd_ctrl_data = {
  71. .cmd0csratio = MT47H128M16RT25E_RATIO,
  72. .cmd1csratio = MT47H128M16RT25E_RATIO,
  73. .cmd2csratio = MT47H128M16RT25E_RATIO,
  74. };
  75. static const struct emif_regs ddr2_emif_reg_data = {
  76. .sdram_config = MT47H128M16RT25E_EMIF_SDCFG,
  77. .ref_ctrl = MT47H128M16RT25E_EMIF_SDREF,
  78. .sdram_tim1 = MT47H128M16RT25E_EMIF_TIM1,
  79. .sdram_tim2 = MT47H128M16RT25E_EMIF_TIM2,
  80. .sdram_tim3 = MT47H128M16RT25E_EMIF_TIM3,
  81. .emif_ddr_phy_ctlr_1 = MT47H128M16RT25E_EMIF_READ_LATENCY,
  82. };
  83. const struct dpll_params dpll_ddr2 = {266, OSC-1, 1, -1, -1, -1, -1};
  84. const struct ctrl_ioregs ioregs_ddr2 = {
  85. .cm0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  86. .cm1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  87. .cm2ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  88. .dt0ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  89. .dt1ioctl = MT47H128M16RT25E_IOCTRL_VALUE,
  90. };
  91. static int read_eeprom(struct pepper_board_id *header)
  92. {
  93. if (i2c_probe(CONFIG_SYS_I2C_EEPROM_ADDR)) {
  94. return -ENODEV;
  95. }
  96. if (i2c_read(CONFIG_SYS_I2C_EEPROM_ADDR, 0, 1, (uchar *)header,
  97. sizeof(struct pepper_board_id))) {
  98. return -EIO;
  99. }
  100. return 0;
  101. }
  102. const struct dpll_params *get_dpll_ddr_params(void)
  103. {
  104. struct pepper_board_id header;
  105. enable_i2c0_pin_mux();
  106. i2c_set_bus_num(0);
  107. if (read_eeprom(&header) < 0)
  108. return &dpll_ddr3;
  109. switch (header.device_vendor) {
  110. case GUMSTIX_PEPPER:
  111. return &dpll_ddr2;
  112. case GUMSTIX_PEPPER_DVI:
  113. return &dpll_ddr3;
  114. default:
  115. return &dpll_ddr3;
  116. }
  117. }
  118. void sdram_init(void)
  119. {
  120. const struct dpll_params *dpll = get_dpll_ddr_params();
  121. /*
  122. * Here we are assuming PLL clock reveals the type of RAM.
  123. * DDR2 = 266
  124. * DDR3 = 400
  125. * Note that DDR3 is the default.
  126. */
  127. if (dpll->m == 266) {
  128. config_ddr(dpll->m, &ioregs_ddr2, &ddr2_data,
  129. &ddr2_cmd_ctrl_data, &ddr2_emif_reg_data, 0);
  130. }
  131. else if (dpll->m == 400) {
  132. config_ddr(dpll->m, &ioregs_ddr3, &ddr3_data,
  133. &ddr3_cmd_ctrl_data, &ddr3_emif_reg_data, 0);
  134. }
  135. }
  136. #ifdef CONFIG_SPL_OS_BOOT
  137. int spl_start_uboot(void)
  138. {
  139. /* break into full u-boot on 'c' */
  140. return serial_tstc() && serial_getc() == 'c';
  141. }
  142. #endif
  143. void set_uart_mux_conf(void)
  144. {
  145. enable_uart0_pin_mux();
  146. }
  147. void set_mux_conf_regs(void)
  148. {
  149. enable_board_pin_mux();
  150. }
  151. #endif
  152. int board_init(void)
  153. {
  154. #if defined(CONFIG_HW_WATCHDOG)
  155. hw_watchdog_init();
  156. #endif
  157. gd->bd->bi_boot_params = CONFIG_SYS_SDRAM_BASE + 0x100;
  158. gpmc_init();
  159. return 0;
  160. }
  161. #if (defined(CONFIG_DRIVER_TI_CPSW) && !defined(CONFIG_SPL_BUILD)) || \
  162. (defined(CONFIG_SPL_ETH_SUPPORT) && defined(CONFIG_SPL_BUILD))
  163. static struct ctrl_dev *cdev = (struct ctrl_dev *)CTRL_DEVICE_BASE;
  164. static void cpsw_control(int enabled)
  165. {
  166. /* VTP can be added here */
  167. return;
  168. }
  169. static struct cpsw_slave_data cpsw_slaves[] = {
  170. {
  171. .slave_reg_ofs = 0x208,
  172. .sliver_reg_ofs = 0xd80,
  173. .phy_addr = 0,
  174. .phy_if = PHY_INTERFACE_MODE_RGMII,
  175. },
  176. };
  177. static struct cpsw_platform_data cpsw_data = {
  178. .mdio_base = CPSW_MDIO_BASE,
  179. .cpsw_base = CPSW_BASE,
  180. .mdio_div = 0xff,
  181. .channels = 8,
  182. .cpdma_reg_ofs = 0x800,
  183. .slaves = 1,
  184. .slave_data = cpsw_slaves,
  185. .ale_reg_ofs = 0xd00,
  186. .ale_entries = 1024,
  187. .host_port_reg_ofs = 0x108,
  188. .hw_stats_reg_ofs = 0x900,
  189. .bd_ram_ofs = 0x2000,
  190. .mac_control = (1 << 5),
  191. .control = cpsw_control,
  192. .host_port_num = 0,
  193. .version = CPSW_CTRL_VERSION_2,
  194. };
  195. int board_eth_init(bd_t *bis)
  196. {
  197. int rv, n = 0;
  198. uint8_t mac_addr[6];
  199. uint32_t mac_hi, mac_lo;
  200. const char *devname;
  201. if (!eth_env_get_enetaddr("ethaddr", mac_addr)) {
  202. /* try reading mac address from efuse */
  203. mac_lo = readl(&cdev->macid0l);
  204. mac_hi = readl(&cdev->macid0h);
  205. mac_addr[0] = mac_hi & 0xFF;
  206. mac_addr[1] = (mac_hi & 0xFF00) >> 8;
  207. mac_addr[2] = (mac_hi & 0xFF0000) >> 16;
  208. mac_addr[3] = (mac_hi & 0xFF000000) >> 24;
  209. mac_addr[4] = mac_lo & 0xFF;
  210. mac_addr[5] = (mac_lo & 0xFF00) >> 8;
  211. if (is_valid_ethaddr(mac_addr))
  212. eth_env_set_enetaddr("ethaddr", mac_addr);
  213. }
  214. writel((RGMII_MODE_ENABLE | RGMII_INT_DELAY), &cdev->miisel);
  215. rv = cpsw_register(&cpsw_data);
  216. if (rv < 0)
  217. printf("Error %d registering CPSW switch\n", rv);
  218. else
  219. n += rv;
  220. /*
  221. *
  222. * CPSW RGMII Internal Delay Mode is not supported in all PVT
  223. * operating points. So we must set the TX clock delay feature
  224. * in the KSZ9021 PHY. Since we only support a single ethernet
  225. * device in U-Boot, we only do this for the current instance.
  226. */
  227. devname = miiphy_get_current_dev();
  228. /* max rx/tx clock delay, min rx/tx control delay */
  229. miiphy_write(devname, 0x0, 0x0b, 0x8104);
  230. miiphy_write(devname, 0x0, 0xc, 0xa0a0);
  231. /* min rx data delay */
  232. miiphy_write(devname, 0x0, 0x0b, 0x8105);
  233. miiphy_write(devname, 0x0, 0x0c, 0x0000);
  234. /* min tx data delay */
  235. miiphy_write(devname, 0x0, 0x0b, 0x8106);
  236. miiphy_write(devname, 0x0, 0x0c, 0x0000);
  237. return n;
  238. }
  239. #endif