mcf5373l.c 4.4 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2000-2003
  4. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  5. * modified by Wolfgang Wegner <w.wegner@astro-kom.de> for ASTRO 5373l
  6. */
  7. #include <common.h>
  8. #include <serial.h>
  9. #include <watchdog.h>
  10. #include <command.h>
  11. #include <asm/m5329.h>
  12. #include <asm/immap_5329.h>
  13. #include <asm/io.h>
  14. /* needed for astro bus: */
  15. #include <asm/uart.h>
  16. #include "astro.h"
  17. DECLARE_GLOBAL_DATA_PTR;
  18. extern void uart_port_conf(void);
  19. int checkboard(void)
  20. {
  21. puts("Board: ");
  22. puts("ASTRO MCF5373L (Urmel) Board\n");
  23. return 0;
  24. }
  25. int dram_init(void)
  26. {
  27. #if !defined(CONFIG_MONITOR_IS_IN_RAM)
  28. sdram_t *sdp = (sdram_t *)(MMAP_SDRAM);
  29. /*
  30. * GPIO configuration for bus should be set correctly from reset,
  31. * so we do not care! First, set up address space: at this point,
  32. * we should be running from internal SRAM;
  33. * so use CONFIG_SYS_SDRAM_BASE as the base address for SDRAM,
  34. * and do not care where it is
  35. */
  36. __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000018,
  37. &sdp->cs0);
  38. __raw_writel((CONFIG_SYS_SDRAM_BASE & 0xFFF00000) | 0x00000000,
  39. &sdp->cs1);
  40. /*
  41. * I am not sure from the data sheet, but it seems burst length
  42. * has to be 8 for the 16 bit data bus we use;
  43. * so these values are for BL = 8
  44. */
  45. __raw_writel(0x33211530, &sdp->cfg1);
  46. __raw_writel(0x56570000, &sdp->cfg2);
  47. /* send PrechargeALL, REF and IREF remain cleared! */
  48. __raw_writel(0xE1462C02, &sdp->ctrl);
  49. udelay(1);
  50. /* refresh SDRAM twice */
  51. __raw_writel(0xE1462C04, &sdp->ctrl);
  52. udelay(1);
  53. __raw_writel(0xE1462C04, &sdp->ctrl);
  54. /* init MR */
  55. __raw_writel(0x008D0000, &sdp->mode);
  56. /* initialize EMR */
  57. __raw_writel(0x80010000, &sdp->mode);
  58. /* wait until DLL is locked */
  59. udelay(1);
  60. /*
  61. * enable automatic refresh, lock mode register,
  62. * clear iref and ipall
  63. */
  64. __raw_writel(0x71462C00, &sdp->ctrl);
  65. /* Dummy write to start SDRAM */
  66. writel(0, CONFIG_SYS_SDRAM_BASE);
  67. #endif
  68. /*
  69. * for get_ram_size() to work, both CS areas have to be
  70. * configured, i.e. CS1 has to be explicitely disabled, else
  71. * probing for memory will cause the SDRAM bus to hang!
  72. * (Do not rely on the SDCS register(s) being set to 0x00000000
  73. * during reset as stated in the data sheet.)
  74. */
  75. gd->ram_size = get_ram_size((long *)CONFIG_SYS_SDRAM_BASE,
  76. 0x80000000 - CONFIG_SYS_SDRAM_BASE);
  77. return 0;
  78. }
  79. #define UART_BASE MMAP_UART0
  80. int rs_serial_init(int port, int baud)
  81. {
  82. uart_t *uart;
  83. u32 counter;
  84. switch (port) {
  85. case 0:
  86. uart = (uart_t *)(MMAP_UART0);
  87. break;
  88. case 1:
  89. uart = (uart_t *)(MMAP_UART1);
  90. break;
  91. case 2:
  92. uart = (uart_t *)(MMAP_UART2);
  93. break;
  94. default:
  95. uart = (uart_t *)(MMAP_UART0);
  96. }
  97. uart_port_conf();
  98. /* write to SICR: SIM2 = uart mode,dcd does not affect rx */
  99. writeb(UART_UCR_RESET_RX, &uart->ucr);
  100. writeb(UART_UCR_RESET_TX, &uart->ucr);
  101. writeb(UART_UCR_RESET_ERROR, &uart->ucr);
  102. writeb(UART_UCR_RESET_MR, &uart->ucr);
  103. __asm__ ("nop");
  104. writeb(0, &uart->uimr);
  105. /* write to CSR: RX/TX baud rate from timers */
  106. writeb(UART_UCSR_RCS_SYS_CLK | UART_UCSR_TCS_SYS_CLK, &uart->ucsr);
  107. writeb(UART_UMR_BC_8 | UART_UMR_PM_NONE, &uart->umr);
  108. writeb(UART_UMR_SB_STOP_BITS_1, &uart->umr);
  109. /* Setting up BaudRate */
  110. counter = (u32) (gd->bus_clk / (baud));
  111. counter >>= 5;
  112. /* write to CTUR: divide counter upper byte */
  113. writeb((u8) ((counter & 0xff00) >> 8), &uart->ubg1);
  114. /* write to CTLR: divide counter lower byte */
  115. writeb((u8) (counter & 0x00ff), &uart->ubg2);
  116. writeb(UART_UCR_RX_ENABLED | UART_UCR_TX_ENABLED, &uart->ucr);
  117. return 0;
  118. }
  119. void astro_put_char(char ch)
  120. {
  121. uart_t *uart;
  122. unsigned long timer;
  123. uart = (uart_t *)(MMAP_UART0);
  124. /*
  125. * Wait for last character to go. Timeout of 6ms should
  126. * be enough for our lowest baud rate of 2400.
  127. */
  128. timer = get_timer(0);
  129. while (get_timer(timer) < 6) {
  130. if (readb(&uart->usr) & UART_USR_TXRDY)
  131. break;
  132. }
  133. writeb(ch, &uart->utb);
  134. return;
  135. }
  136. int astro_is_char(void)
  137. {
  138. uart_t *uart;
  139. uart = (uart_t *)(MMAP_UART0);
  140. return readb(&uart->usr) & UART_USR_RXRDY;
  141. }
  142. int astro_get_char(void)
  143. {
  144. uart_t *uart;
  145. uart = (uart_t *)(MMAP_UART0);
  146. while (!(readb(&uart->usr) & UART_USR_RXRDY)) ;
  147. return readb(&uart->urb);
  148. }
  149. int misc_init_r(void)
  150. {
  151. int retval = 0;
  152. puts("Configure Xilinx FPGA...");
  153. retval = astro5373l_xilinx_load();
  154. if (!retval) {
  155. puts("failed!\n");
  156. return retval;
  157. }
  158. puts("done\n");
  159. puts("Configure Altera FPGA...");
  160. retval = astro5373l_altera_load();
  161. if (!retval) {
  162. puts("failed!\n");
  163. return retval;
  164. }
  165. puts("done\n");
  166. return retval;
  167. }