ns3.c 5.1 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234
  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright 2020 Broadcom.
  4. *
  5. */
  6. #include <common.h>
  7. #include <fdt_support.h>
  8. #include <asm/io.h>
  9. #include <asm/gic-v3.h>
  10. #include <asm/system.h>
  11. #include <asm/armv8/mmu.h>
  12. #include <asm/arch-bcmns3/bl33_info.h>
  13. #include <dt-bindings/memory/bcm-ns3-mc.h>
  14. #include <broadcom/chimp.h>
  15. /* Default reset-level = 3 and strap-val = 0 */
  16. #define L3_RESET 30
  17. #define BANK_OFFSET(bank) ((u64)BCM_NS3_DDR_INFO_BASE + 8 + ((bank) * 16))
  18. /*
  19. * ns3_dram_bank - DDR bank details
  20. *
  21. * @start: DDR bank start address
  22. * @len: DDR bank length
  23. */
  24. struct ns3_dram_bank {
  25. u64 start[BCM_NS3_MAX_NR_BANKS];
  26. u64 len[BCM_NS3_MAX_NR_BANKS];
  27. };
  28. /*
  29. * ns3_dram_hdr - DDR header info
  30. *
  31. * @sig: DDR info signature
  32. * @bank: DDR bank details
  33. */
  34. struct ns3_dram_hdr {
  35. u32 sig;
  36. struct ns3_dram_bank bank;
  37. };
  38. static struct mm_region ns3_mem_map[] = {
  39. {
  40. .virt = 0x0UL,
  41. .phys = 0x0UL,
  42. .size = 0x80000000UL,
  43. .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  44. PTE_BLOCK_NON_SHARE |
  45. PTE_BLOCK_PXN | PTE_BLOCK_UXN
  46. }, {
  47. .virt = BCM_NS3_MEM_START,
  48. .phys = BCM_NS3_MEM_START,
  49. .size = BCM_NS3_MEM_LEN,
  50. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  51. PTE_BLOCK_INNER_SHARE
  52. }, {
  53. .virt = BCM_NS3_BANK_1_MEM_START,
  54. .phys = BCM_NS3_BANK_1_MEM_START,
  55. .size = BCM_NS3_BANK_1_MEM_LEN,
  56. .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  57. PTE_BLOCK_INNER_SHARE
  58. }, {
  59. /* List terminator */
  60. 0,
  61. }
  62. };
  63. struct mm_region *mem_map = ns3_mem_map;
  64. DECLARE_GLOBAL_DATA_PTR;
  65. /*
  66. * Force the bl33_info to the data-section, as .bss will not be valid
  67. * when save_boot_params is invoked.
  68. */
  69. struct bl33_info *bl33_info __section(".data");
  70. /*
  71. * Run modulo 256 checksum calculation and return the calculated checksum
  72. */
  73. static u8 checksum_calc(u8 *p, unsigned int len)
  74. {
  75. unsigned int i;
  76. u8 chksum = 0;
  77. for (i = 0; i < len; i++)
  78. chksum += p[i];
  79. return chksum;
  80. }
  81. /*
  82. * This function parses the memory layout information from a reserved area in
  83. * DDR, and then fix up the FDT before passing it to Linux.
  84. *
  85. * In the case of error, do nothing and the default memory layout in DT will
  86. * be used
  87. */
  88. static int mem_info_parse_fixup(void *fdt)
  89. {
  90. struct ns3_dram_hdr hdr;
  91. u32 *p32, i, nr_banks;
  92. u64 *p64;
  93. /* validate signature */
  94. p32 = (u32 *)BCM_NS3_DDR_INFO_BASE;
  95. hdr.sig = *p32;
  96. if (hdr.sig != BCM_NS3_DDR_INFO_SIG) {
  97. printf("DDR info signature 0x%x invalid\n", hdr.sig);
  98. return -EINVAL;
  99. }
  100. /* run checksum test to validate data */
  101. if (checksum_calc((u8 *)p32, BCM_NS3_DDR_INFO_LEN) != 0) {
  102. printf("Checksum on DDR info failed\n");
  103. return -EINVAL;
  104. }
  105. /* parse information for each bank */
  106. nr_banks = 0;
  107. for (i = 0; i < BCM_NS3_MAX_NR_BANKS; i++) {
  108. /* skip banks with a length of zero */
  109. p64 = (u64 *)BANK_OFFSET(i);
  110. if (*(p64 + 1) == 0)
  111. continue;
  112. hdr.bank.start[i] = *p64;
  113. hdr.bank.len[i] = *(p64 + 1);
  114. printf("mem[%u] 0x%llx - 0x%llx\n", i, hdr.bank.start[i],
  115. hdr.bank.start[i] + hdr.bank.len[i] - 1);
  116. nr_banks++;
  117. }
  118. if (!nr_banks) {
  119. printf("No DDR banks detected\n");
  120. return -ENOMEM;
  121. }
  122. return fdt_fixup_memory_banks(fdt, hdr.bank.start, hdr.bank.len,
  123. nr_banks);
  124. }
  125. int board_init(void)
  126. {
  127. /* Setup memory using "memory" node from DTB */
  128. if (fdtdec_setup_mem_size_base() != 0)
  129. return -EINVAL;
  130. fdtdec_setup_memory_banksize();
  131. if (bl33_info->version != BL33_INFO_VERSION)
  132. printf("*** warning: ATF BL31 and U-Boot not in sync! ***\n");
  133. return 0;
  134. }
  135. int board_late_init(void)
  136. {
  137. return 0;
  138. }
  139. int dram_init(void)
  140. {
  141. /*
  142. * Mark ram base as the last 16MB of 2GB DDR, which is 0xFF00_0000.
  143. * So that relocation happens with in the last 16MB memory.
  144. */
  145. gd->ram_base = (phys_size_t)(BCM_NS3_MEM_END - SZ_16M);
  146. gd->ram_size = (unsigned long)SZ_16M;
  147. return 0;
  148. }
  149. int dram_init_banksize(void)
  150. {
  151. gd->bd->bi_dram[0].start = (BCM_NS3_MEM_END - SZ_16M);
  152. gd->bd->bi_dram[0].size = SZ_16M;
  153. return 0;
  154. }
  155. /* Limit RAM used by U-Boot to the DDR first bank End region */
  156. ulong board_get_usable_ram_top(ulong total_size)
  157. {
  158. return BCM_NS3_MEM_END;
  159. }
  160. void reset_cpu(ulong level)
  161. {
  162. u32 reset_level, strap_val;
  163. /* Default reset type is L3 reset */
  164. if (!level) {
  165. /*
  166. * Encoding: U-Boot reset command expects decimal argument,
  167. * Boot strap val: Bits[3:0]
  168. * reset level: Bits[7:4]
  169. */
  170. strap_val = L3_RESET % 10;
  171. level = L3_RESET / 10;
  172. reset_level = level % 10;
  173. psci_system_reset2(reset_level, strap_val);
  174. } else {
  175. /* U-Boot cmd "reset" with any arg will trigger L1 reset */
  176. psci_system_reset();
  177. }
  178. }
  179. #ifdef CONFIG_OF_BOARD_SETUP
  180. int ft_board_setup(void *fdt, struct bd_info *bd)
  181. {
  182. u32 chimp_hs = CHIMP_HANDSHAKE_WAIT_TIMEOUT;
  183. gic_lpi_tables_init();
  184. /*
  185. * Check for chimp handshake status.
  186. * Zero timeout value will actually fall to default timeout.
  187. *
  188. * System boot is independent of chimp handshake.
  189. * chimp handshake failure is not a catastrophic error.
  190. * Hence continue booting if chimp handshake fails.
  191. */
  192. chimp_handshake_status_optee(0, &chimp_hs);
  193. if (chimp_hs == CHIMP_HANDSHAKE_SUCCESS)
  194. printf("ChiMP handshake successful\n");
  195. else
  196. printf("ERROR: ChiMP handshake status 0x%x\n", chimp_hs);
  197. return mem_info_parse_fixup(fdt);
  198. }
  199. #endif /* CONFIG_OF_BOARD_SETUP */