kmp204x.c 7.1 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2013 Keymile AG
  4. * Valentin Longchamp <valentin.longchamp@keymile.com>
  5. *
  6. * Copyright 2011,2012 Freescale Semiconductor, Inc.
  7. */
  8. #include <common.h>
  9. #include <command.h>
  10. #include <env.h>
  11. #include <init.h>
  12. #include <netdev.h>
  13. #include <linux/compiler.h>
  14. #include <asm/mmu.h>
  15. #include <asm/processor.h>
  16. #include <asm/cache.h>
  17. #include <asm/immap_85xx.h>
  18. #include <asm/fsl_law.h>
  19. #include <asm/fsl_serdes.h>
  20. #include <asm/fsl_portals.h>
  21. #include <asm/fsl_liodn.h>
  22. #include <fm_eth.h>
  23. #include "../common/common.h"
  24. #include "kmp204x.h"
  25. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  26. int checkboard(void)
  27. {
  28. printf("Board: Keymile %s\n", CONFIG_SYS_CONFIG_NAME);
  29. return 0;
  30. }
  31. /* I2C deblocking uses the algorithm defined in board/keymile/common/common.c
  32. * 2 dedicated QRIO GPIOs externally pull the SCL and SDA lines
  33. * For I2C only the low state is activly driven and high state is pulled-up
  34. * by a resistor. Therefore the deblock GPIOs are used
  35. * -> as an active output to drive a low state
  36. * -> as an open-drain input to have a pulled-up high state
  37. */
  38. /* QRIO GPIOs used for deblocking */
  39. #define DEBLOCK_PORT1 GPIO_A
  40. #define DEBLOCK_SCL1 20
  41. #define DEBLOCK_SDA1 21
  42. /* By default deblock GPIOs are floating */
  43. static void i2c_deblock_gpio_cfg(void)
  44. {
  45. /* set I2C bus 1 deblocking GPIOs input, but 0 value for open drain */
  46. qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SCL1);
  47. qrio_gpio_direction_input(DEBLOCK_PORT1, DEBLOCK_SDA1);
  48. qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, 0);
  49. qrio_set_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, 0);
  50. }
  51. void set_sda(int state)
  52. {
  53. qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1, state);
  54. }
  55. void set_scl(int state)
  56. {
  57. qrio_set_opendrain_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1, state);
  58. }
  59. int get_sda(void)
  60. {
  61. return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SDA1);
  62. }
  63. int get_scl(void)
  64. {
  65. return qrio_get_gpio(DEBLOCK_PORT1, DEBLOCK_SCL1);
  66. }
  67. #define ZL30158_RST 8
  68. #define BFTIC4_RST 0
  69. #define RSTRQSR1_WDT_RR 0x00200000
  70. #define RSTRQSR1_SW_RR 0x00100000
  71. int board_early_init_f(void)
  72. {
  73. ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR);
  74. bool cpuwd_flag = false;
  75. /* configure mode for uP reset request */
  76. qrio_uprstreq(UPREQ_CORE_RST);
  77. /* board only uses the DDR_MCK0, so disable the DDR_MCK1/2/3 */
  78. setbits_be32(&gur->ddrclkdr, 0x001f000f);
  79. /* set reset reason according CPU register */
  80. if ((gur->rstrqsr1 & (RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR)) ==
  81. RSTRQSR1_WDT_RR)
  82. cpuwd_flag = true;
  83. qrio_cpuwd_flag(cpuwd_flag);
  84. /* clear CPU bits by writing 1 */
  85. setbits_be32(&gur->rstrqsr1, RSTRQSR1_WDT_RR | RSTRQSR1_SW_RR);
  86. /* set the BFTIC's prstcfg to reset at power-up and unit reset only */
  87. qrio_prstcfg(BFTIC4_RST, PRSTCFG_POWUP_UNIT_RST);
  88. /* and enable WD on it */
  89. qrio_wdmask(BFTIC4_RST, true);
  90. /* set the ZL30138's prstcfg to reset at power-up only */
  91. qrio_prstcfg(ZL30158_RST, PRSTCFG_POWUP_RST);
  92. /* and take it out of reset as soon as possible (needed for Hooper) */
  93. qrio_prst(ZL30158_RST, false, false);
  94. return 0;
  95. }
  96. int board_early_init_r(void)
  97. {
  98. int ret = 0;
  99. /* Flush d-cache and invalidate i-cache of any FLASH data */
  100. flush_dcache();
  101. invalidate_icache();
  102. set_liodns();
  103. setup_qbman_portals();
  104. ret = trigger_fpga_config();
  105. if (ret)
  106. printf("error triggering PCIe FPGA config\n");
  107. /* enable the Unit LED (red) & Boot LED (on) */
  108. qrio_set_leds();
  109. /* enable Application Buffer */
  110. qrio_enable_app_buffer();
  111. return ret;
  112. }
  113. unsigned long get_board_sys_clk(unsigned long dummy)
  114. {
  115. return 66666666;
  116. }
  117. #define ETH_FRONT_PHY_RST 15
  118. #define QSFP2_RST 11
  119. #define QSFP1_RST 10
  120. #define ZL30343_RST 9
  121. int misc_init_f(void)
  122. {
  123. /* configure QRIO pis for i2c deblocking */
  124. i2c_deblock_gpio_cfg();
  125. /* configure the front phy's prstcfg and take it out of reset */
  126. qrio_prstcfg(ETH_FRONT_PHY_RST, PRSTCFG_POWUP_UNIT_CORE_RST);
  127. qrio_prst(ETH_FRONT_PHY_RST, false, false);
  128. /* set the ZL30343 prstcfg to reset at power-up only */
  129. qrio_prstcfg(ZL30343_RST, PRSTCFG_POWUP_RST);
  130. /* and enable the WD on it */
  131. qrio_wdmask(ZL30343_RST, true);
  132. /* set the QSFPs' prstcfg to reset at power-up and unit rst only */
  133. qrio_prstcfg(QSFP1_RST, PRSTCFG_POWUP_UNIT_RST);
  134. qrio_prstcfg(QSFP2_RST, PRSTCFG_POWUP_UNIT_RST);
  135. /* and enable the WD on them */
  136. qrio_wdmask(QSFP1_RST, true);
  137. qrio_wdmask(QSFP2_RST, true);
  138. return 0;
  139. }
  140. #define NUM_SRDS_BANKS 2
  141. int misc_init_r(void)
  142. {
  143. serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
  144. u32 expected[NUM_SRDS_BANKS] = {SRDS_PLLCR0_RFCK_SEL_100,
  145. SRDS_PLLCR0_RFCK_SEL_125};
  146. unsigned int i;
  147. /* check SERDES reference clocks */
  148. for (i = 0; i < NUM_SRDS_BANKS; i++) {
  149. u32 actual = in_be32(&regs->bank[i].pllcr0);
  150. actual &= SRDS_PLLCR0_RFCK_SEL_MASK;
  151. if (actual != expected[i]) {
  152. printf("Warning: SERDES bank %u expects reference \
  153. clock %sMHz, but actual is %sMHz\n", i + 1,
  154. serdes_clock_to_string(expected[i]),
  155. serdes_clock_to_string(actual));
  156. }
  157. }
  158. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  159. return 0;
  160. }
  161. #if defined(CONFIG_HUSH_INIT_VAR)
  162. int hush_init_var(void)
  163. {
  164. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  165. return 0;
  166. }
  167. #endif
  168. #if defined(CONFIG_LAST_STAGE_INIT)
  169. int last_stage_init(void)
  170. {
  171. #if defined(CONFIG_KMCOGE4)
  172. /* on KMCOGE4, the BFTIC4 is on the LBAPP2 */
  173. struct bfticu_iomap *bftic4 =
  174. (struct bfticu_iomap *)CONFIG_SYS_LBAPP2_BASE;
  175. u8 dip_switch = in_8((u8 *)&(bftic4->mswitch)) & BFTICU_DIPSWITCH_MASK;
  176. if (dip_switch != 0) {
  177. /* start bootloader */
  178. puts("DIP: Enabled\n");
  179. env_set("actual_bank", "0");
  180. }
  181. #endif
  182. set_km_env();
  183. return 0;
  184. }
  185. #endif
  186. #ifdef CONFIG_SYS_DPAA_FMAN
  187. void fdt_fixup_fman_mac_addresses(void *blob)
  188. {
  189. int node, i, ret;
  190. char *tmp, *end;
  191. unsigned char mac_addr[6];
  192. /* get the mac addr from env */
  193. tmp = env_get("ethaddr");
  194. if (!tmp) {
  195. printf("ethaddr env variable not defined\n");
  196. return;
  197. }
  198. for (i = 0; i < 6; i++) {
  199. mac_addr[i] = tmp ? simple_strtoul(tmp, &end, 16) : 0;
  200. if (tmp)
  201. tmp = (*end) ? end+1 : end;
  202. }
  203. /* find the correct fdt ethernet path and correct it */
  204. node = fdt_path_offset(blob, "/soc/fman/ethernet@e8000");
  205. if (node < 0) {
  206. printf("no /soc/fman/ethernet path offset\n");
  207. return;
  208. }
  209. ret = fdt_setprop(blob, node, "local-mac-address", &mac_addr, 6);
  210. if (ret) {
  211. printf("error setting local-mac-address property\n");
  212. return;
  213. }
  214. }
  215. #endif
  216. int ft_board_setup(void *blob, bd_t *bd)
  217. {
  218. phys_addr_t base;
  219. phys_size_t size;
  220. ft_cpu_setup(blob, bd);
  221. base = env_get_bootm_low();
  222. size = env_get_bootm_size();
  223. fdt_fixup_memory(blob, (u64)base, (u64)size);
  224. #if defined(CONFIG_HAS_FSL_DR_USB) || defined(CONFIG_HAS_FSL_MPH_USB)
  225. fsl_fdt_fixup_dr_usb(blob, bd);
  226. #endif
  227. #ifdef CONFIG_PCI
  228. pci_of_setup(blob, bd);
  229. #endif
  230. fdt_fixup_liodn(blob);
  231. #ifdef CONFIG_SYS_DPAA_FMAN
  232. fdt_fixup_fman_ethernet(blob);
  233. fdt_fixup_fman_mac_addresses(blob);
  234. #endif
  235. return 0;
  236. }
  237. #if defined(CONFIG_POST)
  238. /* DIC26_SELFTEST GPIO used to start factory test sw */
  239. #define SELFTEST_PORT GPIO_A
  240. #define SELFTEST_PIN 31
  241. int post_hotkeys_pressed(void)
  242. {
  243. qrio_gpio_direction_input(SELFTEST_PORT, SELFTEST_PIN);
  244. return qrio_get_gpio(SELFTEST_PORT, SELFTEST_PIN);
  245. }
  246. #endif