km83xx.c 8.9 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * Copyright (C) 2006 Freescale Semiconductor, Inc.
  4. * Dave Liu <daveliu@freescale.com>
  5. *
  6. * Copyright (C) 2007 Logic Product Development, Inc.
  7. * Peter Barada <peterb@logicpd.com>
  8. *
  9. * Copyright (C) 2007 MontaVista Software, Inc.
  10. * Anton Vorontsov <avorontsov@ru.mvista.com>
  11. *
  12. * (C) Copyright 2008 - 2010
  13. * Heiko Schocher, DENX Software Engineering, hs@denx.de.
  14. */
  15. #include <common.h>
  16. #include <env.h>
  17. #include <init.h>
  18. #include <ioports.h>
  19. #include <mpc83xx.h>
  20. #include <i2c.h>
  21. #include <miiphy.h>
  22. #include <asm/io.h>
  23. #include <asm/mmu.h>
  24. #include <asm/processor.h>
  25. #include <pci.h>
  26. #include <linux/libfdt.h>
  27. #include <post.h>
  28. #include "../common/common.h"
  29. DECLARE_GLOBAL_DATA_PTR;
  30. static uchar ivm_content[CONFIG_SYS_IVM_EEPROM_MAX_LEN];
  31. const qe_iop_conf_t qe_iop_conf_tab[] = {
  32. /* port pin dir open_drain assign */
  33. #if defined(CONFIG_ARCH_MPC8360)
  34. /* MDIO */
  35. {0, 1, 3, 0, 2}, /* MDIO */
  36. {0, 2, 1, 0, 1}, /* MDC */
  37. /* UCC4 - UEC */
  38. {1, 14, 1, 0, 1}, /* TxD0 */
  39. {1, 15, 1, 0, 1}, /* TxD1 */
  40. {1, 20, 2, 0, 1}, /* RxD0 */
  41. {1, 21, 2, 0, 1}, /* RxD1 */
  42. {1, 18, 1, 0, 1}, /* TX_EN */
  43. {1, 26, 2, 0, 1}, /* RX_DV */
  44. {1, 27, 2, 0, 1}, /* RX_ER */
  45. {1, 24, 2, 0, 1}, /* COL */
  46. {1, 25, 2, 0, 1}, /* CRS */
  47. {2, 15, 2, 0, 1}, /* TX_CLK - CLK16 */
  48. {2, 16, 2, 0, 1}, /* RX_CLK - CLK17 */
  49. /* DUART - UART2 */
  50. {5, 0, 1, 0, 2}, /* UART2_SOUT */
  51. {5, 2, 1, 0, 1}, /* UART2_RTS */
  52. {5, 3, 2, 0, 2}, /* UART2_SIN */
  53. {5, 1, 2, 0, 3}, /* UART2_CTS */
  54. #elif !defined(CONFIG_ARCH_MPC8309)
  55. /* Local Bus */
  56. {0, 16, 1, 0, 3}, /* LA00 */
  57. {0, 17, 1, 0, 3}, /* LA01 */
  58. {0, 18, 1, 0, 3}, /* LA02 */
  59. {0, 19, 1, 0, 3}, /* LA03 */
  60. {0, 20, 1, 0, 3}, /* LA04 */
  61. {0, 21, 1, 0, 3}, /* LA05 */
  62. {0, 22, 1, 0, 3}, /* LA06 */
  63. {0, 23, 1, 0, 3}, /* LA07 */
  64. {0, 24, 1, 0, 3}, /* LA08 */
  65. {0, 25, 1, 0, 3}, /* LA09 */
  66. {0, 26, 1, 0, 3}, /* LA10 */
  67. {0, 27, 1, 0, 3}, /* LA11 */
  68. {0, 28, 1, 0, 3}, /* LA12 */
  69. {0, 29, 1, 0, 3}, /* LA13 */
  70. {0, 30, 1, 0, 3}, /* LA14 */
  71. {0, 31, 1, 0, 3}, /* LA15 */
  72. /* MDIO */
  73. {3, 4, 3, 0, 2}, /* MDIO */
  74. {3, 5, 1, 0, 2}, /* MDC */
  75. /* UCC4 - UEC */
  76. {1, 18, 1, 0, 1}, /* TxD0 */
  77. {1, 19, 1, 0, 1}, /* TxD1 */
  78. {1, 22, 2, 0, 1}, /* RxD0 */
  79. {1, 23, 2, 0, 1}, /* RxD1 */
  80. {1, 26, 2, 0, 1}, /* RxER */
  81. {1, 28, 2, 0, 1}, /* Rx_DV */
  82. {1, 30, 1, 0, 1}, /* TxEN */
  83. {1, 31, 2, 0, 1}, /* CRS */
  84. {3, 10, 2, 0, 3}, /* TxCLK->CLK17 */
  85. #endif
  86. /* END of table */
  87. {0, 0, 0, 0, QE_IOP_TAB_END},
  88. };
  89. #if defined(CONFIG_SUVD3)
  90. const uint upma_table[] = {
  91. 0x1ffedc00, 0x0ffcdc80, 0x0ffcdc80, 0x0ffcdc04, /* Words 0 to 3 */
  92. 0x0ffcdc00, 0xffffcc00, 0xffffcc01, 0xfffffc01, /* Words 4 to 7 */
  93. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 8 to 11 */
  94. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 12 to 15 */
  95. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 16 to 19 */
  96. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 20 to 23 */
  97. 0x9cfffc00, 0x00fffc80, 0x00fffc80, 0x00fffc00, /* Words 24 to 27 */
  98. 0xffffec04, 0xffffec01, 0xfffffc01, 0xfffffc01, /* Words 28 to 31 */
  99. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 32 to 35 */
  100. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 36 to 39 */
  101. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 40 to 43 */
  102. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 44 to 47 */
  103. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 48 to 51 */
  104. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 52 to 55 */
  105. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01, /* Words 56 to 59 */
  106. 0xfffffc01, 0xfffffc01, 0xfffffc01, 0xfffffc01 /* Words 60 to 63 */
  107. };
  108. #endif
  109. static int piggy_present(void)
  110. {
  111. struct km_bec_fpga __iomem *base =
  112. (struct km_bec_fpga __iomem *)CONFIG_SYS_KMBEC_FPGA_BASE;
  113. return in_8(&base->bprth) & PIGGY_PRESENT;
  114. }
  115. int ethernet_present(void)
  116. {
  117. return piggy_present();
  118. }
  119. int board_early_init_r(void)
  120. {
  121. struct km_bec_fpga *base =
  122. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  123. #if defined(CONFIG_SUVD3)
  124. immap_t *immap = (immap_t *) CONFIG_SYS_IMMR;
  125. fsl_lbc_t *lbc = &immap->im_lbc;
  126. u32 *mxmr = &lbc->mamr;
  127. #endif
  128. #if defined(CONFIG_ARCH_MPC8360)
  129. unsigned short svid;
  130. /*
  131. * Because of errata in the UCCs, we have to write to the reserved
  132. * registers to slow the clocks down.
  133. */
  134. svid = SVR_REV(mfspr(SVR));
  135. switch (svid) {
  136. case 0x0020:
  137. /*
  138. * MPC8360ECE.pdf QE_ENET10 table 4:
  139. * IMMR + 0x14A8[4:5] = 11 (clk delay for UCC 2)
  140. * IMMR + 0x14A8[18:19] = 11 (clk delay for UCC 1)
  141. */
  142. setbits_be32((void *)(CONFIG_SYS_IMMR + 0x14a8), 0x0c003000);
  143. break;
  144. case 0x0021:
  145. /*
  146. * MPC8360ECE.pdf QE_ENET10 table 4:
  147. * IMMR + 0x14AC[24:27] = 1010
  148. */
  149. clrsetbits_be32((void *)(CONFIG_SYS_IMMR + 0x14ac),
  150. 0x00000050, 0x000000a0);
  151. break;
  152. }
  153. #endif
  154. /* enable the PHY on the PIGGY */
  155. setbits_8(&base->pgy_eth, 0x01);
  156. /* enable the Unit LED (green) */
  157. setbits_8(&base->oprth, WRL_BOOT);
  158. /* enable Application Buffer */
  159. setbits_8(&base->oprtl, OPRTL_XBUFENA);
  160. #if defined(CONFIG_SUVD3)
  161. /* configure UPMA for APP1 */
  162. upmconfig(UPMA, (uint *) upma_table,
  163. sizeof(upma_table) / sizeof(uint));
  164. out_be32(mxmr, CONFIG_SYS_MAMR);
  165. #endif
  166. return 0;
  167. }
  168. int misc_init_r(void)
  169. {
  170. ivm_read_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  171. return 0;
  172. }
  173. int last_stage_init(void)
  174. {
  175. #if defined(CONFIG_TARGET_KMCOGE5NE)
  176. struct bfticu_iomap *base =
  177. (struct bfticu_iomap *)CONFIG_SYS_BFTIC3_BASE;
  178. u8 dip_switch = in_8((u8 *)&(base->mswitch)) & BFTICU_DIPSWITCH_MASK;
  179. if (dip_switch != 0) {
  180. /* start bootloader */
  181. puts("DIP: Enabled\n");
  182. env_set("actual_bank", "0");
  183. }
  184. #endif
  185. set_km_env();
  186. return 0;
  187. }
  188. static int fixed_sdram(void)
  189. {
  190. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  191. u32 msize = 0;
  192. u32 ddr_size;
  193. u32 ddr_size_log2;
  194. out_be32(&im->sysconf.ddrlaw[0].ar, (LAWAR_EN | 0x1e));
  195. out_be32(&im->ddr.csbnds[0].csbnds, (CONFIG_SYS_DDR_CS0_BNDS) | 0x7f);
  196. out_be32(&im->ddr.cs_config[0], CONFIG_SYS_DDR_CS0_CONFIG);
  197. out_be32(&im->ddr.timing_cfg_0, CONFIG_SYS_DDR_TIMING_0);
  198. out_be32(&im->ddr.timing_cfg_1, CONFIG_SYS_DDR_TIMING_1);
  199. out_be32(&im->ddr.timing_cfg_2, CONFIG_SYS_DDR_TIMING_2);
  200. out_be32(&im->ddr.timing_cfg_3, CONFIG_SYS_DDR_TIMING_3);
  201. out_be32(&im->ddr.sdram_cfg, CONFIG_SYS_DDR_SDRAM_CFG);
  202. out_be32(&im->ddr.sdram_cfg2, CONFIG_SYS_DDR_SDRAM_CFG2);
  203. out_be32(&im->ddr.sdram_mode, CONFIG_SYS_DDR_MODE);
  204. out_be32(&im->ddr.sdram_mode2, CONFIG_SYS_DDR_MODE2);
  205. out_be32(&im->ddr.sdram_interval, CONFIG_SYS_DDR_INTERVAL);
  206. out_be32(&im->ddr.sdram_clk_cntl, CONFIG_SYS_DDR_CLK_CNTL);
  207. udelay(200);
  208. setbits_be32(&im->ddr.sdram_cfg, SDRAM_CFG_MEM_EN);
  209. msize = CONFIG_SYS_DDR_SIZE << 20;
  210. disable_addr_trans();
  211. msize = get_ram_size(CONFIG_SYS_SDRAM_BASE, msize);
  212. enable_addr_trans();
  213. msize /= (1024 * 1024);
  214. if (CONFIG_SYS_DDR_SIZE != msize) {
  215. for (ddr_size = msize << 20, ddr_size_log2 = 0;
  216. (ddr_size > 1);
  217. ddr_size = ddr_size >> 1, ddr_size_log2++)
  218. if (ddr_size & 1)
  219. return -1;
  220. out_be32(&im->sysconf.ddrlaw[0].ar,
  221. (LAWAR_EN | ((ddr_size_log2 - 1) & LAWAR_SIZE)));
  222. out_be32(&im->ddr.csbnds[0].csbnds,
  223. (((msize / 16) - 1) & 0xff));
  224. }
  225. return msize;
  226. }
  227. int dram_init(void)
  228. {
  229. immap_t *im = (immap_t *)CONFIG_SYS_IMMR;
  230. u32 msize = 0;
  231. if ((in_be32(&im->sysconf.immrbar) & IMMRBAR_BASE_ADDR) != (u32)im)
  232. return -ENXIO;
  233. out_be32(&im->sysconf.ddrlaw[0].bar,
  234. CONFIG_SYS_SDRAM_BASE & LAWBAR_BAR);
  235. msize = fixed_sdram();
  236. #if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER)
  237. /*
  238. * Initialize DDR ECC byte
  239. */
  240. ddr_enable_ecc(msize * 1024 * 1024);
  241. #endif
  242. /* return total bus SDRAM size(bytes) -- DDR */
  243. gd->ram_size = msize * 1024 * 1024;
  244. return 0;
  245. }
  246. int checkboard(void)
  247. {
  248. puts("Board: ABB " CONFIG_SYS_CONFIG_NAME);
  249. if (piggy_present())
  250. puts(" with PIGGY.");
  251. puts("\n");
  252. return 0;
  253. }
  254. int ft_board_setup(void *blob, bd_t *bd)
  255. {
  256. ft_cpu_setup(blob, bd);
  257. return 0;
  258. }
  259. #if defined(CONFIG_HUSH_INIT_VAR)
  260. int hush_init_var(void)
  261. {
  262. ivm_analyze_eeprom(ivm_content, CONFIG_SYS_IVM_EEPROM_MAX_LEN);
  263. return 0;
  264. }
  265. #endif
  266. #if defined(CONFIG_POST)
  267. int post_hotkeys_pressed(void)
  268. {
  269. int testpin = 0;
  270. struct km_bec_fpga *base =
  271. (struct km_bec_fpga *)CONFIG_SYS_KMBEC_FPGA_BASE;
  272. int testpin_reg = in_8(&base->CONFIG_TESTPIN_REG);
  273. testpin = (testpin_reg & CONFIG_TESTPIN_MASK) != 0;
  274. debug("post_hotkeys_pressed: %d\n", !testpin);
  275. return testpin;
  276. }
  277. ulong post_word_load(void)
  278. {
  279. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  280. debug("post_word_load 0x%08lX: 0x%08X\n", (ulong)addr, in_le32(addr));
  281. return in_le32(addr);
  282. }
  283. void post_word_store(ulong value)
  284. {
  285. void* addr = (ulong *) (CPM_POST_WORD_ADDR);
  286. debug("post_word_store 0x%08lX: 0x%08lX\n", (ulong)addr, value);
  287. out_le32(addr, value);
  288. }
  289. int arch_memory_test_prepare(u32 *vstart, u32 *size, phys_addr_t *phys_offset)
  290. {
  291. *vstart = CONFIG_SYS_MEMTEST_START;
  292. *size = CONFIG_SYS_MEMTEST_END - CONFIG_SYS_MEMTEST_START;
  293. debug("arch_memory_test_prepare 0x%08X 0x%08X\n", *vstart, *size);
  294. return 0;
  295. }
  296. #endif