am3517_crane.h 6.6 KB

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  1. /* SPDX-License-Identifier: GPL-2.0+ */
  2. /*
  3. * am3517_crane.h - Default configuration for AM3517 CraneBoard.
  4. *
  5. * Author: Srinath.R <srinath@mistralsolutions.com>
  6. *
  7. * Based on include/configs/am3517evm.h
  8. *
  9. * Copyright (C) 2011 Mistral Solutions pvt Ltd
  10. */
  11. #ifndef __CONFIG_H
  12. #define __CONFIG_H
  13. /*
  14. * High Level Configuration Options
  15. */
  16. #include <asm/arch/cpu.h> /* get chip and board defs */
  17. #include <asm/arch/omap.h>
  18. /* Clock Defines */
  19. #define V_OSCK 26000000 /* Clock output from T2 */
  20. #define V_SCLK (V_OSCK >> 1)
  21. #define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */
  22. #define CONFIG_SETUP_MEMORY_TAGS 1
  23. #define CONFIG_INITRD_TAG 1
  24. #define CONFIG_REVISION_TAG 1
  25. /*
  26. * Size of malloc() pool
  27. */
  28. #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (128 << 10))
  29. /* initial data */
  30. /*
  31. * DDR related
  32. */
  33. #define CONFIG_SYS_CS0_SIZE (256 * 1024 * 1024)
  34. /*
  35. * Hardware drivers
  36. */
  37. /*
  38. * NS16550 Configuration
  39. */
  40. #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */
  41. #define CONFIG_SYS_NS16550_SERIAL
  42. #define CONFIG_SYS_NS16550_REG_SIZE (-4)
  43. #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
  44. /*
  45. * select serial console configuration
  46. */
  47. #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3
  48. #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
  49. 115200}
  50. /*
  51. * USB configuration
  52. * Enable CONFIG_USB_MUSB_HCD for Host functionalities MSC, keyboard
  53. * Enable CONFIG_USB_MUSB_UDC for Device functionalities.
  54. */
  55. #ifdef CONFIG_USB_AM35X
  56. #ifdef CONFIG_USB_MUSB_UDC
  57. /* USB device configuration */
  58. #define CONFIG_USB_DEVICE 1
  59. #define CONFIG_USB_TTY 1
  60. /* Change these to suit your needs */
  61. #define CONFIG_USBD_VENDORID 0x0451
  62. #define CONFIG_USBD_PRODUCTID 0x5678
  63. #define CONFIG_USBD_MANUFACTURER "Texas Instruments"
  64. #define CONFIG_USBD_PRODUCT_NAME "AM3517CRANE"
  65. #endif /* CONFIG_USB_MUSB_UDC */
  66. #endif /* CONFIG_USB_AM35X */
  67. #define CONFIG_SYS_I2C
  68. /*
  69. * Board NAND Info.
  70. */
  71. #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */
  72. /* to access */
  73. /* nand at CS0 */
  74. #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */
  75. /* NAND devices */
  76. #define CONFIG_JFFS2_NAND
  77. /* nand device jffs2 lives on */
  78. #define CONFIG_JFFS2_DEV "nand0"
  79. /* start of jffs2 partition */
  80. #define CONFIG_JFFS2_PART_OFFSET 0x680000
  81. #define CONFIG_JFFS2_PART_SIZE 0xf980000 /* sz of jffs2 part */
  82. /* Environment information */
  83. #define CONFIG_BOOTFILE "uImage"
  84. #define CONFIG_EXTRA_ENV_SETTINGS \
  85. "loadaddr=0x82000000\0" \
  86. "console=ttyS2,115200n8\0" \
  87. "mmcdev=0\0" \
  88. "mmcargs=setenv bootargs console=${console} " \
  89. "root=/dev/mmcblk0p2 rw " \
  90. "rootfstype=ext3 rootwait\0" \
  91. "nandargs=setenv bootargs console=${console} " \
  92. "root=/dev/mtdblock4 rw " \
  93. "rootfstype=jffs2\0" \
  94. "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \
  95. "bootscript=echo Running bootscript from mmc ...; " \
  96. "source ${loadaddr}\0" \
  97. "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \
  98. "mmcboot=echo Booting from mmc ...; " \
  99. "run mmcargs; " \
  100. "bootm ${loadaddr}\0" \
  101. "nandboot=echo Booting from nand ...; " \
  102. "run nandargs; " \
  103. "nand read ${loadaddr} 280000 400000; " \
  104. "bootm ${loadaddr}\0" \
  105. #define CONFIG_BOOTCOMMAND \
  106. "mmc dev ${mmcdev}; if mmc rescan; then " \
  107. "if run loadbootscript; then " \
  108. "run bootscript; " \
  109. "else " \
  110. "if run loaduimage; then " \
  111. "run mmcboot; " \
  112. "else run nandboot; " \
  113. "fi; " \
  114. "fi; " \
  115. "else run nandboot; fi"
  116. /*
  117. * Miscellaneous configurable options
  118. */
  119. #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */
  120. #define CONFIG_SYS_MAXARGS 32 /* max number of command */
  121. /* args */
  122. /* memtest works on */
  123. #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default load */
  124. /* address */
  125. /*
  126. * AM3517 has 12 GP timers, they can be driven by the system clock
  127. * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK).
  128. * This rate is divided by a local divisor.
  129. */
  130. #define CONFIG_SYS_TIMERBASE OMAP34XX_GPT2
  131. #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */
  132. /*-----------------------------------------------------------------------
  133. * Physical Memory Map
  134. */
  135. #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0
  136. #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1
  137. /*-----------------------------------------------------------------------
  138. * FLASH and environment organization
  139. */
  140. /* **** PISMO SUPPORT *** */
  141. #define CONFIG_SYS_MAX_FLASH_SECT 520 /* max number of sectors */
  142. /* on one chip */
  143. #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of flash banks */
  144. #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
  145. #define CONFIG_SYS_FLASH_BASE NAND_BASE
  146. /* Monitor at start of flash */
  147. #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
  148. #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) /* 128 KiB sector */
  149. /*-----------------------------------------------------------------------
  150. * CFI FLASH driver setup
  151. */
  152. /* timeout values are in ticks */
  153. #define CONFIG_SYS_FLASH_ERASE_TOUT (100 * CONFIG_SYS_HZ)
  154. #define CONFIG_SYS_FLASH_WRITE_TOUT (100 * CONFIG_SYS_HZ)
  155. /* Flash banks JFFS2 should use */
  156. #define CONFIG_SYS_MAX_MTD_BANKS (CONFIG_SYS_MAX_FLASH_BANKS + \
  157. CONFIG_SYS_MAX_NAND_DEVICE)
  158. #define CONFIG_SYS_JFFS2_MEM_NAND
  159. /* use flash_info[2] */
  160. #define CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_MAX_FLASH_BANKS
  161. #define CONFIG_SYS_JFFS2_NUM_BANKS 1
  162. #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
  163. #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800
  164. #define CONFIG_SYS_INIT_RAM_SIZE 0x800
  165. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
  166. CONFIG_SYS_INIT_RAM_SIZE - \
  167. GENERATED_GBL_DATA_SIZE)
  168. /* Defines for SPL */
  169. #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \
  170. CONFIG_SPL_TEXT_BASE)
  171. #define CONFIG_SPL_BSS_START_ADDR 0x80000000
  172. #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */
  173. #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img"
  174. /* NAND boot config */
  175. #define CONFIG_SYS_NAND_5_ADDR_CYCLE
  176. #define CONFIG_SYS_NAND_PAGE_COUNT 64
  177. #define CONFIG_SYS_NAND_PAGE_SIZE 2048
  178. #define CONFIG_SYS_NAND_OOBSIZE 64
  179. #define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024)
  180. #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS
  181. #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\
  182. 10, 11, 12, 13}
  183. #define CONFIG_SYS_NAND_ECCSIZE 512
  184. #define CONFIG_SYS_NAND_ECCBYTES 3
  185. #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW
  186. #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
  187. #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000
  188. /*
  189. * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM
  190. * 64 bytes before this address should be set aside for u-boot.img's
  191. * header. That is 0x800FFFC0--0x80100000 should not be used for any
  192. * other needs.
  193. */
  194. #define CONFIG_SYS_SPL_MALLOC_START 0x80208000
  195. #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000
  196. #endif /* __CONFIG_H */