phy-sun4i-usb.c 14 KB

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  1. /*
  2. * Allwinner sun4i USB PHY driver
  3. *
  4. * Copyright (C) 2017 Jagan Teki <jagan@amarulasolutions.com>
  5. * Copyright (C) 2015 Hans de Goede <hdegoede@redhat.com>
  6. * Copyright (C) 2014 Roman Byshko <rbyshko@gmail.com>
  7. *
  8. * Modelled arch/arm/mach-sunxi/usb_phy.c to compatible with generic-phy.
  9. *
  10. * SPDX-License-Identifier: GPL-2.0+
  11. */
  12. #include <common.h>
  13. #include <dm.h>
  14. #include <dm/device.h>
  15. #include <generic-phy.h>
  16. #include <phy-sun4i-usb.h>
  17. #include <asm/gpio.h>
  18. #include <asm/io.h>
  19. #include <asm/arch/clock.h>
  20. #include <asm/arch/cpu.h>
  21. #define REG_ISCR 0x00
  22. #define REG_PHYCTL_A10 0x04
  23. #define REG_PHYBIST 0x08
  24. #define REG_PHYTUNE 0x0c
  25. #define REG_PHYCTL_A33 0x10
  26. #define REG_PHY_OTGCTL 0x20
  27. #define REG_PMU_UNK1 0x10
  28. /* Common Control Bits for Both PHYs */
  29. #define PHY_PLL_BW 0x03
  30. #define PHY_RES45_CAL_EN 0x0c
  31. /* Private Control Bits for Each PHY */
  32. #define PHY_TX_AMPLITUDE_TUNE 0x20
  33. #define PHY_TX_SLEWRATE_TUNE 0x22
  34. #define PHY_DISCON_TH_SEL 0x2a
  35. #define PHY_SQUELCH_DETECT 0x3c
  36. #define PHYCTL_DATA BIT(7)
  37. #define OTGCTL_ROUTE_MUSB BIT(0)
  38. #define PHY_TX_RATE BIT(4)
  39. #define PHY_TX_MAGNITUDE BIT(2)
  40. #define PHY_TX_AMPLITUDE_LEN 5
  41. #define PHY_RES45_CAL_DATA BIT(0)
  42. #define PHY_RES45_CAL_LEN 1
  43. #define PHY_DISCON_TH_LEN 2
  44. #define SUNXI_AHB_ICHR8_EN BIT(10)
  45. #define SUNXI_AHB_INCR4_BURST_EN BIT(9)
  46. #define SUNXI_AHB_INCRX_ALIGN_EN BIT(8)
  47. #define SUNXI_ULPI_BYPASS_EN BIT(0)
  48. /* A83T specific control bits for PHY0 */
  49. #define PHY_CTL_VBUSVLDEXT BIT(5)
  50. #define PHY_CTL_SIDDQ BIT(3)
  51. /* A83T specific control bits for PHY2 HSIC */
  52. #define SUNXI_EHCI_HS_FORCE BIT(20)
  53. #define SUNXI_HSIC_CONNECT_INT BIT(16)
  54. #define SUNXI_HSIC BIT(1)
  55. #define MAX_PHYS 4
  56. enum sun4i_usb_phy_type {
  57. sun4i_a10_phy,
  58. sun6i_a31_phy,
  59. sun8i_a33_phy,
  60. sun8i_a83t_phy,
  61. sun8i_h3_phy,
  62. sun8i_v3s_phy,
  63. sun50i_a64_phy,
  64. };
  65. struct sun4i_usb_phy_cfg {
  66. int num_phys;
  67. enum sun4i_usb_phy_type type;
  68. u32 disc_thresh;
  69. u8 phyctl_offset;
  70. bool enable_pmu_unk1;
  71. bool phy0_dual_route;
  72. };
  73. struct sun4i_usb_phy_info {
  74. const char *gpio_vbus;
  75. const char *gpio_vbus_det;
  76. const char *gpio_id_det;
  77. int rst_mask;
  78. } phy_info[] = {
  79. {
  80. .gpio_vbus = CONFIG_USB0_VBUS_PIN,
  81. .gpio_vbus_det = CONFIG_USB0_VBUS_DET,
  82. .gpio_id_det = CONFIG_USB0_ID_DET,
  83. .rst_mask = (CCM_USB_CTRL_PHY0_RST | CCM_USB_CTRL_PHY0_CLK),
  84. },
  85. {
  86. .gpio_vbus = CONFIG_USB1_VBUS_PIN,
  87. .gpio_vbus_det = NULL,
  88. .gpio_id_det = NULL,
  89. .rst_mask = (CCM_USB_CTRL_PHY1_RST | CCM_USB_CTRL_PHY1_CLK),
  90. },
  91. {
  92. .gpio_vbus = CONFIG_USB2_VBUS_PIN,
  93. .gpio_vbus_det = NULL,
  94. .gpio_id_det = NULL,
  95. #ifdef CONFIG_MACH_SUN8I_A83T
  96. .rst_mask = (CCM_USB_CTRL_HSIC_RST | CCM_USB_CTRL_HSIC_CLK |
  97. CCM_USB_CTRL_12M_CLK),
  98. #else
  99. .rst_mask = (CCM_USB_CTRL_PHY2_RST | CCM_USB_CTRL_PHY2_CLK),
  100. #endif
  101. },
  102. {
  103. .gpio_vbus = CONFIG_USB3_VBUS_PIN,
  104. .gpio_vbus_det = NULL,
  105. .gpio_id_det = NULL,
  106. #ifdef CONFIG_MACH_SUN6I
  107. .rst_mask = (CCM_USB_CTRL_PHY3_RST | CCM_USB_CTRL_PHY3_CLK),
  108. #endif
  109. },
  110. };
  111. struct sun4i_usb_phy_plat {
  112. void __iomem *pmu;
  113. int power_on_count;
  114. int gpio_vbus;
  115. int gpio_vbus_det;
  116. int gpio_id_det;
  117. int rst_mask;
  118. int id;
  119. };
  120. struct sun4i_usb_phy_data {
  121. void __iomem *base;
  122. struct sunxi_ccm_reg *ccm;
  123. const struct sun4i_usb_phy_cfg *cfg;
  124. struct sun4i_usb_phy_plat *usb_phy;
  125. };
  126. static int initial_usb_scan_delay = CONFIG_INITIAL_USB_SCAN_DELAY;
  127. static void sun4i_usb_phy_write(struct phy *phy, u32 addr, u32 data, int len)
  128. {
  129. struct sun4i_usb_phy_data *phy_data = dev_get_priv(phy->dev);
  130. struct sun4i_usb_phy_plat *usb_phy = &phy_data->usb_phy[phy->id];
  131. u32 temp, usbc_bit = BIT(usb_phy->id * 2);
  132. void __iomem *phyctl = phy_data->base + phy_data->cfg->phyctl_offset;
  133. int i;
  134. if (phy_data->cfg->phyctl_offset == REG_PHYCTL_A33) {
  135. /* SoCs newer than A33 need us to set phyctl to 0 explicitly */
  136. writel(0, phyctl);
  137. }
  138. for (i = 0; i < len; i++) {
  139. temp = readl(phyctl);
  140. /* clear the address portion */
  141. temp &= ~(0xff << 8);
  142. /* set the address */
  143. temp |= ((addr + i) << 8);
  144. writel(temp, phyctl);
  145. /* set the data bit and clear usbc bit*/
  146. temp = readb(phyctl);
  147. if (data & 0x1)
  148. temp |= PHYCTL_DATA;
  149. else
  150. temp &= ~PHYCTL_DATA;
  151. temp &= ~usbc_bit;
  152. writeb(temp, phyctl);
  153. /* pulse usbc_bit */
  154. temp = readb(phyctl);
  155. temp |= usbc_bit;
  156. writeb(temp, phyctl);
  157. temp = readb(phyctl);
  158. temp &= ~usbc_bit;
  159. writeb(temp, phyctl);
  160. data >>= 1;
  161. }
  162. }
  163. static void sun4i_usb_phy_passby(struct phy *phy, bool enable)
  164. {
  165. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  166. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  167. u32 bits, reg_value;
  168. if (!usb_phy->pmu)
  169. return;
  170. bits = SUNXI_AHB_ICHR8_EN | SUNXI_AHB_INCR4_BURST_EN |
  171. SUNXI_AHB_INCRX_ALIGN_EN | SUNXI_ULPI_BYPASS_EN;
  172. /* A83T USB2 is HSIC */
  173. if (data->cfg->type == sun8i_a83t_phy && usb_phy->id == 2)
  174. bits |= SUNXI_EHCI_HS_FORCE | SUNXI_HSIC_CONNECT_INT |
  175. SUNXI_HSIC;
  176. reg_value = readl(usb_phy->pmu);
  177. if (enable)
  178. reg_value |= bits;
  179. else
  180. reg_value &= ~bits;
  181. writel(reg_value, usb_phy->pmu);
  182. }
  183. static int sun4i_usb_phy_power_on(struct phy *phy)
  184. {
  185. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  186. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  187. if (initial_usb_scan_delay) {
  188. mdelay(initial_usb_scan_delay);
  189. initial_usb_scan_delay = 0;
  190. }
  191. usb_phy->power_on_count++;
  192. if (usb_phy->power_on_count != 1)
  193. return 0;
  194. if (usb_phy->gpio_vbus >= 0)
  195. gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_UP);
  196. return 0;
  197. }
  198. static int sun4i_usb_phy_power_off(struct phy *phy)
  199. {
  200. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  201. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  202. usb_phy->power_on_count--;
  203. if (usb_phy->power_on_count != 0)
  204. return 0;
  205. if (usb_phy->gpio_vbus >= 0)
  206. gpio_set_value(usb_phy->gpio_vbus, SUNXI_GPIO_PULL_DISABLE);
  207. return 0;
  208. }
  209. static void sun4i_usb_phy0_reroute(struct sun4i_usb_phy_data *data, bool id_det)
  210. {
  211. u32 regval;
  212. regval = readl(data->base + REG_PHY_OTGCTL);
  213. if (!id_det) {
  214. /* Host mode. Route phy0 to EHCI/OHCI */
  215. regval &= ~OTGCTL_ROUTE_MUSB;
  216. } else {
  217. /* Peripheral mode. Route phy0 to MUSB */
  218. regval |= OTGCTL_ROUTE_MUSB;
  219. }
  220. writel(regval, data->base + REG_PHY_OTGCTL);
  221. }
  222. static int sun4i_usb_phy_init(struct phy *phy)
  223. {
  224. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  225. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  226. u32 val;
  227. setbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
  228. if (data->cfg->type == sun8i_a83t_phy) {
  229. if (phy->id == 0) {
  230. val = readl(data->base + data->cfg->phyctl_offset);
  231. val |= PHY_CTL_VBUSVLDEXT;
  232. val &= ~PHY_CTL_SIDDQ;
  233. writel(val, data->base + data->cfg->phyctl_offset);
  234. }
  235. } else {
  236. if (usb_phy->pmu && data->cfg->enable_pmu_unk1) {
  237. val = readl(usb_phy->pmu + REG_PMU_UNK1);
  238. writel(val & ~2, usb_phy->pmu + REG_PMU_UNK1);
  239. }
  240. if (usb_phy->id == 0)
  241. sun4i_usb_phy_write(phy, PHY_RES45_CAL_EN,
  242. PHY_RES45_CAL_DATA,
  243. PHY_RES45_CAL_LEN);
  244. /* Adjust PHY's magnitude and rate */
  245. sun4i_usb_phy_write(phy, PHY_TX_AMPLITUDE_TUNE,
  246. PHY_TX_MAGNITUDE | PHY_TX_RATE,
  247. PHY_TX_AMPLITUDE_LEN);
  248. /* Disconnect threshold adjustment */
  249. sun4i_usb_phy_write(phy, PHY_DISCON_TH_SEL,
  250. data->cfg->disc_thresh, PHY_DISCON_TH_LEN);
  251. }
  252. if (usb_phy->id != 0)
  253. sun4i_usb_phy_passby(phy, true);
  254. sun4i_usb_phy0_reroute(data, true);
  255. return 0;
  256. }
  257. static int sun4i_usb_phy_exit(struct phy *phy)
  258. {
  259. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  260. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  261. if (phy->id == 0) {
  262. if (data->cfg->type == sun8i_a83t_phy) {
  263. void __iomem *phyctl = data->base +
  264. data->cfg->phyctl_offset;
  265. writel(readl(phyctl) | PHY_CTL_SIDDQ, phyctl);
  266. }
  267. }
  268. sun4i_usb_phy_passby(phy, false);
  269. clrbits_le32(&data->ccm->usb_clk_cfg, usb_phy->rst_mask);
  270. return 0;
  271. }
  272. static int sun4i_usb_phy_xlate(struct phy *phy,
  273. struct ofnode_phandle_args *args)
  274. {
  275. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  276. if (args->args_count >= data->cfg->num_phys)
  277. return -EINVAL;
  278. if (args->args_count)
  279. phy->id = args->args[0];
  280. else
  281. phy->id = 0;
  282. debug("%s: phy_id = %ld\n", __func__, phy->id);
  283. return 0;
  284. }
  285. int sun4i_usb_phy_vbus_detect(struct phy *phy)
  286. {
  287. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  288. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  289. int err, retries = 3;
  290. debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
  291. if (usb_phy->gpio_vbus_det < 0)
  292. return usb_phy->gpio_vbus_det;
  293. err = gpio_get_value(usb_phy->gpio_vbus_det);
  294. /*
  295. * Vbus may have been provided by the board and just been turned of
  296. * some milliseconds ago on reset, what we're measuring then is a
  297. * residual charge on Vbus, sleep a bit and try again.
  298. */
  299. while (err > 0 && retries--) {
  300. mdelay(100);
  301. err = gpio_get_value(usb_phy->gpio_vbus_det);
  302. }
  303. return err;
  304. }
  305. int sun4i_usb_phy_id_detect(struct phy *phy)
  306. {
  307. struct sun4i_usb_phy_data *data = dev_get_priv(phy->dev);
  308. struct sun4i_usb_phy_plat *usb_phy = &data->usb_phy[phy->id];
  309. debug("%s: id_det = %d\n", __func__, usb_phy->gpio_id_det);
  310. if (usb_phy->gpio_id_det < 0)
  311. return usb_phy->gpio_id_det;
  312. return gpio_get_value(usb_phy->gpio_id_det);
  313. }
  314. void sun4i_usb_phy_set_squelch_detect(struct phy *phy, bool enabled)
  315. {
  316. sun4i_usb_phy_write(phy, PHY_SQUELCH_DETECT, enabled ? 0 : 2, 2);
  317. }
  318. static struct phy_ops sun4i_usb_phy_ops = {
  319. .of_xlate = sun4i_usb_phy_xlate,
  320. .init = sun4i_usb_phy_init,
  321. .power_on = sun4i_usb_phy_power_on,
  322. .power_off = sun4i_usb_phy_power_off,
  323. .exit = sun4i_usb_phy_exit,
  324. };
  325. static int sun4i_usb_phy_probe(struct udevice *dev)
  326. {
  327. struct sun4i_usb_phy_plat *plat = dev_get_platdata(dev);
  328. struct sun4i_usb_phy_data *data = dev_get_priv(dev);
  329. int i, ret;
  330. data->cfg = (const struct sun4i_usb_phy_cfg *)dev_get_driver_data(dev);
  331. if (!data->cfg)
  332. return -EINVAL;
  333. data->base = (void __iomem *)devfdt_get_addr_name(dev, "phy_ctrl");
  334. if (IS_ERR(data->base))
  335. return PTR_ERR(data->base);
  336. data->ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE;
  337. if (IS_ERR(data->ccm))
  338. return PTR_ERR(data->ccm);
  339. data->usb_phy = plat;
  340. for (i = 0; i < data->cfg->num_phys; i++) {
  341. struct sun4i_usb_phy_plat *phy = &plat[i];
  342. struct sun4i_usb_phy_info *info = &phy_info[i];
  343. char name[16];
  344. phy->gpio_vbus = sunxi_name_to_gpio(info->gpio_vbus);
  345. if (phy->gpio_vbus >= 0) {
  346. ret = gpio_request(phy->gpio_vbus, "usb_vbus");
  347. if (ret)
  348. return ret;
  349. ret = gpio_direction_output(phy->gpio_vbus, 0);
  350. if (ret)
  351. return ret;
  352. }
  353. phy->gpio_vbus_det = sunxi_name_to_gpio(info->gpio_vbus_det);
  354. if (phy->gpio_vbus_det >= 0) {
  355. ret = gpio_request(phy->gpio_vbus_det, "usb_vbus_det");
  356. if (ret)
  357. return ret;
  358. ret = gpio_direction_input(phy->gpio_vbus_det);
  359. if (ret)
  360. return ret;
  361. }
  362. phy->gpio_id_det = sunxi_name_to_gpio(info->gpio_id_det);
  363. if (phy->gpio_id_det >= 0) {
  364. ret = gpio_request(phy->gpio_id_det, "usb_id_det");
  365. if (ret)
  366. return ret;
  367. ret = gpio_direction_input(phy->gpio_id_det);
  368. if (ret)
  369. return ret;
  370. sunxi_gpio_set_pull(phy->gpio_id_det, SUNXI_GPIO_PULL_UP);
  371. }
  372. if (i || data->cfg->phy0_dual_route) {
  373. snprintf(name, sizeof(name), "pmu%d", i);
  374. phy->pmu = (void __iomem *)devfdt_get_addr_name(dev, name);
  375. if (IS_ERR(phy->pmu))
  376. return PTR_ERR(phy->pmu);
  377. }
  378. phy->id = i;
  379. phy->rst_mask = info->rst_mask;
  380. };
  381. setbits_le32(&data->ccm->usb_clk_cfg, CCM_USB_CTRL_PHYGATE);
  382. debug("Allwinner Sun4I USB PHY driver loaded\n");
  383. return 0;
  384. }
  385. static const struct sun4i_usb_phy_cfg sun4i_a10_cfg = {
  386. .num_phys = 3,
  387. .type = sun4i_a10_phy,
  388. .disc_thresh = 3,
  389. .phyctl_offset = REG_PHYCTL_A10,
  390. .enable_pmu_unk1 = false,
  391. };
  392. static const struct sun4i_usb_phy_cfg sun5i_a13_cfg = {
  393. .num_phys = 2,
  394. .type = sun4i_a10_phy,
  395. .disc_thresh = 2,
  396. .phyctl_offset = REG_PHYCTL_A10,
  397. .enable_pmu_unk1 = false,
  398. };
  399. static const struct sun4i_usb_phy_cfg sun6i_a31_cfg = {
  400. .num_phys = 3,
  401. .type = sun6i_a31_phy,
  402. .disc_thresh = 3,
  403. .phyctl_offset = REG_PHYCTL_A10,
  404. .enable_pmu_unk1 = false,
  405. };
  406. static const struct sun4i_usb_phy_cfg sun7i_a20_cfg = {
  407. .num_phys = 3,
  408. .type = sun4i_a10_phy,
  409. .disc_thresh = 2,
  410. .phyctl_offset = REG_PHYCTL_A10,
  411. .enable_pmu_unk1 = false,
  412. };
  413. static const struct sun4i_usb_phy_cfg sun8i_a23_cfg = {
  414. .num_phys = 2,
  415. .type = sun4i_a10_phy,
  416. .disc_thresh = 3,
  417. .phyctl_offset = REG_PHYCTL_A10,
  418. .enable_pmu_unk1 = false,
  419. };
  420. static const struct sun4i_usb_phy_cfg sun8i_a33_cfg = {
  421. .num_phys = 2,
  422. .type = sun8i_a33_phy,
  423. .disc_thresh = 3,
  424. .phyctl_offset = REG_PHYCTL_A33,
  425. .enable_pmu_unk1 = false,
  426. };
  427. static const struct sun4i_usb_phy_cfg sun8i_a83t_cfg = {
  428. .num_phys = 3,
  429. .type = sun8i_a83t_phy,
  430. .phyctl_offset = REG_PHYCTL_A33,
  431. };
  432. static const struct sun4i_usb_phy_cfg sun8i_h3_cfg = {
  433. .num_phys = 4,
  434. .type = sun8i_h3_phy,
  435. .disc_thresh = 3,
  436. .phyctl_offset = REG_PHYCTL_A33,
  437. .enable_pmu_unk1 = true,
  438. .phy0_dual_route = true,
  439. };
  440. static const struct sun4i_usb_phy_cfg sun8i_v3s_cfg = {
  441. .num_phys = 1,
  442. .type = sun8i_v3s_phy,
  443. .disc_thresh = 3,
  444. .phyctl_offset = REG_PHYCTL_A33,
  445. .enable_pmu_unk1 = true,
  446. .phy0_dual_route = true,
  447. };
  448. static const struct sun4i_usb_phy_cfg sun50i_a64_cfg = {
  449. .num_phys = 2,
  450. .type = sun50i_a64_phy,
  451. .disc_thresh = 3,
  452. .phyctl_offset = REG_PHYCTL_A33,
  453. .enable_pmu_unk1 = true,
  454. .phy0_dual_route = true,
  455. };
  456. static const struct udevice_id sun4i_usb_phy_ids[] = {
  457. { .compatible = "allwinner,sun4i-a10-usb-phy", .data = (ulong)&sun4i_a10_cfg },
  458. { .compatible = "allwinner,sun5i-a13-usb-phy", .data = (ulong)&sun5i_a13_cfg },
  459. { .compatible = "allwinner,sun6i-a31-usb-phy", .data = (ulong)&sun6i_a31_cfg },
  460. { .compatible = "allwinner,sun7i-a20-usb-phy", .data = (ulong)&sun7i_a20_cfg },
  461. { .compatible = "allwinner,sun8i-a23-usb-phy", .data = (ulong)&sun8i_a23_cfg },
  462. { .compatible = "allwinner,sun8i-a33-usb-phy", .data = (ulong)&sun8i_a33_cfg },
  463. { .compatible = "allwinner,sun8i-a83t-usb-phy", .data = (ulong)&sun8i_a83t_cfg },
  464. { .compatible = "allwinner,sun8i-h3-usb-phy", .data = (ulong)&sun8i_h3_cfg },
  465. { .compatible = "allwinner,sun8i-v3s-usb-phy", .data = (ulong)&sun8i_v3s_cfg },
  466. { .compatible = "allwinner,sun50i-a64-usb-phy", .data = (ulong)&sun50i_a64_cfg},
  467. { }
  468. };
  469. U_BOOT_DRIVER(sun4i_usb_phy) = {
  470. .name = "sun4i_usb_phy",
  471. .id = UCLASS_PHY,
  472. .of_match = sun4i_usb_phy_ids,
  473. .ops = &sun4i_usb_phy_ops,
  474. .probe = sun4i_usb_phy_probe,
  475. .platdata_auto_alloc_size = sizeof(struct sun4i_usb_phy_plat[MAX_PHYS]),
  476. .priv_auto_alloc_size = sizeof(struct sun4i_usb_phy_data),
  477. };