xhci.c 43 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * USB HOST XHCI Controller stack
  4. *
  5. * Based on xHCI host controller driver in linux-kernel
  6. * by Sarah Sharp.
  7. *
  8. * Copyright (C) 2008 Intel Corp.
  9. * Author: Sarah Sharp
  10. *
  11. * Copyright (C) 2013 Samsung Electronics Co.Ltd
  12. * Authors: Vivek Gautam <gautam.vivek@samsung.com>
  13. * Vikas Sajjan <vikas.sajjan@samsung.com>
  14. */
  15. /**
  16. * This file gives the xhci stack for usb3.0 looking into
  17. * xhci specification Rev1.0 (5/21/10).
  18. * The quirk devices support hasn't been given yet.
  19. */
  20. #include <common.h>
  21. #include <cpu_func.h>
  22. #include <dm.h>
  23. #include <log.h>
  24. #include <asm/byteorder.h>
  25. #include <usb.h>
  26. #include <malloc.h>
  27. #include <watchdog.h>
  28. #include <asm/cache.h>
  29. #include <asm/unaligned.h>
  30. #include <linux/bitops.h>
  31. #include <linux/bug.h>
  32. #include <linux/delay.h>
  33. #include <linux/errno.h>
  34. #include <linux/iopoll.h>
  35. #include <usb/xhci.h>
  36. #ifndef CONFIG_USB_MAX_CONTROLLER_COUNT
  37. #define CONFIG_USB_MAX_CONTROLLER_COUNT 1
  38. #endif
  39. static struct descriptor {
  40. struct usb_hub_descriptor hub;
  41. struct usb_device_descriptor device;
  42. struct usb_config_descriptor config;
  43. struct usb_interface_descriptor interface;
  44. struct usb_endpoint_descriptor endpoint;
  45. struct usb_ss_ep_comp_descriptor ep_companion;
  46. } __attribute__ ((packed)) descriptor = {
  47. {
  48. 0xc, /* bDescLength */
  49. 0x2a, /* bDescriptorType: hub descriptor */
  50. 2, /* bNrPorts -- runtime modified */
  51. cpu_to_le16(0x8), /* wHubCharacteristics */
  52. 10, /* bPwrOn2PwrGood */
  53. 0, /* bHubCntrCurrent */
  54. { /* Device removable */
  55. } /* at most 7 ports! XXX */
  56. },
  57. {
  58. 0x12, /* bLength */
  59. 1, /* bDescriptorType: UDESC_DEVICE */
  60. cpu_to_le16(0x0300), /* bcdUSB: v3.0 */
  61. 9, /* bDeviceClass: UDCLASS_HUB */
  62. 0, /* bDeviceSubClass: UDSUBCLASS_HUB */
  63. 3, /* bDeviceProtocol: UDPROTO_SSHUBSTT */
  64. 9, /* bMaxPacketSize: 512 bytes 2^9 */
  65. 0x0000, /* idVendor */
  66. 0x0000, /* idProduct */
  67. cpu_to_le16(0x0100), /* bcdDevice */
  68. 1, /* iManufacturer */
  69. 2, /* iProduct */
  70. 0, /* iSerialNumber */
  71. 1 /* bNumConfigurations: 1 */
  72. },
  73. {
  74. 0x9,
  75. 2, /* bDescriptorType: UDESC_CONFIG */
  76. cpu_to_le16(0x1f), /* includes SS endpoint descriptor */
  77. 1, /* bNumInterface */
  78. 1, /* bConfigurationValue */
  79. 0, /* iConfiguration */
  80. 0x40, /* bmAttributes: UC_SELF_POWER */
  81. 0 /* bMaxPower */
  82. },
  83. {
  84. 0x9, /* bLength */
  85. 4, /* bDescriptorType: UDESC_INTERFACE */
  86. 0, /* bInterfaceNumber */
  87. 0, /* bAlternateSetting */
  88. 1, /* bNumEndpoints */
  89. 9, /* bInterfaceClass: UICLASS_HUB */
  90. 0, /* bInterfaceSubClass: UISUBCLASS_HUB */
  91. 0, /* bInterfaceProtocol: UIPROTO_HSHUBSTT */
  92. 0 /* iInterface */
  93. },
  94. {
  95. 0x7, /* bLength */
  96. 5, /* bDescriptorType: UDESC_ENDPOINT */
  97. 0x81, /* bEndpointAddress: IN endpoint 1 */
  98. 3, /* bmAttributes: UE_INTERRUPT */
  99. 8, /* wMaxPacketSize */
  100. 255 /* bInterval */
  101. },
  102. {
  103. 0x06, /* ss_bLength */
  104. 0x30, /* ss_bDescriptorType: SS EP Companion */
  105. 0x00, /* ss_bMaxBurst: allows 1 TX between ACKs */
  106. /* ss_bmAttributes: 1 packet per service interval */
  107. 0x00,
  108. /* ss_wBytesPerInterval: 15 bits for max 15 ports */
  109. cpu_to_le16(0x02),
  110. },
  111. };
  112. #if !CONFIG_IS_ENABLED(DM_USB)
  113. static struct xhci_ctrl xhcic[CONFIG_USB_MAX_CONTROLLER_COUNT];
  114. #endif
  115. struct xhci_ctrl *xhci_get_ctrl(struct usb_device *udev)
  116. {
  117. #if CONFIG_IS_ENABLED(DM_USB)
  118. struct udevice *dev;
  119. /* Find the USB controller */
  120. for (dev = udev->dev;
  121. device_get_uclass_id(dev) != UCLASS_USB;
  122. dev = dev->parent)
  123. ;
  124. return dev_get_priv(dev);
  125. #else
  126. return udev->controller;
  127. #endif
  128. }
  129. /**
  130. * Waits for as per specified amount of time
  131. * for the "result" to match with "done"
  132. *
  133. * @param ptr pointer to the register to be read
  134. * @param mask mask for the value read
  135. * @param done value to be campared with result
  136. * @param usec time to wait till
  137. * @return 0 if handshake is success else < 0 on failure
  138. */
  139. static int
  140. handshake(uint32_t volatile *ptr, uint32_t mask, uint32_t done, int usec)
  141. {
  142. uint32_t result;
  143. int ret;
  144. ret = readx_poll_sleep_timeout(xhci_readl, ptr, result,
  145. (result & mask) == done || result == U32_MAX,
  146. 1, usec);
  147. if (result == U32_MAX) /* card removed */
  148. return -ENODEV;
  149. return ret;
  150. }
  151. /**
  152. * Set the run bit and wait for the host to be running.
  153. *
  154. * @param hcor pointer to host controller operation registers
  155. * @return status of the Handshake
  156. */
  157. static int xhci_start(struct xhci_hcor *hcor)
  158. {
  159. u32 temp;
  160. int ret;
  161. puts("Starting the controller\n");
  162. temp = xhci_readl(&hcor->or_usbcmd);
  163. temp |= (CMD_RUN);
  164. xhci_writel(&hcor->or_usbcmd, temp);
  165. /*
  166. * Wait for the HCHalted Status bit to be 0 to indicate the host is
  167. * running.
  168. */
  169. ret = handshake(&hcor->or_usbsts, STS_HALT, 0, XHCI_MAX_HALT_USEC);
  170. if (ret)
  171. debug("Host took too long to start, "
  172. "waited %u microseconds.\n",
  173. XHCI_MAX_HALT_USEC);
  174. return ret;
  175. }
  176. #if CONFIG_IS_ENABLED(DM_USB)
  177. /**
  178. * Resets XHCI Hardware
  179. *
  180. * @param ctrl pointer to host controller
  181. * @return 0 if OK, or a negative error code.
  182. */
  183. static int xhci_reset_hw(struct xhci_ctrl *ctrl)
  184. {
  185. int ret;
  186. ret = reset_get_by_index(ctrl->dev, 0, &ctrl->reset);
  187. if (ret && ret != -ENOENT && ret != -ENOTSUPP) {
  188. dev_err(ctrl->dev, "failed to get reset\n");
  189. return ret;
  190. }
  191. if (reset_valid(&ctrl->reset)) {
  192. ret = reset_assert(&ctrl->reset);
  193. if (ret)
  194. return ret;
  195. ret = reset_deassert(&ctrl->reset);
  196. if (ret)
  197. return ret;
  198. }
  199. return 0;
  200. }
  201. #endif
  202. /**
  203. * Resets the XHCI Controller
  204. *
  205. * @param hcor pointer to host controller operation registers
  206. * @return -EBUSY if XHCI Controller is not halted else status of handshake
  207. */
  208. static int xhci_reset(struct xhci_hcor *hcor)
  209. {
  210. u32 cmd;
  211. u32 state;
  212. int ret;
  213. /* Halting the Host first */
  214. debug("// Halt the HC: %p\n", hcor);
  215. state = xhci_readl(&hcor->or_usbsts) & STS_HALT;
  216. if (!state) {
  217. cmd = xhci_readl(&hcor->or_usbcmd);
  218. cmd &= ~CMD_RUN;
  219. xhci_writel(&hcor->or_usbcmd, cmd);
  220. }
  221. ret = handshake(&hcor->or_usbsts,
  222. STS_HALT, STS_HALT, XHCI_MAX_HALT_USEC);
  223. if (ret) {
  224. printf("Host not halted after %u microseconds.\n",
  225. XHCI_MAX_HALT_USEC);
  226. return -EBUSY;
  227. }
  228. debug("// Reset the HC\n");
  229. cmd = xhci_readl(&hcor->or_usbcmd);
  230. cmd |= CMD_RESET;
  231. xhci_writel(&hcor->or_usbcmd, cmd);
  232. ret = handshake(&hcor->or_usbcmd, CMD_RESET, 0, XHCI_MAX_RESET_USEC);
  233. if (ret)
  234. return ret;
  235. /*
  236. * xHCI cannot write to any doorbells or operational registers other
  237. * than status until the "Controller Not Ready" flag is cleared.
  238. */
  239. return handshake(&hcor->or_usbsts, STS_CNR, 0, XHCI_MAX_RESET_USEC);
  240. }
  241. /**
  242. * Used for passing endpoint bitmasks between the core and HCDs.
  243. * Find the index for an endpoint given its descriptor.
  244. * Use the return value to right shift 1 for the bitmask.
  245. *
  246. * Index = (epnum * 2) + direction - 1,
  247. * where direction = 0 for OUT, 1 for IN.
  248. * For control endpoints, the IN index is used (OUT index is unused), so
  249. * index = (epnum * 2) + direction - 1 = (epnum * 2) + 1 - 1 = (epnum * 2)
  250. *
  251. * @param desc USB enpdoint Descriptor
  252. * @return index of the Endpoint
  253. */
  254. static unsigned int xhci_get_ep_index(struct usb_endpoint_descriptor *desc)
  255. {
  256. unsigned int index;
  257. if (usb_endpoint_xfer_control(desc))
  258. index = (unsigned int)(usb_endpoint_num(desc) * 2);
  259. else
  260. index = (unsigned int)((usb_endpoint_num(desc) * 2) -
  261. (usb_endpoint_dir_in(desc) ? 0 : 1));
  262. return index;
  263. }
  264. /*
  265. * Convert bInterval expressed in microframes (in 1-255 range) to exponent of
  266. * microframes, rounded down to nearest power of 2.
  267. */
  268. static unsigned int xhci_microframes_to_exponent(unsigned int desc_interval,
  269. unsigned int min_exponent,
  270. unsigned int max_exponent)
  271. {
  272. unsigned int interval;
  273. interval = fls(desc_interval) - 1;
  274. interval = clamp_val(interval, min_exponent, max_exponent);
  275. if ((1 << interval) != desc_interval)
  276. debug("rounding interval to %d microframes, "\
  277. "ep desc says %d microframes\n",
  278. 1 << interval, desc_interval);
  279. return interval;
  280. }
  281. static unsigned int xhci_parse_microframe_interval(struct usb_device *udev,
  282. struct usb_endpoint_descriptor *endpt_desc)
  283. {
  284. if (endpt_desc->bInterval == 0)
  285. return 0;
  286. return xhci_microframes_to_exponent(endpt_desc->bInterval, 0, 15);
  287. }
  288. static unsigned int xhci_parse_frame_interval(struct usb_device *udev,
  289. struct usb_endpoint_descriptor *endpt_desc)
  290. {
  291. return xhci_microframes_to_exponent(endpt_desc->bInterval * 8, 3, 10);
  292. }
  293. /*
  294. * Convert interval expressed as 2^(bInterval - 1) == interval into
  295. * straight exponent value 2^n == interval.
  296. */
  297. static unsigned int xhci_parse_exponent_interval(struct usb_device *udev,
  298. struct usb_endpoint_descriptor *endpt_desc)
  299. {
  300. unsigned int interval;
  301. interval = clamp_val(endpt_desc->bInterval, 1, 16) - 1;
  302. if (interval != endpt_desc->bInterval - 1)
  303. debug("ep %#x - rounding interval to %d %sframes\n",
  304. endpt_desc->bEndpointAddress, 1 << interval,
  305. udev->speed == USB_SPEED_FULL ? "" : "micro");
  306. if (udev->speed == USB_SPEED_FULL) {
  307. /*
  308. * Full speed isoc endpoints specify interval in frames,
  309. * not microframes. We are using microframes everywhere,
  310. * so adjust accordingly.
  311. */
  312. interval += 3; /* 1 frame = 2^3 uframes */
  313. }
  314. return interval;
  315. }
  316. /*
  317. * Return the polling or NAK interval.
  318. *
  319. * The polling interval is expressed in "microframes". If xHCI's Interval field
  320. * is set to N, it will service the endpoint every 2^(Interval)*125us.
  321. *
  322. * The NAK interval is one NAK per 1 to 255 microframes, or no NAKs if interval
  323. * is set to 0.
  324. */
  325. static unsigned int xhci_get_endpoint_interval(struct usb_device *udev,
  326. struct usb_endpoint_descriptor *endpt_desc)
  327. {
  328. unsigned int interval = 0;
  329. switch (udev->speed) {
  330. case USB_SPEED_HIGH:
  331. /* Max NAK rate */
  332. if (usb_endpoint_xfer_control(endpt_desc) ||
  333. usb_endpoint_xfer_bulk(endpt_desc)) {
  334. interval = xhci_parse_microframe_interval(udev,
  335. endpt_desc);
  336. break;
  337. }
  338. /* Fall through - SS and HS isoc/int have same decoding */
  339. case USB_SPEED_SUPER:
  340. if (usb_endpoint_xfer_int(endpt_desc) ||
  341. usb_endpoint_xfer_isoc(endpt_desc)) {
  342. interval = xhci_parse_exponent_interval(udev,
  343. endpt_desc);
  344. }
  345. break;
  346. case USB_SPEED_FULL:
  347. if (usb_endpoint_xfer_isoc(endpt_desc)) {
  348. interval = xhci_parse_exponent_interval(udev,
  349. endpt_desc);
  350. break;
  351. }
  352. /*
  353. * Fall through for interrupt endpoint interval decoding
  354. * since it uses the same rules as low speed interrupt
  355. * endpoints.
  356. */
  357. case USB_SPEED_LOW:
  358. if (usb_endpoint_xfer_int(endpt_desc) ||
  359. usb_endpoint_xfer_isoc(endpt_desc)) {
  360. interval = xhci_parse_frame_interval(udev, endpt_desc);
  361. }
  362. break;
  363. default:
  364. BUG();
  365. }
  366. return interval;
  367. }
  368. /*
  369. * The "Mult" field in the endpoint context is only set for SuperSpeed isoc eps.
  370. * High speed endpoint descriptors can define "the number of additional
  371. * transaction opportunities per microframe", but that goes in the Max Burst
  372. * endpoint context field.
  373. */
  374. static u32 xhci_get_endpoint_mult(struct usb_device *udev,
  375. struct usb_endpoint_descriptor *endpt_desc,
  376. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  377. {
  378. if (udev->speed < USB_SPEED_SUPER ||
  379. !usb_endpoint_xfer_isoc(endpt_desc))
  380. return 0;
  381. return ss_ep_comp_desc->bmAttributes;
  382. }
  383. static u32 xhci_get_endpoint_max_burst(struct usb_device *udev,
  384. struct usb_endpoint_descriptor *endpt_desc,
  385. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  386. {
  387. /* Super speed and Plus have max burst in ep companion desc */
  388. if (udev->speed >= USB_SPEED_SUPER)
  389. return ss_ep_comp_desc->bMaxBurst;
  390. if (udev->speed == USB_SPEED_HIGH &&
  391. (usb_endpoint_xfer_isoc(endpt_desc) ||
  392. usb_endpoint_xfer_int(endpt_desc)))
  393. return usb_endpoint_maxp_mult(endpt_desc) - 1;
  394. return 0;
  395. }
  396. /*
  397. * Return the maximum endpoint service interval time (ESIT) payload.
  398. * Basically, this is the maxpacket size, multiplied by the burst size
  399. * and mult size.
  400. */
  401. static u32 xhci_get_max_esit_payload(struct usb_device *udev,
  402. struct usb_endpoint_descriptor *endpt_desc,
  403. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc)
  404. {
  405. int max_burst;
  406. int max_packet;
  407. /* Only applies for interrupt or isochronous endpoints */
  408. if (usb_endpoint_xfer_control(endpt_desc) ||
  409. usb_endpoint_xfer_bulk(endpt_desc))
  410. return 0;
  411. /* SuperSpeed Isoc ep with less than 48k per esit */
  412. if (udev->speed >= USB_SPEED_SUPER)
  413. return le16_to_cpu(ss_ep_comp_desc->wBytesPerInterval);
  414. max_packet = usb_endpoint_maxp(endpt_desc);
  415. max_burst = usb_endpoint_maxp_mult(endpt_desc);
  416. /* A 0 in max burst means 1 transfer per ESIT */
  417. return max_packet * max_burst;
  418. }
  419. /**
  420. * Issue a configure endpoint command or evaluate context command
  421. * and wait for it to finish.
  422. *
  423. * @param udev pointer to the Device Data Structure
  424. * @param ctx_change flag to indicate the Context has changed or NOT
  425. * @return 0 on success, -1 on failure
  426. */
  427. static int xhci_configure_endpoints(struct usb_device *udev, bool ctx_change)
  428. {
  429. struct xhci_container_ctx *in_ctx;
  430. struct xhci_virt_device *virt_dev;
  431. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  432. union xhci_trb *event;
  433. virt_dev = ctrl->devs[udev->slot_id];
  434. in_ctx = virt_dev->in_ctx;
  435. xhci_flush_cache((uintptr_t)in_ctx->bytes, in_ctx->size);
  436. xhci_queue_command(ctrl, in_ctx->bytes, udev->slot_id, 0,
  437. ctx_change ? TRB_EVAL_CONTEXT : TRB_CONFIG_EP);
  438. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  439. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags))
  440. != udev->slot_id);
  441. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  442. case COMP_SUCCESS:
  443. debug("Successful %s command\n",
  444. ctx_change ? "Evaluate Context" : "Configure Endpoint");
  445. break;
  446. default:
  447. printf("ERROR: %s command returned completion code %d.\n",
  448. ctx_change ? "Evaluate Context" : "Configure Endpoint",
  449. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  450. return -EINVAL;
  451. }
  452. xhci_acknowledge_event(ctrl);
  453. return 0;
  454. }
  455. /**
  456. * Configure the endpoint, programming the device contexts.
  457. *
  458. * @param udev pointer to the USB device structure
  459. * @return returns the status of the xhci_configure_endpoints
  460. */
  461. static int xhci_set_configuration(struct usb_device *udev)
  462. {
  463. struct xhci_container_ctx *in_ctx;
  464. struct xhci_container_ctx *out_ctx;
  465. struct xhci_input_control_ctx *ctrl_ctx;
  466. struct xhci_slot_ctx *slot_ctx;
  467. struct xhci_ep_ctx *ep_ctx[MAX_EP_CTX_NUM];
  468. int cur_ep;
  469. int max_ep_flag = 0;
  470. int ep_index;
  471. unsigned int dir;
  472. unsigned int ep_type;
  473. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  474. int num_of_ep;
  475. int ep_flag = 0;
  476. u64 trb_64 = 0;
  477. int slot_id = udev->slot_id;
  478. struct xhci_virt_device *virt_dev = ctrl->devs[slot_id];
  479. struct usb_interface *ifdesc;
  480. u32 max_esit_payload;
  481. unsigned int interval;
  482. unsigned int mult;
  483. unsigned int max_burst;
  484. unsigned int avg_trb_len;
  485. unsigned int err_count = 0;
  486. out_ctx = virt_dev->out_ctx;
  487. in_ctx = virt_dev->in_ctx;
  488. num_of_ep = udev->config.if_desc[0].no_of_ep;
  489. ifdesc = &udev->config.if_desc[0];
  490. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  491. /* Initialize the input context control */
  492. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  493. ctrl_ctx->drop_flags = 0;
  494. /* EP_FLAG gives values 1 & 4 for EP1OUT and EP2IN */
  495. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  496. ep_flag = xhci_get_ep_index(&ifdesc->ep_desc[cur_ep]);
  497. ctrl_ctx->add_flags |= cpu_to_le32(1 << (ep_flag + 1));
  498. if (max_ep_flag < ep_flag)
  499. max_ep_flag = ep_flag;
  500. }
  501. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  502. /* slot context */
  503. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  504. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  505. slot_ctx->dev_info &= ~(cpu_to_le32(LAST_CTX_MASK));
  506. slot_ctx->dev_info |= cpu_to_le32(LAST_CTX(max_ep_flag + 1) | 0);
  507. xhci_endpoint_copy(ctrl, in_ctx, out_ctx, 0);
  508. /* filling up ep contexts */
  509. for (cur_ep = 0; cur_ep < num_of_ep; cur_ep++) {
  510. struct usb_endpoint_descriptor *endpt_desc = NULL;
  511. struct usb_ss_ep_comp_descriptor *ss_ep_comp_desc = NULL;
  512. endpt_desc = &ifdesc->ep_desc[cur_ep];
  513. ss_ep_comp_desc = &ifdesc->ss_ep_comp_desc[cur_ep];
  514. trb_64 = 0;
  515. /*
  516. * Get values to fill the endpoint context, mostly from ep
  517. * descriptor. The average TRB buffer lengt for bulk endpoints
  518. * is unclear as we have no clue on scatter gather list entry
  519. * size. For Isoc and Int, set it to max available.
  520. * See xHCI 1.1 spec 4.14.1.1 for details.
  521. */
  522. max_esit_payload = xhci_get_max_esit_payload(udev, endpt_desc,
  523. ss_ep_comp_desc);
  524. interval = xhci_get_endpoint_interval(udev, endpt_desc);
  525. mult = xhci_get_endpoint_mult(udev, endpt_desc,
  526. ss_ep_comp_desc);
  527. max_burst = xhci_get_endpoint_max_burst(udev, endpt_desc,
  528. ss_ep_comp_desc);
  529. avg_trb_len = max_esit_payload;
  530. ep_index = xhci_get_ep_index(endpt_desc);
  531. ep_ctx[ep_index] = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  532. /* Allocate the ep rings */
  533. virt_dev->eps[ep_index].ring = xhci_ring_alloc(1, true);
  534. if (!virt_dev->eps[ep_index].ring)
  535. return -ENOMEM;
  536. /*NOTE: ep_desc[0] actually represents EP1 and so on */
  537. dir = (((endpt_desc->bEndpointAddress) & (0x80)) >> 7);
  538. ep_type = (((endpt_desc->bmAttributes) & (0x3)) | (dir << 2));
  539. ep_ctx[ep_index]->ep_info =
  540. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_HI(max_esit_payload) |
  541. EP_INTERVAL(interval) | EP_MULT(mult));
  542. ep_ctx[ep_index]->ep_info2 = cpu_to_le32(EP_TYPE(ep_type));
  543. ep_ctx[ep_index]->ep_info2 |=
  544. cpu_to_le32(MAX_PACKET
  545. (get_unaligned(&endpt_desc->wMaxPacketSize)));
  546. /* Allow 3 retries for everything but isoc, set CErr = 3 */
  547. if (!usb_endpoint_xfer_isoc(endpt_desc))
  548. err_count = 3;
  549. ep_ctx[ep_index]->ep_info2 |=
  550. cpu_to_le32(MAX_BURST(max_burst) |
  551. ERROR_COUNT(err_count));
  552. trb_64 = virt_to_phys(virt_dev->eps[ep_index].ring->enqueue);
  553. ep_ctx[ep_index]->deq = cpu_to_le64(trb_64 |
  554. virt_dev->eps[ep_index].ring->cycle_state);
  555. /*
  556. * xHCI spec 6.2.3:
  557. * 'Average TRB Length' should be 8 for control endpoints.
  558. */
  559. if (usb_endpoint_xfer_control(endpt_desc))
  560. avg_trb_len = 8;
  561. ep_ctx[ep_index]->tx_info =
  562. cpu_to_le32(EP_MAX_ESIT_PAYLOAD_LO(max_esit_payload) |
  563. EP_AVG_TRB_LENGTH(avg_trb_len));
  564. /*
  565. * The MediaTek xHCI defines some extra SW parameters which
  566. * are put into reserved DWs in Slot and Endpoint Contexts
  567. * for synchronous endpoints.
  568. */
  569. if (ctrl->quirks & XHCI_MTK_HOST) {
  570. ep_ctx[ep_index]->reserved[0] =
  571. cpu_to_le32(EP_BPKTS(1) | EP_BBM(1));
  572. }
  573. }
  574. return xhci_configure_endpoints(udev, false);
  575. }
  576. /**
  577. * Issue an Address Device command (which will issue a SetAddress request to
  578. * the device).
  579. *
  580. * @param udev pointer to the Device Data Structure
  581. * @return 0 if successful else error code on failure
  582. */
  583. static int xhci_address_device(struct usb_device *udev, int root_portnr)
  584. {
  585. int ret = 0;
  586. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  587. struct xhci_slot_ctx *slot_ctx;
  588. struct xhci_input_control_ctx *ctrl_ctx;
  589. struct xhci_virt_device *virt_dev;
  590. int slot_id = udev->slot_id;
  591. union xhci_trb *event;
  592. virt_dev = ctrl->devs[slot_id];
  593. /*
  594. * This is the first Set Address since device plug-in
  595. * so setting up the slot context.
  596. */
  597. debug("Setting up addressable devices %p\n", ctrl->dcbaa);
  598. xhci_setup_addressable_virt_dev(ctrl, udev, root_portnr);
  599. ctrl_ctx = xhci_get_input_control_ctx(virt_dev->in_ctx);
  600. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG | EP0_FLAG);
  601. ctrl_ctx->drop_flags = 0;
  602. xhci_queue_command(ctrl, (void *)ctrl_ctx, slot_id, 0, TRB_ADDR_DEV);
  603. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  604. BUG_ON(TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags)) != slot_id);
  605. switch (GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))) {
  606. case COMP_CTX_STATE:
  607. case COMP_EBADSLT:
  608. printf("Setup ERROR: address device command for slot %d.\n",
  609. slot_id);
  610. ret = -EINVAL;
  611. break;
  612. case COMP_TX_ERR:
  613. puts("Device not responding to set address.\n");
  614. ret = -EPROTO;
  615. break;
  616. case COMP_DEV_ERR:
  617. puts("ERROR: Incompatible device"
  618. "for address device command.\n");
  619. ret = -ENODEV;
  620. break;
  621. case COMP_SUCCESS:
  622. debug("Successful Address Device command\n");
  623. udev->status = 0;
  624. break;
  625. default:
  626. printf("ERROR: unexpected command completion code 0x%x.\n",
  627. GET_COMP_CODE(le32_to_cpu(event->event_cmd.status)));
  628. ret = -EINVAL;
  629. break;
  630. }
  631. xhci_acknowledge_event(ctrl);
  632. if (ret < 0)
  633. /*
  634. * TODO: Unsuccessful Address Device command shall leave the
  635. * slot in default state. So, issue Disable Slot command now.
  636. */
  637. return ret;
  638. xhci_inval_cache((uintptr_t)virt_dev->out_ctx->bytes,
  639. virt_dev->out_ctx->size);
  640. slot_ctx = xhci_get_slot_ctx(ctrl, virt_dev->out_ctx);
  641. debug("xHC internal address is: %d\n",
  642. le32_to_cpu(slot_ctx->dev_state) & DEV_ADDR_MASK);
  643. return 0;
  644. }
  645. /**
  646. * Issue Enable slot command to the controller to allocate
  647. * device slot and assign the slot id. It fails if the xHC
  648. * ran out of device slots, the Enable Slot command timed out,
  649. * or allocating memory failed.
  650. *
  651. * @param udev pointer to the Device Data Structure
  652. * @return Returns 0 on succes else return error code on failure
  653. */
  654. static int _xhci_alloc_device(struct usb_device *udev)
  655. {
  656. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  657. union xhci_trb *event;
  658. int ret;
  659. /*
  660. * Root hub will be first device to be initailized.
  661. * If this device is root-hub, don't do any xHC related
  662. * stuff.
  663. */
  664. if (ctrl->rootdev == 0) {
  665. udev->speed = USB_SPEED_SUPER;
  666. return 0;
  667. }
  668. xhci_queue_command(ctrl, NULL, 0, 0, TRB_ENABLE_SLOT);
  669. event = xhci_wait_for_event(ctrl, TRB_COMPLETION);
  670. BUG_ON(GET_COMP_CODE(le32_to_cpu(event->event_cmd.status))
  671. != COMP_SUCCESS);
  672. udev->slot_id = TRB_TO_SLOT_ID(le32_to_cpu(event->event_cmd.flags));
  673. xhci_acknowledge_event(ctrl);
  674. ret = xhci_alloc_virt_device(ctrl, udev->slot_id);
  675. if (ret < 0) {
  676. /*
  677. * TODO: Unsuccessful Address Device command shall leave
  678. * the slot in default. So, issue Disable Slot command now.
  679. */
  680. puts("Could not allocate xHCI USB device data structures\n");
  681. return ret;
  682. }
  683. return 0;
  684. }
  685. #if !CONFIG_IS_ENABLED(DM_USB)
  686. int usb_alloc_device(struct usb_device *udev)
  687. {
  688. return _xhci_alloc_device(udev);
  689. }
  690. #endif
  691. /*
  692. * Full speed devices may have a max packet size greater than 8 bytes, but the
  693. * USB core doesn't know that until it reads the first 8 bytes of the
  694. * descriptor. If the usb_device's max packet size changes after that point,
  695. * we need to issue an evaluate context command and wait on it.
  696. *
  697. * @param udev pointer to the Device Data Structure
  698. * @return returns the status of the xhci_configure_endpoints
  699. */
  700. int xhci_check_maxpacket(struct usb_device *udev)
  701. {
  702. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  703. unsigned int slot_id = udev->slot_id;
  704. int ep_index = 0; /* control endpoint */
  705. struct xhci_container_ctx *in_ctx;
  706. struct xhci_container_ctx *out_ctx;
  707. struct xhci_input_control_ctx *ctrl_ctx;
  708. struct xhci_ep_ctx *ep_ctx;
  709. int max_packet_size;
  710. int hw_max_packet_size;
  711. int ret = 0;
  712. out_ctx = ctrl->devs[slot_id]->out_ctx;
  713. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  714. ep_ctx = xhci_get_ep_ctx(ctrl, out_ctx, ep_index);
  715. hw_max_packet_size = MAX_PACKET_DECODED(le32_to_cpu(ep_ctx->ep_info2));
  716. max_packet_size = udev->epmaxpacketin[0];
  717. if (hw_max_packet_size != max_packet_size) {
  718. debug("Max Packet Size for ep 0 changed.\n");
  719. debug("Max packet size in usb_device = %d\n", max_packet_size);
  720. debug("Max packet size in xHCI HW = %d\n", hw_max_packet_size);
  721. debug("Issuing evaluate context command.\n");
  722. /* Set up the modified control endpoint 0 */
  723. xhci_endpoint_copy(ctrl, ctrl->devs[slot_id]->in_ctx,
  724. ctrl->devs[slot_id]->out_ctx, ep_index);
  725. in_ctx = ctrl->devs[slot_id]->in_ctx;
  726. ep_ctx = xhci_get_ep_ctx(ctrl, in_ctx, ep_index);
  727. ep_ctx->ep_info2 &= cpu_to_le32(~MAX_PACKET(MAX_PACKET_MASK));
  728. ep_ctx->ep_info2 |= cpu_to_le32(MAX_PACKET(max_packet_size));
  729. /*
  730. * Set up the input context flags for the command
  731. * FIXME: This won't work if a non-default control endpoint
  732. * changes max packet sizes.
  733. */
  734. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  735. ctrl_ctx->add_flags = cpu_to_le32(EP0_FLAG);
  736. ctrl_ctx->drop_flags = 0;
  737. ret = xhci_configure_endpoints(udev, true);
  738. }
  739. return ret;
  740. }
  741. /**
  742. * Clears the Change bits of the Port Status Register
  743. *
  744. * @param wValue request value
  745. * @param wIndex request index
  746. * @param addr address of posrt status register
  747. * @param port_status state of port status register
  748. * @return none
  749. */
  750. static void xhci_clear_port_change_bit(u16 wValue,
  751. u16 wIndex, volatile uint32_t *addr, u32 port_status)
  752. {
  753. char *port_change_bit;
  754. u32 status;
  755. switch (wValue) {
  756. case USB_PORT_FEAT_C_RESET:
  757. status = PORT_RC;
  758. port_change_bit = "reset";
  759. break;
  760. case USB_PORT_FEAT_C_CONNECTION:
  761. status = PORT_CSC;
  762. port_change_bit = "connect";
  763. break;
  764. case USB_PORT_FEAT_C_OVER_CURRENT:
  765. status = PORT_OCC;
  766. port_change_bit = "over-current";
  767. break;
  768. case USB_PORT_FEAT_C_ENABLE:
  769. status = PORT_PEC;
  770. port_change_bit = "enable/disable";
  771. break;
  772. case USB_PORT_FEAT_C_SUSPEND:
  773. status = PORT_PLC;
  774. port_change_bit = "suspend/resume";
  775. break;
  776. default:
  777. /* Should never happen */
  778. return;
  779. }
  780. /* Change bits are all write 1 to clear */
  781. xhci_writel(addr, port_status | status);
  782. port_status = xhci_readl(addr);
  783. debug("clear port %s change, actual port %d status = 0x%x\n",
  784. port_change_bit, wIndex, port_status);
  785. }
  786. /**
  787. * Save Read Only (RO) bits and save read/write bits where
  788. * writing a 0 clears the bit and writing a 1 sets the bit (RWS).
  789. * For all other types (RW1S, RW1CS, RW, and RZ), writing a '0' has no effect.
  790. *
  791. * @param state state of the Port Status and Control Regsiter
  792. * @return a value that would result in the port being in the
  793. * same state, if the value was written to the port
  794. * status control register.
  795. */
  796. static u32 xhci_port_state_to_neutral(u32 state)
  797. {
  798. /* Save read-only status and port state */
  799. return (state & XHCI_PORT_RO) | (state & XHCI_PORT_RWS);
  800. }
  801. /**
  802. * Submits the Requests to the XHCI Host Controller
  803. *
  804. * @param udev pointer to the USB device structure
  805. * @param pipe contains the DIR_IN or OUT , devnum
  806. * @param buffer buffer to be read/written based on the request
  807. * @return returns 0 if successful else -1 on failure
  808. */
  809. static int xhci_submit_root(struct usb_device *udev, unsigned long pipe,
  810. void *buffer, struct devrequest *req)
  811. {
  812. uint8_t tmpbuf[4];
  813. u16 typeReq;
  814. void *srcptr = NULL;
  815. int len, srclen;
  816. uint32_t reg;
  817. volatile uint32_t *status_reg;
  818. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  819. struct xhci_hccr *hccr = ctrl->hccr;
  820. struct xhci_hcor *hcor = ctrl->hcor;
  821. int max_ports = HCS_MAX_PORTS(xhci_readl(&hccr->cr_hcsparams1));
  822. if ((req->requesttype & USB_RT_PORT) &&
  823. le16_to_cpu(req->index) > max_ports) {
  824. printf("The request port(%d) exceeds maximum port number\n",
  825. le16_to_cpu(req->index) - 1);
  826. return -EINVAL;
  827. }
  828. status_reg = (volatile uint32_t *)
  829. (&hcor->portregs[le16_to_cpu(req->index) - 1].or_portsc);
  830. srclen = 0;
  831. typeReq = req->request | req->requesttype << 8;
  832. switch (typeReq) {
  833. case DeviceRequest | USB_REQ_GET_DESCRIPTOR:
  834. switch (le16_to_cpu(req->value) >> 8) {
  835. case USB_DT_DEVICE:
  836. debug("USB_DT_DEVICE request\n");
  837. srcptr = &descriptor.device;
  838. srclen = 0x12;
  839. break;
  840. case USB_DT_CONFIG:
  841. debug("USB_DT_CONFIG config\n");
  842. srcptr = &descriptor.config;
  843. srclen = 0x19;
  844. break;
  845. case USB_DT_STRING:
  846. debug("USB_DT_STRING config\n");
  847. switch (le16_to_cpu(req->value) & 0xff) {
  848. case 0: /* Language */
  849. srcptr = "\4\3\11\4";
  850. srclen = 4;
  851. break;
  852. case 1: /* Vendor String */
  853. srcptr = "\16\3U\0-\0B\0o\0o\0t\0";
  854. srclen = 14;
  855. break;
  856. case 2: /* Product Name */
  857. srcptr = "\52\3X\0H\0C\0I\0 "
  858. "\0H\0o\0s\0t\0 "
  859. "\0C\0o\0n\0t\0r\0o\0l\0l\0e\0r\0";
  860. srclen = 42;
  861. break;
  862. default:
  863. printf("unknown value DT_STRING %x\n",
  864. le16_to_cpu(req->value));
  865. goto unknown;
  866. }
  867. break;
  868. default:
  869. printf("unknown value %x\n", le16_to_cpu(req->value));
  870. goto unknown;
  871. }
  872. break;
  873. case USB_REQ_GET_DESCRIPTOR | ((USB_DIR_IN | USB_RT_HUB) << 8):
  874. switch (le16_to_cpu(req->value) >> 8) {
  875. case USB_DT_HUB:
  876. case USB_DT_SS_HUB:
  877. debug("USB_DT_HUB config\n");
  878. srcptr = &descriptor.hub;
  879. srclen = 0x8;
  880. break;
  881. default:
  882. printf("unknown value %x\n", le16_to_cpu(req->value));
  883. goto unknown;
  884. }
  885. break;
  886. case USB_REQ_SET_ADDRESS | (USB_RECIP_DEVICE << 8):
  887. debug("USB_REQ_SET_ADDRESS\n");
  888. ctrl->rootdev = le16_to_cpu(req->value);
  889. break;
  890. case DeviceOutRequest | USB_REQ_SET_CONFIGURATION:
  891. /* Do nothing */
  892. break;
  893. case USB_REQ_GET_STATUS | ((USB_DIR_IN | USB_RT_HUB) << 8):
  894. tmpbuf[0] = 1; /* USB_STATUS_SELFPOWERED */
  895. tmpbuf[1] = 0;
  896. srcptr = tmpbuf;
  897. srclen = 2;
  898. break;
  899. case USB_REQ_GET_STATUS | ((USB_RT_PORT | USB_DIR_IN) << 8):
  900. memset(tmpbuf, 0, 4);
  901. reg = xhci_readl(status_reg);
  902. if (reg & PORT_CONNECT) {
  903. tmpbuf[0] |= USB_PORT_STAT_CONNECTION;
  904. switch (reg & DEV_SPEED_MASK) {
  905. case XDEV_FS:
  906. debug("SPEED = FULLSPEED\n");
  907. break;
  908. case XDEV_LS:
  909. debug("SPEED = LOWSPEED\n");
  910. tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8;
  911. break;
  912. case XDEV_HS:
  913. debug("SPEED = HIGHSPEED\n");
  914. tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8;
  915. break;
  916. case XDEV_SS:
  917. debug("SPEED = SUPERSPEED\n");
  918. tmpbuf[1] |= USB_PORT_STAT_SUPER_SPEED >> 8;
  919. break;
  920. }
  921. }
  922. if (reg & PORT_PE)
  923. tmpbuf[0] |= USB_PORT_STAT_ENABLE;
  924. if ((reg & PORT_PLS_MASK) == XDEV_U3)
  925. tmpbuf[0] |= USB_PORT_STAT_SUSPEND;
  926. if (reg & PORT_OC)
  927. tmpbuf[0] |= USB_PORT_STAT_OVERCURRENT;
  928. if (reg & PORT_RESET)
  929. tmpbuf[0] |= USB_PORT_STAT_RESET;
  930. if (reg & PORT_POWER)
  931. /*
  932. * XXX: This Port power bit (for USB 3.0 hub)
  933. * we are faking in USB 2.0 hub port status;
  934. * since there's a change in bit positions in
  935. * two:
  936. * USB 2.0 port status PP is at position[8]
  937. * USB 3.0 port status PP is at position[9]
  938. * So, we are still keeping it at position [8]
  939. */
  940. tmpbuf[1] |= USB_PORT_STAT_POWER >> 8;
  941. if (reg & PORT_CSC)
  942. tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION;
  943. if (reg & PORT_PEC)
  944. tmpbuf[2] |= USB_PORT_STAT_C_ENABLE;
  945. if (reg & PORT_OCC)
  946. tmpbuf[2] |= USB_PORT_STAT_C_OVERCURRENT;
  947. if (reg & PORT_RC)
  948. tmpbuf[2] |= USB_PORT_STAT_C_RESET;
  949. srcptr = tmpbuf;
  950. srclen = 4;
  951. break;
  952. case USB_REQ_SET_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  953. reg = xhci_readl(status_reg);
  954. reg = xhci_port_state_to_neutral(reg);
  955. switch (le16_to_cpu(req->value)) {
  956. case USB_PORT_FEAT_ENABLE:
  957. reg |= PORT_PE;
  958. xhci_writel(status_reg, reg);
  959. break;
  960. case USB_PORT_FEAT_POWER:
  961. reg |= PORT_POWER;
  962. xhci_writel(status_reg, reg);
  963. break;
  964. case USB_PORT_FEAT_RESET:
  965. reg |= PORT_RESET;
  966. xhci_writel(status_reg, reg);
  967. break;
  968. default:
  969. printf("unknown feature %x\n", le16_to_cpu(req->value));
  970. goto unknown;
  971. }
  972. break;
  973. case USB_REQ_CLEAR_FEATURE | ((USB_DIR_OUT | USB_RT_PORT) << 8):
  974. reg = xhci_readl(status_reg);
  975. reg = xhci_port_state_to_neutral(reg);
  976. switch (le16_to_cpu(req->value)) {
  977. case USB_PORT_FEAT_ENABLE:
  978. reg &= ~PORT_PE;
  979. break;
  980. case USB_PORT_FEAT_POWER:
  981. reg &= ~PORT_POWER;
  982. break;
  983. case USB_PORT_FEAT_C_RESET:
  984. case USB_PORT_FEAT_C_CONNECTION:
  985. case USB_PORT_FEAT_C_OVER_CURRENT:
  986. case USB_PORT_FEAT_C_ENABLE:
  987. xhci_clear_port_change_bit((le16_to_cpu(req->value)),
  988. le16_to_cpu(req->index),
  989. status_reg, reg);
  990. break;
  991. default:
  992. printf("unknown feature %x\n", le16_to_cpu(req->value));
  993. goto unknown;
  994. }
  995. xhci_writel(status_reg, reg);
  996. break;
  997. default:
  998. puts("Unknown request\n");
  999. goto unknown;
  1000. }
  1001. debug("scrlen = %d\n req->length = %d\n",
  1002. srclen, le16_to_cpu(req->length));
  1003. len = min(srclen, (int)le16_to_cpu(req->length));
  1004. if (srcptr != NULL && len > 0)
  1005. memcpy(buffer, srcptr, len);
  1006. else
  1007. debug("Len is 0\n");
  1008. udev->act_len = len;
  1009. udev->status = 0;
  1010. return 0;
  1011. unknown:
  1012. udev->act_len = 0;
  1013. udev->status = USB_ST_STALLED;
  1014. return -ENODEV;
  1015. }
  1016. /**
  1017. * Submits the INT request to XHCI Host cotroller
  1018. *
  1019. * @param udev pointer to the USB device
  1020. * @param pipe contains the DIR_IN or OUT , devnum
  1021. * @param buffer buffer to be read/written based on the request
  1022. * @param length length of the buffer
  1023. * @param interval interval of the interrupt
  1024. * @return 0
  1025. */
  1026. static int _xhci_submit_int_msg(struct usb_device *udev, unsigned long pipe,
  1027. void *buffer, int length, int interval,
  1028. bool nonblock)
  1029. {
  1030. if (usb_pipetype(pipe) != PIPE_INTERRUPT) {
  1031. printf("non-interrupt pipe (type=%lu)", usb_pipetype(pipe));
  1032. return -EINVAL;
  1033. }
  1034. /*
  1035. * xHCI uses normal TRBs for both bulk and interrupt. When the
  1036. * interrupt endpoint is to be serviced, the xHC will consume
  1037. * (at most) one TD. A TD (comprised of sg list entries) can
  1038. * take several service intervals to transmit.
  1039. */
  1040. return xhci_bulk_tx(udev, pipe, length, buffer);
  1041. }
  1042. /**
  1043. * submit the BULK type of request to the USB Device
  1044. *
  1045. * @param udev pointer to the USB device
  1046. * @param pipe contains the DIR_IN or OUT , devnum
  1047. * @param buffer buffer to be read/written based on the request
  1048. * @param length length of the buffer
  1049. * @return returns 0 if successful else -1 on failure
  1050. */
  1051. static int _xhci_submit_bulk_msg(struct usb_device *udev, unsigned long pipe,
  1052. void *buffer, int length)
  1053. {
  1054. if (usb_pipetype(pipe) != PIPE_BULK) {
  1055. printf("non-bulk pipe (type=%lu)", usb_pipetype(pipe));
  1056. return -EINVAL;
  1057. }
  1058. return xhci_bulk_tx(udev, pipe, length, buffer);
  1059. }
  1060. /**
  1061. * submit the control type of request to the Root hub/Device based on the devnum
  1062. *
  1063. * @param udev pointer to the USB device
  1064. * @param pipe contains the DIR_IN or OUT , devnum
  1065. * @param buffer buffer to be read/written based on the request
  1066. * @param length length of the buffer
  1067. * @param setup Request type
  1068. * @param root_portnr Root port number that this device is on
  1069. * @return returns 0 if successful else -1 on failure
  1070. */
  1071. static int _xhci_submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1072. void *buffer, int length,
  1073. struct devrequest *setup, int root_portnr)
  1074. {
  1075. struct xhci_ctrl *ctrl = xhci_get_ctrl(udev);
  1076. int ret = 0;
  1077. if (usb_pipetype(pipe) != PIPE_CONTROL) {
  1078. printf("non-control pipe (type=%lu)", usb_pipetype(pipe));
  1079. return -EINVAL;
  1080. }
  1081. if (usb_pipedevice(pipe) == ctrl->rootdev)
  1082. return xhci_submit_root(udev, pipe, buffer, setup);
  1083. if (setup->request == USB_REQ_SET_ADDRESS &&
  1084. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD)
  1085. return xhci_address_device(udev, root_portnr);
  1086. if (setup->request == USB_REQ_SET_CONFIGURATION &&
  1087. (setup->requesttype & USB_TYPE_MASK) == USB_TYPE_STANDARD) {
  1088. ret = xhci_set_configuration(udev);
  1089. if (ret) {
  1090. puts("Failed to configure xHCI endpoint\n");
  1091. return ret;
  1092. }
  1093. }
  1094. return xhci_ctrl_tx(udev, pipe, setup, length, buffer);
  1095. }
  1096. static int xhci_lowlevel_init(struct xhci_ctrl *ctrl)
  1097. {
  1098. struct xhci_hccr *hccr;
  1099. struct xhci_hcor *hcor;
  1100. uint32_t val;
  1101. uint32_t val2;
  1102. uint32_t reg;
  1103. hccr = ctrl->hccr;
  1104. hcor = ctrl->hcor;
  1105. /*
  1106. * Program the Number of Device Slots Enabled field in the CONFIG
  1107. * register with the max value of slots the HC can handle.
  1108. */
  1109. val = (xhci_readl(&hccr->cr_hcsparams1) & HCS_SLOTS_MASK);
  1110. val2 = xhci_readl(&hcor->or_config);
  1111. val |= (val2 & ~HCS_SLOTS_MASK);
  1112. xhci_writel(&hcor->or_config, val);
  1113. /* initializing xhci data structures */
  1114. if (xhci_mem_init(ctrl, hccr, hcor) < 0)
  1115. return -ENOMEM;
  1116. reg = xhci_readl(&hccr->cr_hcsparams1);
  1117. descriptor.hub.bNbrPorts = HCS_MAX_PORTS(reg);
  1118. printf("Register %x NbrPorts %d\n", reg, descriptor.hub.bNbrPorts);
  1119. /* Port Indicators */
  1120. reg = xhci_readl(&hccr->cr_hccparams);
  1121. if (HCS_INDICATOR(reg))
  1122. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1123. | 0x80, &descriptor.hub.wHubCharacteristics);
  1124. /* Port Power Control */
  1125. if (HCC_PPC(reg))
  1126. put_unaligned(get_unaligned(&descriptor.hub.wHubCharacteristics)
  1127. | 0x01, &descriptor.hub.wHubCharacteristics);
  1128. if (xhci_start(hcor)) {
  1129. xhci_reset(hcor);
  1130. return -ENODEV;
  1131. }
  1132. /* Zero'ing IRQ control register and IRQ pending register */
  1133. xhci_writel(&ctrl->ir_set->irq_control, 0x0);
  1134. xhci_writel(&ctrl->ir_set->irq_pending, 0x0);
  1135. reg = HC_VERSION(xhci_readl(&hccr->cr_capbase));
  1136. printf("USB XHCI %x.%02x\n", reg >> 8, reg & 0xff);
  1137. ctrl->hci_version = reg;
  1138. return 0;
  1139. }
  1140. static int xhci_lowlevel_stop(struct xhci_ctrl *ctrl)
  1141. {
  1142. u32 temp;
  1143. xhci_reset(ctrl->hcor);
  1144. debug("// Disabling event ring interrupts\n");
  1145. temp = xhci_readl(&ctrl->hcor->or_usbsts);
  1146. xhci_writel(&ctrl->hcor->or_usbsts, temp & ~STS_EINT);
  1147. temp = xhci_readl(&ctrl->ir_set->irq_pending);
  1148. xhci_writel(&ctrl->ir_set->irq_pending, ER_IRQ_DISABLE(temp));
  1149. return 0;
  1150. }
  1151. #if !CONFIG_IS_ENABLED(DM_USB)
  1152. int submit_control_msg(struct usb_device *udev, unsigned long pipe,
  1153. void *buffer, int length, struct devrequest *setup)
  1154. {
  1155. struct usb_device *hop = udev;
  1156. if (hop->parent)
  1157. while (hop->parent->parent)
  1158. hop = hop->parent;
  1159. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1160. hop->portnr);
  1161. }
  1162. int submit_bulk_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1163. int length)
  1164. {
  1165. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1166. }
  1167. int submit_int_msg(struct usb_device *udev, unsigned long pipe, void *buffer,
  1168. int length, int interval, bool nonblock)
  1169. {
  1170. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1171. nonblock);
  1172. }
  1173. /**
  1174. * Intialises the XHCI host controller
  1175. * and allocates the necessary data structures
  1176. *
  1177. * @param index index to the host controller data structure
  1178. * @return pointer to the intialised controller
  1179. */
  1180. int usb_lowlevel_init(int index, enum usb_init_type init, void **controller)
  1181. {
  1182. struct xhci_hccr *hccr;
  1183. struct xhci_hcor *hcor;
  1184. struct xhci_ctrl *ctrl;
  1185. int ret;
  1186. *controller = NULL;
  1187. if (xhci_hcd_init(index, &hccr, (struct xhci_hcor **)&hcor) != 0)
  1188. return -ENODEV;
  1189. if (xhci_reset(hcor) != 0)
  1190. return -ENODEV;
  1191. ctrl = &xhcic[index];
  1192. ctrl->hccr = hccr;
  1193. ctrl->hcor = hcor;
  1194. ret = xhci_lowlevel_init(ctrl);
  1195. if (ret) {
  1196. ctrl->hccr = NULL;
  1197. ctrl->hcor = NULL;
  1198. } else {
  1199. *controller = &xhcic[index];
  1200. }
  1201. return ret;
  1202. }
  1203. /**
  1204. * Stops the XHCI host controller
  1205. * and cleans up all the related data structures
  1206. *
  1207. * @param index index to the host controller data structure
  1208. * @return none
  1209. */
  1210. int usb_lowlevel_stop(int index)
  1211. {
  1212. struct xhci_ctrl *ctrl = (xhcic + index);
  1213. if (ctrl->hcor) {
  1214. xhci_lowlevel_stop(ctrl);
  1215. xhci_hcd_stop(index);
  1216. xhci_cleanup(ctrl);
  1217. }
  1218. return 0;
  1219. }
  1220. #endif /* CONFIG_IS_ENABLED(DM_USB) */
  1221. #if CONFIG_IS_ENABLED(DM_USB)
  1222. static int xhci_submit_control_msg(struct udevice *dev, struct usb_device *udev,
  1223. unsigned long pipe, void *buffer, int length,
  1224. struct devrequest *setup)
  1225. {
  1226. struct usb_device *uhop;
  1227. struct udevice *hub;
  1228. int root_portnr = 0;
  1229. debug("%s: dev='%s', udev=%p, udev->dev='%s', portnr=%d\n", __func__,
  1230. dev->name, udev, udev->dev->name, udev->portnr);
  1231. hub = udev->dev;
  1232. if (device_get_uclass_id(hub) == UCLASS_USB_HUB) {
  1233. /* Figure out our port number on the root hub */
  1234. if (usb_hub_is_root_hub(hub)) {
  1235. root_portnr = udev->portnr;
  1236. } else {
  1237. while (!usb_hub_is_root_hub(hub->parent))
  1238. hub = hub->parent;
  1239. uhop = dev_get_parent_priv(hub);
  1240. root_portnr = uhop->portnr;
  1241. }
  1242. }
  1243. /*
  1244. struct usb_device *hop = udev;
  1245. if (hop->parent)
  1246. while (hop->parent->parent)
  1247. hop = hop->parent;
  1248. */
  1249. return _xhci_submit_control_msg(udev, pipe, buffer, length, setup,
  1250. root_portnr);
  1251. }
  1252. static int xhci_submit_bulk_msg(struct udevice *dev, struct usb_device *udev,
  1253. unsigned long pipe, void *buffer, int length)
  1254. {
  1255. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1256. return _xhci_submit_bulk_msg(udev, pipe, buffer, length);
  1257. }
  1258. static int xhci_submit_int_msg(struct udevice *dev, struct usb_device *udev,
  1259. unsigned long pipe, void *buffer, int length,
  1260. int interval, bool nonblock)
  1261. {
  1262. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1263. return _xhci_submit_int_msg(udev, pipe, buffer, length, interval,
  1264. nonblock);
  1265. }
  1266. static int xhci_alloc_device(struct udevice *dev, struct usb_device *udev)
  1267. {
  1268. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1269. return _xhci_alloc_device(udev);
  1270. }
  1271. static int xhci_update_hub_device(struct udevice *dev, struct usb_device *udev)
  1272. {
  1273. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1274. struct usb_hub_device *hub = dev_get_uclass_priv(udev->dev);
  1275. struct xhci_virt_device *virt_dev;
  1276. struct xhci_input_control_ctx *ctrl_ctx;
  1277. struct xhci_container_ctx *out_ctx;
  1278. struct xhci_container_ctx *in_ctx;
  1279. struct xhci_slot_ctx *slot_ctx;
  1280. int slot_id = udev->slot_id;
  1281. unsigned think_time;
  1282. debug("%s: dev='%s', udev=%p\n", __func__, dev->name, udev);
  1283. /* Ignore root hubs */
  1284. if (usb_hub_is_root_hub(udev->dev))
  1285. return 0;
  1286. virt_dev = ctrl->devs[slot_id];
  1287. BUG_ON(!virt_dev);
  1288. out_ctx = virt_dev->out_ctx;
  1289. in_ctx = virt_dev->in_ctx;
  1290. ctrl_ctx = xhci_get_input_control_ctx(in_ctx);
  1291. /* Initialize the input context control */
  1292. ctrl_ctx->add_flags = cpu_to_le32(SLOT_FLAG);
  1293. ctrl_ctx->drop_flags = 0;
  1294. xhci_inval_cache((uintptr_t)out_ctx->bytes, out_ctx->size);
  1295. /* slot context */
  1296. xhci_slot_copy(ctrl, in_ctx, out_ctx);
  1297. slot_ctx = xhci_get_slot_ctx(ctrl, in_ctx);
  1298. /* Update hub related fields */
  1299. slot_ctx->dev_info |= cpu_to_le32(DEV_HUB);
  1300. /*
  1301. * refer to section 6.2.2: MTT should be 0 for full speed hub,
  1302. * but it may be already set to 1 when setup an xHCI virtual
  1303. * device, so clear it anyway.
  1304. */
  1305. if (hub->tt.multi)
  1306. slot_ctx->dev_info |= cpu_to_le32(DEV_MTT);
  1307. else if (udev->speed == USB_SPEED_FULL)
  1308. slot_ctx->dev_info &= cpu_to_le32(~DEV_MTT);
  1309. slot_ctx->dev_info2 |= cpu_to_le32(XHCI_MAX_PORTS(udev->maxchild));
  1310. /*
  1311. * Set TT think time - convert from ns to FS bit times.
  1312. * Note 8 FS bit times == (8 bits / 12000000 bps) ~= 666ns
  1313. *
  1314. * 0 = 8 FS bit times, 1 = 16 FS bit times,
  1315. * 2 = 24 FS bit times, 3 = 32 FS bit times.
  1316. *
  1317. * This field shall be 0 if the device is not a high-spped hub.
  1318. */
  1319. think_time = hub->tt.think_time;
  1320. if (think_time != 0)
  1321. think_time = (think_time / 666) - 1;
  1322. if (udev->speed == USB_SPEED_HIGH)
  1323. slot_ctx->tt_info |= cpu_to_le32(TT_THINK_TIME(think_time));
  1324. slot_ctx->dev_state = 0;
  1325. return xhci_configure_endpoints(udev, false);
  1326. }
  1327. static int xhci_get_max_xfer_size(struct udevice *dev, size_t *size)
  1328. {
  1329. /*
  1330. * xHCD allocates one segment which includes 64 TRBs for each endpoint
  1331. * and the last TRB in this segment is configured as a link TRB to form
  1332. * a TRB ring. Each TRB can transfer up to 64K bytes, however data
  1333. * buffers referenced by transfer TRBs shall not span 64KB boundaries.
  1334. * Hence the maximum number of TRBs we can use in one transfer is 62.
  1335. */
  1336. *size = (TRBS_PER_SEGMENT - 2) * TRB_MAX_BUFF_SIZE;
  1337. return 0;
  1338. }
  1339. int xhci_register(struct udevice *dev, struct xhci_hccr *hccr,
  1340. struct xhci_hcor *hcor)
  1341. {
  1342. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1343. struct usb_bus_priv *priv = dev_get_uclass_priv(dev);
  1344. int ret;
  1345. debug("%s: dev='%s', ctrl=%p, hccr=%p, hcor=%p\n", __func__, dev->name,
  1346. ctrl, hccr, hcor);
  1347. ctrl->dev = dev;
  1348. ret = xhci_reset_hw(ctrl);
  1349. if (ret)
  1350. goto err;
  1351. /*
  1352. * XHCI needs to issue a Address device command to setup
  1353. * proper device context structures, before it can interact
  1354. * with the device. So a get_descriptor will fail before any
  1355. * of that is done for XHCI unlike EHCI.
  1356. */
  1357. priv->desc_before_addr = false;
  1358. ret = xhci_reset(hcor);
  1359. if (ret)
  1360. goto err;
  1361. ctrl->hccr = hccr;
  1362. ctrl->hcor = hcor;
  1363. ret = xhci_lowlevel_init(ctrl);
  1364. if (ret)
  1365. goto err;
  1366. return 0;
  1367. err:
  1368. free(ctrl);
  1369. debug("%s: failed, ret=%d\n", __func__, ret);
  1370. return ret;
  1371. }
  1372. int xhci_deregister(struct udevice *dev)
  1373. {
  1374. struct xhci_ctrl *ctrl = dev_get_priv(dev);
  1375. xhci_lowlevel_stop(ctrl);
  1376. xhci_cleanup(ctrl);
  1377. return 0;
  1378. }
  1379. struct dm_usb_ops xhci_usb_ops = {
  1380. .control = xhci_submit_control_msg,
  1381. .bulk = xhci_submit_bulk_msg,
  1382. .interrupt = xhci_submit_int_msg,
  1383. .alloc_device = xhci_alloc_device,
  1384. .update_hub_device = xhci_update_hub_device,
  1385. .get_max_xfer_size = xhci_get_max_xfer_size,
  1386. };
  1387. #endif