xtfpga.c 2.7 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * (C) Copyright 2007 - 2013 Tensilica Inc.
  4. * (C) Copyright 2014 - 2016 Cadence Design Systems Inc.
  5. */
  6. #include <common.h>
  7. #include <command.h>
  8. #include <dm.h>
  9. #include <init.h>
  10. #include <dm/platform_data/net_ethoc.h>
  11. #include <env.h>
  12. #include <linux/ctype.h>
  13. #include <linux/string.h>
  14. #include <linux/stringify.h>
  15. #include <asm/global_data.h>
  16. DECLARE_GLOBAL_DATA_PTR;
  17. /*
  18. * Check board idendity.
  19. * (Print information about the board to stdout.)
  20. */
  21. #if defined(CONFIG_XTFPGA_LX60)
  22. const char *board = "XT_AV60";
  23. const char *description = "Avnet Xilinx LX60 FPGA Evaluation Board / ";
  24. #elif defined(CONFIG_XTFPGA_LX110)
  25. const char *board = "XT_AV110";
  26. const char *description = "Avnet Xilinx Virtex-5 LX110 Evaluation Kit / ";
  27. #elif defined(CONFIG_XTFPGA_LX200)
  28. const char *board = "XT_AV200";
  29. const char *description = "Avnet Xilinx Virtex-4 LX200 Evaluation Kit / ";
  30. #elif defined(CONFIG_XTFPGA_ML605)
  31. const char *board = "XT_ML605";
  32. const char *description = "Xilinx Virtex-6 FPGA ML605 Evaluation Kit / ";
  33. #elif defined(CONFIG_XTFPGA_KC705)
  34. const char *board = "XT_KC705";
  35. const char *description = "Xilinx Kintex-7 FPGA KC705 Evaluation Kit / ";
  36. #else
  37. const char *board = "<unknown>";
  38. const char *description = "";
  39. #endif
  40. int checkboard(void)
  41. {
  42. printf("Board: %s: %sTensilica bitstream\n", board, description);
  43. return 0;
  44. }
  45. int dram_init_banksize(void)
  46. {
  47. return 0;
  48. }
  49. int board_postclk_init(void)
  50. {
  51. /*
  52. * Obtain CPU clock frequency from board and cache in global
  53. * data structure (Hz). Return 0 on success (OK to continue),
  54. * else non-zero (hang).
  55. */
  56. #ifdef CONFIG_SYS_FPGAREG_FREQ
  57. gd->cpu_clk = (*(volatile unsigned long *)CONFIG_SYS_FPGAREG_FREQ);
  58. #else
  59. /* early Tensilica bitstreams lack this reg, but most run at 50 MHz */
  60. gd->cpu_clk = 50000000UL;
  61. #endif
  62. return 0;
  63. }
  64. /*
  65. * Miscellaneous late initializations.
  66. * The environment has been set up, so we can set the Ethernet address.
  67. */
  68. int misc_init_r(void)
  69. {
  70. #ifdef CONFIG_CMD_NET
  71. /*
  72. * Initialize ethernet environment variables and board info.
  73. * Default MAC address comes from CONFIG_ETHADDR + DIP switches 1-6.
  74. */
  75. char *s = env_get("ethaddr");
  76. if (s == 0) {
  77. unsigned int x;
  78. char s[] = __stringify(CONFIG_ETHBASE);
  79. x = (*(volatile u32 *)CONFIG_SYS_FPGAREG_DIPSW)
  80. & FPGAREG_MAC_MASK;
  81. sprintf(&s[15], "%02x", x);
  82. env_set("ethaddr", s);
  83. }
  84. #endif /* CONFIG_CMD_NET */
  85. return 0;
  86. }
  87. U_BOOT_DEVICE(sysreset) = {
  88. .name = "xtfpga_sysreset",
  89. };
  90. static struct ethoc_eth_pdata ethoc_pdata = {
  91. .eth_pdata = {
  92. .iobase = CONFIG_SYS_ETHOC_BASE,
  93. },
  94. .packet_base = CONFIG_SYS_ETHOC_BUFFER_ADDR,
  95. };
  96. U_BOOT_DEVICE(ethoc) = {
  97. .name = "ethoc",
  98. .platdata = &ethoc_pdata,
  99. };