cpu_init.c 15 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187188189190191192193194195196197198199200201202203204205206207208209210211212213214215216217218219220221222223224225226227228229230231232233234235236237238239240241242243244245246247248249250251252253254255256257258259260261262263264265266267268269270271272273274275276277278279280281282283284285286287288289290291292293294295296297298299300301302303304305306307308309310311312313314315316317318319320321322323324325326327328329330331332333334335336337338339340341342343344345346347348349350351352353354355356357358359360361362363364365366367368369370371372373374375376377378379380381382383384385386387388389390391392393394395396397398399400401402403404405406407408409410411412413414415416417
  1. /*
  2. * (C) Copyright 2000
  3. * Rob Taylor. Flying Pig Systems. robt@flyingpig.com.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <asm/processor.h>
  25. #include <mpc824x.h>
  26. #ifndef CONFIG_SYS_BANK0_ROW
  27. #define CONFIG_SYS_BANK0_ROW 0
  28. #endif
  29. #ifndef CONFIG_SYS_BANK1_ROW
  30. #define CONFIG_SYS_BANK1_ROW 0
  31. #endif
  32. #ifndef CONFIG_SYS_BANK2_ROW
  33. #define CONFIG_SYS_BANK2_ROW 0
  34. #endif
  35. #ifndef CONFIG_SYS_BANK3_ROW
  36. #define CONFIG_SYS_BANK3_ROW 0
  37. #endif
  38. #ifndef CONFIG_SYS_BANK4_ROW
  39. #define CONFIG_SYS_BANK4_ROW 0
  40. #endif
  41. #ifndef CONFIG_SYS_BANK5_ROW
  42. #define CONFIG_SYS_BANK5_ROW 0
  43. #endif
  44. #ifndef CONFIG_SYS_BANK6_ROW
  45. #define CONFIG_SYS_BANK6_ROW 0
  46. #endif
  47. #ifndef CONFIG_SYS_BANK7_ROW
  48. #define CONFIG_SYS_BANK7_ROW 0
  49. #endif
  50. #ifndef CONFIG_SYS_DBUS_SIZE2
  51. #define CONFIG_SYS_DBUS_SIZE2 0
  52. #endif
  53. /*
  54. * Breath some life into the CPU...
  55. *
  56. * Set up the memory map,
  57. * initialize a bunch of registers,
  58. */
  59. void
  60. cpu_init_f (void)
  61. {
  62. /* MOUSSE board is initialized in asm */
  63. #if !defined(CONFIG_MOUSSE) && !defined(CONFIG_BMW)
  64. register unsigned long val;
  65. CONFIG_WRITE_HALFWORD(PCICR, 0x06); /* Bus Master, respond to PCI memory space acesses*/
  66. /* CONFIG_WRITE_HALFWORD(PCISR, 0xffff); */ /*reset PCISR*/
  67. #if defined(CONFIG_MUSENKI) || defined(CONFIG_PN62)
  68. /* Why is this here, you ask? Try, just try setting 0x8000
  69. * in PCIACR with CONFIG_WRITE_HALFWORD()
  70. * this one was a stumper, and we are annoyed
  71. */
  72. #define M_CONFIG_WRITE_HALFWORD( addr, data ) \
  73. __asm__ __volatile__(" \
  74. stw %2,0(%0)\n \
  75. sync\n \
  76. sth %3,2(%1)\n \
  77. sync\n \
  78. " \
  79. : /* no output */ \
  80. : "r" (CONFIG_ADDR), "r" (CONFIG_DATA), \
  81. "r" (PCISWAP(addr & ~3)), "r" (PCISWAP(data << 16)) \
  82. );
  83. M_CONFIG_WRITE_HALFWORD(PCIACR, 0x8000);
  84. #endif
  85. CONFIG_WRITE_BYTE(PCLSR, 0x8); /* set PCI cache line size */
  86. CONFIG_WRITE_BYTE (PLTR, 0x40); /* set PCI latency timer */
  87. /*
  88. * Note that although this bit is cleared after a hard reset, it
  89. * must be explicitly set and then cleared by software during
  90. * initialization in order to guarantee correct operation of the
  91. * DLL and the SDRAM_CLK[0:3] signals (if they are used).
  92. */
  93. CONFIG_READ_BYTE (AMBOR, val);
  94. CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
  95. CONFIG_WRITE_BYTE(AMBOR, val | 0x20);
  96. CONFIG_WRITE_BYTE(AMBOR, val & 0xDF);
  97. #ifdef CONFIG_MPC8245
  98. /* silicon bug 28 MPC8245 */
  99. CONFIG_READ_BYTE(AMBOR,val);
  100. CONFIG_WRITE_BYTE(AMBOR,val|0x1);
  101. #if 0
  102. /*
  103. * The following bug only affects older (XPC8245) processors.
  104. * DMA transfers initiated by external devices get corrupted due
  105. * to a hardware scheduling problem.
  106. *
  107. * The effect is:
  108. * when transferring X words, the first 32 words are transferred
  109. * OK, the next 3 x 32 words are 'old' data (from previous DMA)
  110. * while the rest of the X words is xferred fine.
  111. *
  112. * Disabling 3 of the 4 32 word hardware buffers solves the problem
  113. * with no significant performance loss.
  114. */
  115. CONFIG_READ_BYTE(PCMBCR,val);
  116. /* in order not to corrupt data which is being read over the PCI bus
  117. * with the PPC as slave, we need to reduce the number of PCMRBs to 1,
  118. * 4.11 in the processor user manual
  119. * */
  120. #if 1
  121. CONFIG_WRITE_BYTE(PCMBCR,(val|0xC0)); /* 1 PCMRB */
  122. #else
  123. CONFIG_WRITE_BYTE(PCMBCR,(val|0x80)); /* 2 PCMRBs */
  124. CONFIG_WRITE_BYTE(PCMBCR,(val|0x40)); /* 3 PCMRBs */
  125. /* default, 4 PCMRBs are used */
  126. #endif
  127. #endif
  128. #endif
  129. CONFIG_READ_WORD(PICR1, val);
  130. #if defined(CONFIG_MPC8240)
  131. CONFIG_WRITE_WORD( PICR1,
  132. (val & (PICR1_ADDRESS_MAP | PICR1_RCS0)) |
  133. PIRC1_MSK | PICR1_PROC_TYPE_603E |
  134. PICR1_FLASH_WR_EN | PICR1_MCP_EN |
  135. PICR1_CF_DPARK | PICR1_EN_PCS |
  136. PICR1_CF_APARK );
  137. #elif defined(CONFIG_MPC8245)
  138. CONFIG_WRITE_WORD( PICR1,
  139. (val & (PICR1_RCS0)) |
  140. PICR1_PROC_TYPE_603E |
  141. PICR1_FLASH_WR_EN | PICR1_MCP_EN |
  142. PICR1_CF_DPARK | PICR1_NO_BUSW_CK |
  143. PICR1_DEC| PICR1_CF_APARK | 0x10); /* 8245 UM says bit 4 must be set */
  144. #else
  145. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  146. #endif
  147. CONFIG_READ_WORD(PICR2, val);
  148. val= val & ~ (PICR2_CF_SNOOP_WS_MASK | PICR2_CF_APHASE_WS_MASK); /*mask off waitstate bits*/
  149. #ifndef CONFIG_PN62
  150. val |= PICR2_CF_SNOOP_WS_1WS | PICR2_CF_APHASE_WS_1WS; /*1 wait state*/
  151. #endif
  152. CONFIG_WRITE_WORD(PICR2, val);
  153. CONFIG_WRITE_WORD(EUMBBAR, CONFIG_SYS_EUMB_ADDR);
  154. #ifndef CONFIG_SYS_RAMBOOT
  155. CONFIG_WRITE_WORD(MCCR1, (CONFIG_SYS_ROMNAL << MCCR1_ROMNAL_SHIFT) |
  156. (CONFIG_SYS_BANK0_ROW) |
  157. (CONFIG_SYS_BANK1_ROW << MCCR1_BANK1ROW_SHIFT) |
  158. (CONFIG_SYS_BANK2_ROW << MCCR1_BANK2ROW_SHIFT) |
  159. (CONFIG_SYS_BANK3_ROW << MCCR1_BANK3ROW_SHIFT) |
  160. (CONFIG_SYS_BANK4_ROW << MCCR1_BANK4ROW_SHIFT) |
  161. (CONFIG_SYS_BANK5_ROW << MCCR1_BANK5ROW_SHIFT) |
  162. (CONFIG_SYS_BANK6_ROW << MCCR1_BANK6ROW_SHIFT) |
  163. (CONFIG_SYS_BANK7_ROW << MCCR1_BANK7ROW_SHIFT) |
  164. (CONFIG_SYS_ROMFAL << MCCR1_ROMFAL_SHIFT));
  165. #endif
  166. #if defined(CONFIG_SYS_ASRISE) && defined(CONFIG_SYS_ASFALL)
  167. CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT |
  168. CONFIG_SYS_ASRISE << MCCR2_ASRISE_SHIFT |
  169. CONFIG_SYS_ASFALL << MCCR2_ASFALL_SHIFT);
  170. #else
  171. CONFIG_WRITE_WORD(MCCR2, CONFIG_SYS_REFINT << MCCR2_REFINT_SHIFT);
  172. #endif
  173. #if defined(CONFIG_MPC8240)
  174. CONFIG_WRITE_WORD(MCCR3,
  175. (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
  176. (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT) |
  177. (CONFIG_SYS_RDLAT << MCCR3_RDLAT_SHIFT));
  178. #elif defined(CONFIG_MPC8245)
  179. CONFIG_WRITE_WORD(MCCR3,
  180. (((CONFIG_SYS_BSTOPRE & 0x003c) >> 2) << MCCR3_BSTOPRE2TO5_SHIFT) |
  181. (CONFIG_SYS_REFREC << MCCR3_REFREC_SHIFT));
  182. #else
  183. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  184. #endif
  185. /* this is gross. We think these should all be the same, and various boards
  186. * should define CONFIG_SYS_ACTORW to 0 if they don't want to set it, or even, if
  187. * its not set, we define it to zero in this file
  188. */
  189. #if defined(CONFIG_CU824) || defined(CONFIG_PN62)
  190. CONFIG_WRITE_WORD(MCCR4,
  191. (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
  192. (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
  193. MCCR4_BIT21 |
  194. (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
  195. ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
  196. (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
  197. CONFIG_SYS_SDMODE_BURSTLEN) << MCCR4_SDMODE_SHIFT) |
  198. (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
  199. (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) << MCCR4_BSTOPRE6TO9_SHIFT));
  200. #elif defined(CONFIG_MPC8240)
  201. CONFIG_WRITE_WORD(MCCR4,
  202. (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
  203. (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
  204. MCCR4_BIT21 |
  205. (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
  206. ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
  207. (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
  208. (CONFIG_SYS_SDMODE_BURSTLEN)) <<MCCR4_SDMODE_SHIFT) |
  209. (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
  210. #elif defined(CONFIG_MPC8245)
  211. CONFIG_READ_WORD(MCCR1, val);
  212. val &= MCCR1_DBUS_SIZE0; /* test for 64-bit mem bus */
  213. CONFIG_WRITE_WORD(MCCR4,
  214. (CONFIG_SYS_PRETOACT << MCCR4_PRETOACT_SHIFT) |
  215. (CONFIG_SYS_ACTTOPRE << MCCR4_ACTTOPRE_SHIFT) |
  216. (CONFIG_SYS_EXTROM ? MCCR4_EXTROM : 0) |
  217. (CONFIG_SYS_REGDIMM ? MCCR4_REGDIMM : 0) |
  218. (CONFIG_SYS_REGISTERD_TYPE_BUFFER ? MCCR4_REGISTERED: 0) |
  219. ((CONFIG_SYS_BSTOPRE & 0x0003) <<MCCR4_BSTOPRE0TO1_SHIFT ) |
  220. (CONFIG_SYS_DBUS_SIZE2 << MCCR4_DBUS_SIZE2_SHIFT) |
  221. (((CONFIG_SYS_SDMODE_CAS_LAT <<4) | (CONFIG_SYS_SDMODE_WRAP <<3) |
  222. (val ? 2 : 3)) << MCCR4_SDMODE_SHIFT) |
  223. (CONFIG_SYS_ACTORW << MCCR4_ACTTORW_SHIFT) |
  224. (((CONFIG_SYS_BSTOPRE & 0x03c0) >> 6) <<MCCR4_BSTOPRE6TO9_SHIFT ));
  225. #else
  226. #error Specific type of MPC824x must be defined (i.e. CONFIG_MPC8240)
  227. #endif
  228. CONFIG_WRITE_WORD(MSAR1,
  229. ( (CONFIG_SYS_BANK0_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
  230. (((CONFIG_SYS_BANK1_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
  231. (((CONFIG_SYS_BANK2_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
  232. (((CONFIG_SYS_BANK3_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
  233. CONFIG_WRITE_WORD(EMSAR1,
  234. ( (CONFIG_SYS_BANK0_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
  235. (((CONFIG_SYS_BANK1_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
  236. (((CONFIG_SYS_BANK2_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
  237. (((CONFIG_SYS_BANK3_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
  238. CONFIG_WRITE_WORD(MSAR2,
  239. ( (CONFIG_SYS_BANK4_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
  240. (((CONFIG_SYS_BANK5_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
  241. (((CONFIG_SYS_BANK6_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
  242. (((CONFIG_SYS_BANK7_START & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
  243. CONFIG_WRITE_WORD(EMSAR2,
  244. ( (CONFIG_SYS_BANK4_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
  245. (((CONFIG_SYS_BANK5_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
  246. (((CONFIG_SYS_BANK6_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
  247. (((CONFIG_SYS_BANK7_START & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
  248. CONFIG_WRITE_WORD(MEAR1,
  249. ( (CONFIG_SYS_BANK0_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
  250. (((CONFIG_SYS_BANK1_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
  251. (((CONFIG_SYS_BANK2_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
  252. (((CONFIG_SYS_BANK3_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
  253. CONFIG_WRITE_WORD(EMEAR1,
  254. ( (CONFIG_SYS_BANK0_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
  255. (((CONFIG_SYS_BANK1_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
  256. (((CONFIG_SYS_BANK2_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
  257. (((CONFIG_SYS_BANK3_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
  258. CONFIG_WRITE_WORD(MEAR2,
  259. ( (CONFIG_SYS_BANK4_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) |
  260. (((CONFIG_SYS_BANK5_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 8) |
  261. (((CONFIG_SYS_BANK6_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 16) |
  262. (((CONFIG_SYS_BANK7_END & MICR_ADDR_MASK) >> MICR_ADDR_SHIFT) << 24));
  263. CONFIG_WRITE_WORD(EMEAR2,
  264. ( (CONFIG_SYS_BANK4_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) |
  265. (((CONFIG_SYS_BANK5_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 8) |
  266. (((CONFIG_SYS_BANK6_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 16) |
  267. (((CONFIG_SYS_BANK7_END & MICR_EADDR_MASK) >> MICR_EADDR_SHIFT) << 24));
  268. CONFIG_WRITE_BYTE(ODCR, CONFIG_SYS_ODCR);
  269. #ifdef CONFIG_SYS_DLL_MAX_DELAY
  270. CONFIG_WRITE_BYTE(MIOCR1, CONFIG_SYS_DLL_MAX_DELAY); /* needed to make DLL lock */
  271. #endif
  272. #if defined(CONFIG_SYS_DLL_EXTEND) && defined(CONFIG_SYS_PCI_HOLD_DEL)
  273. CONFIG_WRITE_BYTE(PMCR2, CONFIG_SYS_DLL_EXTEND | CONFIG_SYS_PCI_HOLD_DEL);
  274. #endif
  275. #if defined(MIOCR2) && defined(CONFIG_SYS_SDRAM_DSCD)
  276. CONFIG_WRITE_BYTE(MIOCR2, CONFIG_SYS_SDRAM_DSCD); /* change memory input */
  277. #endif /* setup & hold time */
  278. CONFIG_WRITE_BYTE(MBER,
  279. CONFIG_SYS_BANK0_ENABLE |
  280. (CONFIG_SYS_BANK1_ENABLE << 1) |
  281. (CONFIG_SYS_BANK2_ENABLE << 2) |
  282. (CONFIG_SYS_BANK3_ENABLE << 3) |
  283. (CONFIG_SYS_BANK4_ENABLE << 4) |
  284. (CONFIG_SYS_BANK5_ENABLE << 5) |
  285. (CONFIG_SYS_BANK6_ENABLE << 6) |
  286. (CONFIG_SYS_BANK7_ENABLE << 7));
  287. #ifdef CONFIG_SYS_PGMAX
  288. CONFIG_WRITE_BYTE(MPMR, CONFIG_SYS_PGMAX);
  289. #endif
  290. /* ! Wait 200us before initialize other registers */
  291. /*FIXME: write a decent udelay wait */
  292. __asm__ __volatile__(
  293. " mtctr %0 \n \
  294. 0: bdnz 0b\n"
  295. :
  296. : "r" (0x10000));
  297. CONFIG_READ_WORD(MCCR1, val);
  298. CONFIG_WRITE_WORD(MCCR1, val | MCCR1_MEMGO); /* set memory access going */
  299. __asm__ __volatile__("eieio");
  300. #endif /* !CONFIG_MOUSSE && !CONFIG_BMW */
  301. }
  302. #ifdef CONFIG_MOUSSE
  303. #ifdef INCLUDE_MPC107_REPORT
  304. struct MPC107_s {
  305. unsigned int iobase;
  306. char desc[120];
  307. } MPC107Regs[] = {
  308. { BMC_BASE + 0x00, "MPC107 Vendor/Device ID" },
  309. { BMC_BASE + 0x04, "MPC107 PCI Command/Status Register" },
  310. { BMC_BASE + 0x08, "MPC107 Revision" },
  311. { BMC_BASE + 0x0C, "MPC107 Cache Line Size" },
  312. { BMC_BASE + 0x10, "MPC107 LMBAR" },
  313. { BMC_BASE + 0x14, "MPC824x PCSR" },
  314. { BMC_BASE + 0xA8, "MPC824x PICR1" },
  315. { BMC_BASE + 0xAC, "MPC824x PICR2" },
  316. { BMC_BASE + 0x46, "MPC824x PACR" },
  317. { BMC_BASE + 0x310, "MPC824x ITWR" },
  318. { BMC_BASE + 0x300, "MPC824x OMBAR" },
  319. { BMC_BASE + 0x308, "MPC824x OTWR" },
  320. { BMC_BASE + 0x14, "MPC107 Peripheral Control and Status Register" },
  321. { BMC_BASE + 0x78, "MPC107 EUMBAR" },
  322. { BMC_BASE + 0xC0, "MPC107 Processor Bus Error Status" },
  323. { BMC_BASE + 0xC4, "MPC107 PCI Bus Error Status" },
  324. { BMC_BASE + 0xC8, "MPC107 Processor/PCI Error Address" },
  325. { BMC_BASE + 0xE0, "MPC107 AMBOR Register" },
  326. { BMC_BASE + 0xF0, "MPC107 MCCR1 Register" },
  327. { BMC_BASE + 0xF4, "MPC107 MCCR2 Register" },
  328. { BMC_BASE + 0xF8, "MPC107 MCCR3 Register" },
  329. { BMC_BASE + 0xFC, "MPC107 MCCR4 Register" },
  330. };
  331. #define N_MPC107_Regs (sizeof(MPC107Regs)/sizeof(MPC107Regs[0]))
  332. #endif /* INCLUDE_MPC107_REPORT */
  333. #endif /* CONFIG_MOUSSE */
  334. /*
  335. * initialize higher level parts of CPU like time base and timers
  336. */
  337. int cpu_init_r (void)
  338. {
  339. #ifdef CONFIG_MOUSSE
  340. #ifdef INCLUDE_MPC107_REPORT
  341. unsigned int tmp = 0, i;
  342. #endif
  343. /*
  344. * Initialize the EUMBBAR (Embedded Util Mem Block Base Addr Reg).
  345. * This is necessary before the EPIC, DMA ctlr, I2C ctlr, etc. can
  346. * be accessed.
  347. */
  348. #ifdef CONFIG_MPC8240 /* only on MPC8240 */
  349. mpc824x_mpc107_setreg (EUMBBAR, EUMBBAR_VAL);
  350. /* MOT/SPS: Issue #10002, PCI (FD Alias enable) */
  351. mpc824x_mpc107_setreg (AMBOR, 0x000000C0);
  352. #endif
  353. #ifdef INCLUDE_MPC107_REPORT
  354. /* Check MPC824x PCI Device and Vendor ID */
  355. while ((tmp = mpc824x_mpc107_getreg (BMC_BASE)) != 0x31057) {
  356. printf (" MPC107: offset=0x%x, val = 0x%x\n",
  357. BMC_BASE,
  358. tmp);
  359. }
  360. for (i = 0; i < N_MPC107_Regs; i++) {
  361. printf (" 0x%x/%s = 0x%x\n",
  362. MPC107Regs[i].iobase,
  363. MPC107Regs[i].desc,
  364. mpc824x_mpc107_getreg (MPC107Regs[i].iobase));
  365. }
  366. printf ("IBAT0L = 0x%08X\n", mfspr (IBAT0L));
  367. printf ("IBAT0U = 0x%08X\n", mfspr (IBAT0U));
  368. printf ("IBAT1L = 0x%08X\n", mfspr (IBAT1L));
  369. printf ("IBAT1U = 0x%08X\n", mfspr (IBAT1U));
  370. printf ("IBAT2L = 0x%08X\n", mfspr (IBAT2L));
  371. printf ("IBAT2U = 0x%08X\n", mfspr (IBAT2U));
  372. printf ("IBAT3L = 0x%08X\n", mfspr (IBAT3L));
  373. printf ("IBAT3U = 0x%08X\n", mfspr (IBAT3U));
  374. printf ("DBAT0L = 0x%08X\n", mfspr (DBAT0L));
  375. printf ("DBAT0U = 0x%08X\n", mfspr (DBAT0U));
  376. printf ("DBAT1L = 0x%08X\n", mfspr (DBAT1L));
  377. printf ("DBAT1U = 0x%08X\n", mfspr (DBAT1U));
  378. printf ("DBAT2L = 0x%08X\n", mfspr (DBAT2L));
  379. printf ("DBAT2U = 0x%08X\n", mfspr (DBAT2U));
  380. printf ("DBAT3L = 0x%08X\n", mfspr (DBAT3L));
  381. printf ("DBAT3U = 0x%08X\n", mfspr (DBAT3U));
  382. #endif /* INCLUDE_MPC107_REPORT */
  383. #endif /* CONFIG_MOUSSE */
  384. return (0);
  385. }