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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. /*
  25. * U-Boot - Startup Code for MPC8220 CPUs
  26. */
  27. #include <config.h>
  28. #include <mpc8220.h>
  29. #include <timestamp.h>
  30. #include <version.h>
  31. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  32. #include <ppc_asm.tmpl>
  33. #include <ppc_defs.h>
  34. #include <asm/cache.h>
  35. #include <asm/mmu.h>
  36. #ifndef CONFIG_IDENT_STRING
  37. #define CONFIG_IDENT_STRING ""
  38. #endif
  39. /* We don't want the MMU yet.
  40. */
  41. #undef MSR_KERNEL
  42. /* Floating Point enable, Machine Check and Recoverable Interr. */
  43. #ifdef DEBUG
  44. #define MSR_KERNEL (MSR_FP|MSR_RI)
  45. #else
  46. #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  47. #endif
  48. /*
  49. * Set up GOT: Global Offset Table
  50. *
  51. * Use r12 to access the GOT
  52. */
  53. START_GOT
  54. GOT_ENTRY(_GOT2_TABLE_)
  55. GOT_ENTRY(_FIXUP_TABLE_)
  56. GOT_ENTRY(_start)
  57. GOT_ENTRY(_start_of_vectors)
  58. GOT_ENTRY(_end_of_vectors)
  59. GOT_ENTRY(transfer_to_handler)
  60. GOT_ENTRY(__init_end)
  61. GOT_ENTRY(_end)
  62. GOT_ENTRY(__bss_start)
  63. END_GOT
  64. /*
  65. * Version string
  66. */
  67. .data
  68. .globl version_string
  69. version_string:
  70. .ascii U_BOOT_VERSION
  71. .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  72. .ascii CONFIG_IDENT_STRING, "\0"
  73. /*
  74. * Exception vectors
  75. */
  76. .text
  77. . = EXC_OFF_SYS_RESET
  78. .globl _start
  79. _start:
  80. li r21, BOOTFLAG_COLD /* Normal Power-On */
  81. nop
  82. b boot_cold
  83. . = EXC_OFF_SYS_RESET + 0x10
  84. .globl _start_warm
  85. _start_warm:
  86. li r21, BOOTFLAG_WARM /* Software reboot */
  87. b boot_warm
  88. boot_cold:
  89. boot_warm:
  90. mfmsr r5 /* save msr contents */
  91. /* replace default MBAR base address from 0x80000000
  92. to 0xf0000000 */
  93. #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
  94. lis r3, CONFIG_SYS_MBAR@h
  95. ori r3, r3, CONFIG_SYS_MBAR@l
  96. /* MBAR is mirrored into the MBAR SPR */
  97. mtspr MBAR,r3
  98. mtspr SPRN_SPRG7W,r3
  99. lis r4, CONFIG_SYS_DEFAULT_MBAR@h
  100. stw r3, 0(r4)
  101. #endif /* CONFIG_SYS_DEFAULT_MBAR */
  102. /* Initialise the MPC8220 processor core */
  103. /*--------------------------------------------------------------*/
  104. bl init_8220_core
  105. /* initialize some things that are hard to access from C */
  106. /*--------------------------------------------------------------*/
  107. /* set up stack in on-chip SRAM */
  108. lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
  109. ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
  110. ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
  111. li r0, 0 /* Make room for stack frame header and */
  112. stwu r0, -4(r1) /* clear final stack frame so that */
  113. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  114. /* let the C-code set up the rest */
  115. /* */
  116. /* Be careful to keep code relocatable ! */
  117. /*--------------------------------------------------------------*/
  118. GET_GOT /* initialize GOT access */
  119. /* r3: IMMR */
  120. bl cpu_init_f /* run low-level CPU init code (in Flash)*/
  121. mr r3, r21
  122. /* r3: BOOTFLAG */
  123. bl board_init_f /* run 1st part of board init code (in Flash)*/
  124. /*
  125. * Vector Table
  126. */
  127. .globl _start_of_vectors
  128. _start_of_vectors:
  129. /* Machine check */
  130. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  131. /* Data Storage exception. */
  132. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  133. /* Instruction Storage exception. */
  134. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  135. /* External Interrupt exception. */
  136. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  137. /* Alignment exception. */
  138. . = 0x600
  139. Alignment:
  140. EXCEPTION_PROLOG(SRR0, SRR1)
  141. mfspr r4,DAR
  142. stw r4,_DAR(r21)
  143. mfspr r5,DSISR
  144. stw r5,_DSISR(r21)
  145. addi r3,r1,STACK_FRAME_OVERHEAD
  146. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  147. /* Program check exception */
  148. . = 0x700
  149. ProgramCheck:
  150. EXCEPTION_PROLOG(SRR0, SRR1)
  151. addi r3,r1,STACK_FRAME_OVERHEAD
  152. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  153. MSR_KERNEL, COPY_EE)
  154. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  155. /* I guess we could implement decrementer, and may have
  156. * to someday for timekeeping.
  157. */
  158. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  159. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  160. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  161. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  162. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  163. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  164. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  165. STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
  166. STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
  167. STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
  168. #ifdef DEBUG
  169. . = 0x1300
  170. /*
  171. * This exception occurs when the program counter matches the
  172. * Instruction Address Breakpoint Register (IABR).
  173. *
  174. * I want the cpu to halt if this occurs so I can hunt around
  175. * with the debugger and look at things.
  176. *
  177. * When DEBUG is defined, both machine check enable (in the MSR)
  178. * and checkstop reset enable (in the reset mode register) are
  179. * turned off and so a checkstop condition will result in the cpu
  180. * halting.
  181. *
  182. * I force the cpu into a checkstop condition by putting an illegal
  183. * instruction here (at least this is the theory).
  184. *
  185. * well - that didnt work, so just do an infinite loop!
  186. */
  187. 1: b 1b
  188. #else
  189. STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
  190. #endif
  191. STD_EXCEPTION(0x1400, SMI, UnknownException)
  192. STD_EXCEPTION(0x1500, Trap_15, UnknownException)
  193. STD_EXCEPTION(0x1600, Trap_16, UnknownException)
  194. STD_EXCEPTION(0x1700, Trap_17, UnknownException)
  195. STD_EXCEPTION(0x1800, Trap_18, UnknownException)
  196. STD_EXCEPTION(0x1900, Trap_19, UnknownException)
  197. STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
  198. STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
  199. STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
  200. STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
  201. STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
  202. STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
  203. STD_EXCEPTION(0x2000, Trap_20, UnknownException)
  204. STD_EXCEPTION(0x2100, Trap_21, UnknownException)
  205. STD_EXCEPTION(0x2200, Trap_22, UnknownException)
  206. STD_EXCEPTION(0x2300, Trap_23, UnknownException)
  207. STD_EXCEPTION(0x2400, Trap_24, UnknownException)
  208. STD_EXCEPTION(0x2500, Trap_25, UnknownException)
  209. STD_EXCEPTION(0x2600, Trap_26, UnknownException)
  210. STD_EXCEPTION(0x2700, Trap_27, UnknownException)
  211. STD_EXCEPTION(0x2800, Trap_28, UnknownException)
  212. STD_EXCEPTION(0x2900, Trap_29, UnknownException)
  213. STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
  214. STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
  215. STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
  216. STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
  217. STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
  218. STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
  219. .globl _end_of_vectors
  220. _end_of_vectors:
  221. . = 0x3000
  222. /*
  223. * This code finishes saving the registers to the exception frame
  224. * and jumps to the appropriate handler for the exception.
  225. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  226. */
  227. .globl transfer_to_handler
  228. transfer_to_handler:
  229. stw r22,_NIP(r21)
  230. lis r22,MSR_POW@h
  231. andc r23,r23,r22
  232. stw r23,_MSR(r21)
  233. SAVE_GPR(7, r21)
  234. SAVE_4GPRS(8, r21)
  235. SAVE_8GPRS(12, r21)
  236. SAVE_8GPRS(24, r21)
  237. mflr r23
  238. andi. r24,r23,0x3f00 /* get vector offset */
  239. stw r24,TRAP(r21)
  240. li r22,0
  241. stw r22,RESULT(r21)
  242. lwz r24,0(r23) /* virtual address of handler */
  243. lwz r23,4(r23) /* where to go when done */
  244. mtspr SRR0,r24
  245. mtspr SRR1,r20
  246. mtlr r23
  247. SYNC
  248. rfi /* jump to handler, enable MMU */
  249. int_return:
  250. mfmsr r28 /* Disable interrupts */
  251. li r4,0
  252. ori r4,r4,MSR_EE
  253. andc r28,r28,r4
  254. SYNC /* Some chip revs need this... */
  255. mtmsr r28
  256. SYNC
  257. lwz r2,_CTR(r1)
  258. lwz r0,_LINK(r1)
  259. mtctr r2
  260. mtlr r0
  261. lwz r2,_XER(r1)
  262. lwz r0,_CCR(r1)
  263. mtspr XER,r2
  264. mtcrf 0xFF,r0
  265. REST_10GPRS(3, r1)
  266. REST_10GPRS(13, r1)
  267. REST_8GPRS(23, r1)
  268. REST_GPR(31, r1)
  269. lwz r2,_NIP(r1) /* Restore environment */
  270. lwz r0,_MSR(r1)
  271. mtspr SRR0,r2
  272. mtspr SRR1,r0
  273. lwz r0,GPR0(r1)
  274. lwz r2,GPR2(r1)
  275. lwz r1,GPR1(r1)
  276. SYNC
  277. rfi
  278. /*
  279. * This code initialises the MPC8220 processor core
  280. * (conforms to PowerPC 603e spec)
  281. * Note: expects original MSR contents to be in r5.
  282. */
  283. .globl init_8220_core
  284. init_8220_core:
  285. /* Initialize machine status; enable machine check interrupt */
  286. /*--------------------------------------------------------------*/
  287. li r3, MSR_KERNEL /* Set ME and RI flags */
  288. rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
  289. #ifdef DEBUG
  290. rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
  291. #endif
  292. SYNC /* Some chip revs need this... */
  293. mtmsr r3
  294. SYNC
  295. mtspr SRR1, r3 /* Make SRR1 match MSR */
  296. /* Initialize the Hardware Implementation-dependent Registers */
  297. /* HID0 also contains cache control */
  298. /*--------------------------------------------------------------*/
  299. lis r3, CONFIG_SYS_HID0_INIT@h
  300. ori r3, r3, CONFIG_SYS_HID0_INIT@l
  301. SYNC
  302. mtspr HID0, r3
  303. lis r3, CONFIG_SYS_HID0_FINAL@h
  304. ori r3, r3, CONFIG_SYS_HID0_FINAL@l
  305. SYNC
  306. mtspr HID0, r3
  307. /* Enable Extra BATs */
  308. mfspr r3, 1011 /* HID2 */
  309. lis r4, 0x0004
  310. ori r4, r4, 0x0000
  311. or r4, r4, r3
  312. mtspr 1011, r4
  313. sync
  314. /* clear all BAT's */
  315. /*--------------------------------------------------------------*/
  316. li r0, 0
  317. mtspr DBAT0U, r0
  318. mtspr DBAT0L, r0
  319. mtspr DBAT1U, r0
  320. mtspr DBAT1L, r0
  321. mtspr DBAT2U, r0
  322. mtspr DBAT2L, r0
  323. mtspr DBAT3U, r0
  324. mtspr DBAT3L, r0
  325. mtspr DBAT4U, r0
  326. mtspr DBAT4L, r0
  327. mtspr DBAT5U, r0
  328. mtspr DBAT5L, r0
  329. mtspr DBAT6U, r0
  330. mtspr DBAT6L, r0
  331. mtspr DBAT7U, r0
  332. mtspr DBAT7L, r0
  333. mtspr IBAT0U, r0
  334. mtspr IBAT0L, r0
  335. mtspr IBAT1U, r0
  336. mtspr IBAT1L, r0
  337. mtspr IBAT2U, r0
  338. mtspr IBAT2L, r0
  339. mtspr IBAT3U, r0
  340. mtspr IBAT3L, r0
  341. mtspr IBAT4U, r0
  342. mtspr IBAT4L, r0
  343. mtspr IBAT5U, r0
  344. mtspr IBAT5L, r0
  345. mtspr IBAT6U, r0
  346. mtspr IBAT6L, r0
  347. mtspr IBAT7U, r0
  348. mtspr IBAT7L, r0
  349. SYNC
  350. /* invalidate all tlb's */
  351. /* */
  352. /* From the 603e User Manual: "The 603e provides the ability to */
  353. /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
  354. /* instruction invalidates the TLB entry indexed by the EA, and */
  355. /* operates on both the instruction and data TLBs simultaneously*/
  356. /* invalidating four TLB entries (both sets in each TLB). The */
  357. /* index corresponds to bits 15-19 of the EA. To invalidate all */
  358. /* entries within both TLBs, 32 tlbie instructions should be */
  359. /* issued, incrementing this field by one each time." */
  360. /* */
  361. /* "Note that the tlbia instruction is not implemented on the */
  362. /* 603e." */
  363. /* */
  364. /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
  365. /* incrementing by 0x1000 each time. The code below is sort of */
  366. /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
  367. /* */
  368. /*--------------------------------------------------------------*/
  369. li r3, 32
  370. mtctr r3
  371. li r3, 0
  372. 1: tlbie r3
  373. addi r3, r3, 0x1000
  374. bdnz 1b
  375. SYNC
  376. /* Done! */
  377. /*--------------------------------------------------------------*/
  378. blr
  379. /* Cache functions.
  380. *
  381. * Note: requires that all cache bits in
  382. * HID0 are in the low half word.
  383. */
  384. .globl icache_enable
  385. icache_enable:
  386. lis r4, 0
  387. ori r4, r4, CONFIG_SYS_HID0_INIT /* set ICE & ICFI bit */
  388. rlwinm r3, r4, 0, 21, 19 /* clear the ICFI bit */
  389. /*
  390. * The setting of the instruction cache enable (ICE) bit must be
  391. * preceded by an isync instruction to prevent the cache from being
  392. * enabled or disabled while an instruction access is in progress.
  393. */
  394. isync
  395. mtspr HID0, r4 /* Enable Instr Cache & Inval cache */
  396. mtspr HID0, r3 /* using 2 consec instructions */
  397. isync
  398. blr
  399. .globl icache_disable
  400. icache_disable:
  401. mfspr r3, HID0
  402. rlwinm r3, r3, 0, 17, 15 /* clear the ICE bit */
  403. mtspr HID0, r3
  404. isync
  405. blr
  406. .globl icache_status
  407. icache_status:
  408. mfspr r3, HID0
  409. rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
  410. blr
  411. .globl dcache_enable
  412. dcache_enable:
  413. lis r4, 0
  414. ori r4, r4, HID0_DCE|HID0_DCFI /* set DCE & DCFI bit */
  415. rlwinm r3, r4, 0, 22, 20 /* clear the DCFI bit */
  416. /* Enable address translation in MSR bit */
  417. mfmsr r5
  418. ori r5, r5, 0x
  419. /*
  420. * The setting of the instruction cache enable (ICE) bit must be
  421. * preceded by an isync instruction to prevent the cache from being
  422. * enabled or disabled while an instruction access is in progress.
  423. */
  424. isync
  425. mtspr HID0, r4 /* Enable Data Cache & Inval cache*/
  426. mtspr HID0, r3 /* using 2 consec instructions */
  427. isync
  428. blr
  429. .globl dcache_disable
  430. dcache_disable:
  431. mfspr r3, HID0
  432. rlwinm r3, r3, 0, 18, 16 /* clear the DCE bit */
  433. mtspr HID0, r3
  434. isync
  435. blr
  436. .globl dcache_status
  437. dcache_status:
  438. mfspr r3, HID0
  439. rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
  440. blr
  441. .globl get_pvr
  442. get_pvr:
  443. mfspr r3, PVR
  444. blr
  445. /*------------------------------------------------------------------------------*/
  446. /*
  447. * void relocate_code (addr_sp, gd, addr_moni)
  448. *
  449. * This "function" does not return, instead it continues in RAM
  450. * after relocating the monitor code.
  451. *
  452. * r3 = dest
  453. * r4 = src
  454. * r5 = length in bytes
  455. * r6 = cachelinesize
  456. */
  457. .globl relocate_code
  458. relocate_code:
  459. mr r1, r3 /* Set new stack pointer */
  460. mr r9, r4 /* Save copy of Global Data pointer */
  461. mr r10, r5 /* Save copy of Destination Address */
  462. GET_GOT
  463. mr r3, r5 /* Destination Address */
  464. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  465. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  466. lwz r5, GOT(__init_end)
  467. sub r5, r5, r4
  468. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  469. /*
  470. * Fix GOT pointer:
  471. *
  472. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  473. *
  474. * Offset:
  475. */
  476. sub r15, r10, r4
  477. /* First our own GOT */
  478. add r12, r12, r15
  479. /* then the one used by the C code */
  480. add r30, r30, r15
  481. /*
  482. * Now relocate code
  483. */
  484. cmplw cr1,r3,r4
  485. addi r0,r5,3
  486. srwi. r0,r0,2
  487. beq cr1,4f /* In place copy is not necessary */
  488. beq 7f /* Protect against 0 count */
  489. mtctr r0
  490. bge cr1,2f
  491. la r8,-4(r4)
  492. la r7,-4(r3)
  493. 1: lwzu r0,4(r8)
  494. stwu r0,4(r7)
  495. bdnz 1b
  496. b 4f
  497. 2: slwi r0,r0,2
  498. add r8,r4,r0
  499. add r7,r3,r0
  500. 3: lwzu r0,-4(r8)
  501. stwu r0,-4(r7)
  502. bdnz 3b
  503. /*
  504. * Now flush the cache: note that we must start from a cache aligned
  505. * address. Otherwise we might miss one cache line.
  506. */
  507. 4: cmpwi r6,0
  508. add r5,r3,r5
  509. beq 7f /* Always flush prefetch queue in any case */
  510. subi r0,r6,1
  511. andc r3,r3,r0
  512. mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
  513. rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
  514. cmpwi r7,0
  515. beq 9f
  516. mr r4,r3
  517. 5: dcbst 0,r4
  518. add r4,r4,r6
  519. cmplw r4,r5
  520. blt 5b
  521. sync /* Wait for all dcbst to complete on bus */
  522. 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
  523. rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
  524. cmpwi r7,0
  525. beq 7f
  526. mr r4,r3
  527. 6: icbi 0,r4
  528. add r4,r4,r6
  529. cmplw r4,r5
  530. blt 6b
  531. 7: sync /* Wait for all icbi to complete on bus */
  532. isync
  533. /*
  534. * We are done. Do not return, instead branch to second part of board
  535. * initialization, now running from RAM.
  536. */
  537. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  538. mtlr r0
  539. blr
  540. in_ram:
  541. /*
  542. * Relocation Function, r12 point to got2+0x8000
  543. *
  544. * Adjust got2 pointers, no need to check for 0, this code
  545. * already puts a few entries in the table.
  546. */
  547. li r0,__got2_entries@sectoff@l
  548. la r3,GOT(_GOT2_TABLE_)
  549. lwz r11,GOT(_GOT2_TABLE_)
  550. mtctr r0
  551. sub r11,r3,r11
  552. addi r3,r3,-4
  553. 1: lwzu r0,4(r3)
  554. cmpwi r0,0
  555. beq- 2f
  556. add r0,r0,r11
  557. stw r0,0(r3)
  558. 2: bdnz 1b
  559. /*
  560. * Now adjust the fixups and the pointers to the fixups
  561. * in case we need to move ourselves again.
  562. */
  563. li r0,__fixup_entries@sectoff@l
  564. lwz r3,GOT(_FIXUP_TABLE_)
  565. cmpwi r0,0
  566. mtctr r0
  567. addi r3,r3,-4
  568. beq 4f
  569. 3: lwzu r4,4(r3)
  570. lwzux r0,r4,r11
  571. add r0,r0,r11
  572. stw r10,0(r3)
  573. stw r0,0(r4)
  574. bdnz 3b
  575. 4:
  576. clear_bss:
  577. /*
  578. * Now clear BSS segment
  579. */
  580. lwz r3,GOT(__bss_start)
  581. lwz r4,GOT(_end)
  582. cmplw 0, r3, r4
  583. beq 6f
  584. li r0, 0
  585. 5:
  586. stw r0, 0(r3)
  587. addi r3, r3, 4
  588. cmplw 0, r3, r4
  589. bne 5b
  590. 6:
  591. mr r3, r9 /* Global Data pointer */
  592. mr r4, r10 /* Destination Address */
  593. bl board_init_r
  594. /*
  595. * Copy exception vector code to low memory
  596. *
  597. * r3: dest_addr
  598. * r7: source address, r8: end address, r9: target address
  599. */
  600. .globl trap_init
  601. trap_init:
  602. mflr r4 /* save link register */
  603. GET_GOT
  604. lwz r7, GOT(_start)
  605. lwz r8, GOT(_end_of_vectors)
  606. li r9, 0x100 /* reset vector always at 0x100 */
  607. cmplw 0, r7, r8
  608. bgelr /* return if r7>=r8 - just in case */
  609. 1:
  610. lwz r0, 0(r7)
  611. stw r0, 0(r9)
  612. addi r7, r7, 4
  613. addi r9, r9, 4
  614. cmplw 0, r7, r8
  615. bne 1b
  616. /*
  617. * relocate `hdlr' and `int_return' entries
  618. */
  619. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  620. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  621. 2:
  622. bl trap_reloc
  623. addi r7, r7, 0x100 /* next exception vector */
  624. cmplw 0, r7, r8
  625. blt 2b
  626. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  627. bl trap_reloc
  628. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  629. bl trap_reloc
  630. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  631. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  632. 3:
  633. bl trap_reloc
  634. addi r7, r7, 0x100 /* next exception vector */
  635. cmplw 0, r7, r8
  636. blt 3b
  637. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  638. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  639. 4:
  640. bl trap_reloc
  641. addi r7, r7, 0x100 /* next exception vector */
  642. cmplw 0, r7, r8
  643. blt 4b
  644. mfmsr r3 /* now that the vectors have */
  645. lis r7, MSR_IP@h /* relocated into low memory */
  646. ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
  647. andc r3, r3, r7 /* (if it was on) */
  648. SYNC /* Some chip revs need this... */
  649. mtmsr r3
  650. SYNC
  651. mtlr r4 /* restore link register */
  652. blr