cpu_init.c 4.1 KB

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  1. /*
  2. * (C) Copyright 2000-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #include <mpc8220.h>
  25. DECLARE_GLOBAL_DATA_PTR;
  26. /*
  27. * Breath some life into the CPU...
  28. *
  29. * Set up the memory map,
  30. * initialize a bunch of registers.
  31. */
  32. void cpu_init_f (void)
  33. {
  34. volatile flexbus8220_t *flexbus = (volatile flexbus8220_t *) MMAP_FB;
  35. volatile pcfg8220_t *portcfg = (volatile pcfg8220_t *) MMAP_PCFG;
  36. volatile xlbarb8220_t *xlbarb = (volatile xlbarb8220_t *) MMAP_XLBARB;
  37. /* Pointer is writable since we allocated a register for it */
  38. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  39. /* Clear initial global data */
  40. memset ((void *) gd, 0, sizeof (gd_t));
  41. /* Clear all port configuration */
  42. portcfg->pcfg0 = 0;
  43. portcfg->pcfg1 = 0;
  44. portcfg->pcfg2 = 0;
  45. portcfg->pcfg3 = 0;
  46. portcfg->pcfg2 = CONFIG_SYS_GP1_PORT2_CONFIG;
  47. portcfg->pcfg3 = CONFIG_SYS_PCI_PORT3_CONFIG | CONFIG_SYS_GP2_PORT3_CONFIG;
  48. /*
  49. * Flexbus Controller: configure chip selects and enable them
  50. */
  51. #if defined (CONFIG_SYS_CS0_BASE)
  52. flexbus->csar0 = CONFIG_SYS_CS0_BASE;
  53. /* Sorcery-C can hang-up after CTRL reg initialization */
  54. #if defined (CONFIG_SYS_CS0_CTRL)
  55. flexbus->cscr0 = CONFIG_SYS_CS0_CTRL;
  56. #endif
  57. flexbus->csmr0 = ((CONFIG_SYS_CS0_MASK - 1) & 0xffff0000) | 1;
  58. __asm__ volatile ("sync");
  59. #endif
  60. #if defined (CONFIG_SYS_CS1_BASE)
  61. flexbus->csar1 = CONFIG_SYS_CS1_BASE;
  62. flexbus->cscr1 = CONFIG_SYS_CS1_CTRL;
  63. flexbus->csmr1 = ((CONFIG_SYS_CS1_MASK - 1) & 0xffff0000) | 1;
  64. __asm__ volatile ("sync");
  65. #endif
  66. #if defined (CONFIG_SYS_CS2_BASE)
  67. flexbus->csar2 = CONFIG_SYS_CS2_BASE;
  68. flexbus->cscr2 = CONFIG_SYS_CS2_CTRL;
  69. flexbus->csmr2 = ((CONFIG_SYS_CS2_MASK - 1) & 0xffff0000) | 1;
  70. portcfg->pcfg3 |= CONFIG_SYS_CS2_PORT3_CONFIG;
  71. __asm__ volatile ("sync");
  72. #endif
  73. #if defined (CONFIG_SYS_CS3_BASE)
  74. flexbus->csar3 = CONFIG_SYS_CS3_BASE;
  75. flexbus->cscr3 = CONFIG_SYS_CS3_CTRL;
  76. flexbus->csmr3 = ((CONFIG_SYS_CS3_MASK - 1) & 0xffff0000) | 1;
  77. portcfg->pcfg3 |= CONFIG_SYS_CS3_PORT3_CONFIG;
  78. __asm__ volatile ("sync");
  79. #endif
  80. #if defined (CONFIG_SYS_CS4_BASE)
  81. flexbus->csar4 = CONFIG_SYS_CS4_BASE;
  82. flexbus->cscr4 = CONFIG_SYS_CS4_CTRL;
  83. flexbus->csmr4 = ((CONFIG_SYS_CS4_MASK - 1) & 0xffff0000) | 1;
  84. portcfg->pcfg3 |= CONFIG_SYS_CS4_PORT3_CONFIG;
  85. __asm__ volatile ("sync");
  86. #endif
  87. #if defined (CONFIG_SYS_CS5_BASE)
  88. flexbus->csar5 = CONFIG_SYS_CS5_BASE;
  89. flexbus->cscr5 = CONFIG_SYS_CS5_CTRL;
  90. flexbus->csmr5 = ((CONFIG_SYS_CS5_MASK - 1) & 0xffff0000) | 1;
  91. portcfg->pcfg3 |= CONFIG_SYS_CS5_PORT3_CONFIG;
  92. __asm__ volatile ("sync");
  93. #endif
  94. /* This section of the code cannot place in cpu_init_r(),
  95. it will cause the system to hang */
  96. /* enable timebase */
  97. xlbarb->addrTenTimeOut = 0x1000;
  98. xlbarb->dataTenTimeOut = 0x1000;
  99. xlbarb->busActTimeOut = 0x2000;
  100. xlbarb->config = 0x00002000;
  101. /* Master Priority Enable */
  102. xlbarb->mastPriority = 0;
  103. xlbarb->mastPriEn = 0xff;
  104. }
  105. /*
  106. * initialize higher level parts of CPU like time base and timers
  107. */
  108. int cpu_init_r (void)
  109. {
  110. /* this may belongs to disable interrupt section */
  111. /* mask all interrupts */
  112. *(vu_long *) 0xf0000700 = 0xfffffc00;
  113. *(vu_long *) 0xf0000714 |= 0x0001ffff;
  114. *(vu_long *) 0xf0000710 &= ~0x00000f00;
  115. /* route critical ints to normal ints */
  116. *(vu_long *) 0xf0000710 |= 0x00000001;
  117. #if defined(CONFIG_CMD_NET) && defined(CONFIG_MPC8220_FEC)
  118. /* load FEC microcode */
  119. loadtask (0, 2);
  120. #endif
  121. return (0);
  122. }