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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000 - 2003 Wolfgang Denk <wd@denx.de>
  5. *
  6. * See file CREDITS for list of people who contributed to this
  7. * project.
  8. *
  9. * This program is free software; you can redistribute it and/or
  10. * modify it under the terms of the GNU General Public License as
  11. * published by the Free Software Foundation; either version 2 of
  12. * the License, or (at your option) any later version.
  13. *
  14. * This program is distributed in the hope that it will be useful,
  15. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  16. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  17. * GNU General Public License for more details.
  18. *
  19. * You should have received a copy of the GNU General Public License
  20. * along with this program; if not, write to the Free Software
  21. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  22. * MA 02111-1307 USA
  23. */
  24. /*
  25. * U-Boot - Startup Code for MPC5xxx CPUs
  26. */
  27. #include <config.h>
  28. #include <mpc5xxx.h>
  29. #include <timestamp.h>
  30. #include <version.h>
  31. #define CONFIG_MPC5xxx 1 /* needed for Linux kernel header files */
  32. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  33. #include <ppc_asm.tmpl>
  34. #include <ppc_defs.h>
  35. #include <asm/cache.h>
  36. #include <asm/mmu.h>
  37. #ifndef CONFIG_IDENT_STRING
  38. #define CONFIG_IDENT_STRING ""
  39. #endif
  40. /* We don't want the MMU yet.
  41. */
  42. #undef MSR_KERNEL
  43. /* Floating Point enable, Machine Check and Recoverable Interr. */
  44. #ifdef DEBUG
  45. #define MSR_KERNEL (MSR_FP|MSR_RI)
  46. #else
  47. #define MSR_KERNEL (MSR_FP|MSR_ME|MSR_RI)
  48. #endif
  49. /*
  50. * Set up GOT: Global Offset Table
  51. *
  52. * Use r12 to access the GOT
  53. */
  54. START_GOT
  55. GOT_ENTRY(_GOT2_TABLE_)
  56. GOT_ENTRY(_FIXUP_TABLE_)
  57. GOT_ENTRY(_start)
  58. GOT_ENTRY(_start_of_vectors)
  59. GOT_ENTRY(_end_of_vectors)
  60. GOT_ENTRY(transfer_to_handler)
  61. GOT_ENTRY(__init_end)
  62. GOT_ENTRY(_end)
  63. GOT_ENTRY(__bss_start)
  64. END_GOT
  65. /*
  66. * Version string
  67. */
  68. .data
  69. .globl version_string
  70. version_string:
  71. .ascii U_BOOT_VERSION
  72. .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  73. .ascii CONFIG_IDENT_STRING, "\0"
  74. /*
  75. * Exception vectors
  76. */
  77. .text
  78. . = EXC_OFF_SYS_RESET
  79. .globl _start
  80. _start:
  81. li r21, BOOTFLAG_COLD /* Normal Power-On */
  82. nop
  83. b boot_cold
  84. . = EXC_OFF_SYS_RESET + 0x10
  85. .globl _start_warm
  86. _start_warm:
  87. li r21, BOOTFLAG_WARM /* Software reboot */
  88. b boot_warm
  89. boot_cold:
  90. boot_warm:
  91. mfmsr r5 /* save msr contents */
  92. /* Move CSBoot and adjust instruction pointer */
  93. /*--------------------------------------------------------------*/
  94. #if defined(CONFIG_SYS_LOWBOOT)
  95. # if defined(CONFIG_SYS_RAMBOOT)
  96. # error CONFIG_SYS_LOWBOOT is incompatible with CONFIG_SYS_RAMBOOT
  97. # endif /* CONFIG_SYS_RAMBOOT */
  98. lis r4, CONFIG_SYS_DEFAULT_MBAR@h
  99. lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
  100. ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
  101. stw r3, 0x4(r4) /* CS0 start */
  102. lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
  103. ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
  104. stw r3, 0x8(r4) /* CS0 stop */
  105. lis r3, 0x02010000@h
  106. ori r3, r3, 0x02010000@l
  107. stw r3, 0x54(r4) /* CS0 and Boot enable */
  108. lis r3, lowboot_reentry@h /* jump from bootlow address space (0x0000xxxx) */
  109. ori r3, r3, lowboot_reentry@l /* to the address space the linker used */
  110. mtlr r3
  111. blr
  112. lowboot_reentry:
  113. lis r3, START_REG(CONFIG_SYS_BOOTCS_START)@h
  114. ori r3, r3, START_REG(CONFIG_SYS_BOOTCS_START)@l
  115. stw r3, 0x4c(r4) /* Boot start */
  116. lis r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@h
  117. ori r3, r3, STOP_REG(CONFIG_SYS_BOOTCS_START, CONFIG_SYS_BOOTCS_SIZE)@l
  118. stw r3, 0x50(r4) /* Boot stop */
  119. lis r3, 0x02000001@h
  120. ori r3, r3, 0x02000001@l
  121. stw r3, 0x54(r4) /* Boot enable, CS0 disable */
  122. #endif /* CONFIG_SYS_LOWBOOT */
  123. #if defined(CONFIG_SYS_DEFAULT_MBAR) && !defined(CONFIG_SYS_RAMBOOT)
  124. lis r3, CONFIG_SYS_MBAR@h
  125. ori r3, r3, CONFIG_SYS_MBAR@l
  126. /* MBAR is mirrored into the MBAR SPR */
  127. mtspr MBAR,r3
  128. rlwinm r3, r3, 16, 16, 31
  129. lis r4, CONFIG_SYS_DEFAULT_MBAR@h
  130. stw r3, 0(r4)
  131. #endif /* CONFIG_SYS_DEFAULT_MBAR */
  132. /* Initialise the MPC5xxx processor core */
  133. /*--------------------------------------------------------------*/
  134. bl init_5xxx_core
  135. /* initialize some things that are hard to access from C */
  136. /*--------------------------------------------------------------*/
  137. /* set up stack in on-chip SRAM */
  138. lis r3, CONFIG_SYS_INIT_RAM_ADDR@h
  139. ori r3, r3, CONFIG_SYS_INIT_RAM_ADDR@l
  140. ori r1, r3, CONFIG_SYS_INIT_SP_OFFSET
  141. li r0, 0 /* Make room for stack frame header and */
  142. stwu r0, -4(r1) /* clear final stack frame so that */
  143. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  144. /* let the C-code set up the rest */
  145. /* */
  146. /* Be careful to keep code relocatable ! */
  147. /*--------------------------------------------------------------*/
  148. GET_GOT /* initialize GOT access */
  149. /* r3: IMMR */
  150. bl cpu_init_f /* run low-level CPU init code (in Flash)*/
  151. mr r3, r21
  152. /* r3: BOOTFLAG */
  153. bl board_init_f /* run 1st part of board init code (in Flash)*/
  154. /*
  155. * Vector Table
  156. */
  157. .globl _start_of_vectors
  158. _start_of_vectors:
  159. /* Machine check */
  160. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  161. /* Data Storage exception. */
  162. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  163. /* Instruction Storage exception. */
  164. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  165. /* External Interrupt exception. */
  166. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  167. /* Alignment exception. */
  168. . = 0x600
  169. Alignment:
  170. EXCEPTION_PROLOG(SRR0, SRR1)
  171. mfspr r4,DAR
  172. stw r4,_DAR(r21)
  173. mfspr r5,DSISR
  174. stw r5,_DSISR(r21)
  175. addi r3,r1,STACK_FRAME_OVERHEAD
  176. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  177. /* Program check exception */
  178. . = 0x700
  179. ProgramCheck:
  180. EXCEPTION_PROLOG(SRR0, SRR1)
  181. addi r3,r1,STACK_FRAME_OVERHEAD
  182. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  183. MSR_KERNEL, COPY_EE)
  184. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  185. /* I guess we could implement decrementer, and may have
  186. * to someday for timekeeping.
  187. */
  188. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  189. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  190. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  191. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  192. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  193. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  194. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  195. STD_EXCEPTION(0x1000, InstructionTLBMiss, UnknownException)
  196. STD_EXCEPTION(0x1100, DataLoadTLBMiss, UnknownException)
  197. STD_EXCEPTION(0x1200, DataStoreTLBMiss, UnknownException)
  198. #ifdef DEBUG
  199. . = 0x1300
  200. /*
  201. * This exception occurs when the program counter matches the
  202. * Instruction Address Breakpoint Register (IABR).
  203. *
  204. * I want the cpu to halt if this occurs so I can hunt around
  205. * with the debugger and look at things.
  206. *
  207. * When DEBUG is defined, both machine check enable (in the MSR)
  208. * and checkstop reset enable (in the reset mode register) are
  209. * turned off and so a checkstop condition will result in the cpu
  210. * halting.
  211. *
  212. * I force the cpu into a checkstop condition by putting an illegal
  213. * instruction here (at least this is the theory).
  214. *
  215. * well - that didnt work, so just do an infinite loop!
  216. */
  217. 1: b 1b
  218. #else
  219. STD_EXCEPTION(0x1300, InstructionBreakpoint, DebugException)
  220. #endif
  221. STD_EXCEPTION(0x1400, SMI, UnknownException)
  222. STD_EXCEPTION(0x1500, Trap_15, UnknownException)
  223. STD_EXCEPTION(0x1600, Trap_16, UnknownException)
  224. STD_EXCEPTION(0x1700, Trap_17, UnknownException)
  225. STD_EXCEPTION(0x1800, Trap_18, UnknownException)
  226. STD_EXCEPTION(0x1900, Trap_19, UnknownException)
  227. STD_EXCEPTION(0x1a00, Trap_1a, UnknownException)
  228. STD_EXCEPTION(0x1b00, Trap_1b, UnknownException)
  229. STD_EXCEPTION(0x1c00, Trap_1c, UnknownException)
  230. STD_EXCEPTION(0x1d00, Trap_1d, UnknownException)
  231. STD_EXCEPTION(0x1e00, Trap_1e, UnknownException)
  232. STD_EXCEPTION(0x1f00, Trap_1f, UnknownException)
  233. STD_EXCEPTION(0x2000, Trap_20, UnknownException)
  234. STD_EXCEPTION(0x2100, Trap_21, UnknownException)
  235. STD_EXCEPTION(0x2200, Trap_22, UnknownException)
  236. STD_EXCEPTION(0x2300, Trap_23, UnknownException)
  237. STD_EXCEPTION(0x2400, Trap_24, UnknownException)
  238. STD_EXCEPTION(0x2500, Trap_25, UnknownException)
  239. STD_EXCEPTION(0x2600, Trap_26, UnknownException)
  240. STD_EXCEPTION(0x2700, Trap_27, UnknownException)
  241. STD_EXCEPTION(0x2800, Trap_28, UnknownException)
  242. STD_EXCEPTION(0x2900, Trap_29, UnknownException)
  243. STD_EXCEPTION(0x2a00, Trap_2a, UnknownException)
  244. STD_EXCEPTION(0x2b00, Trap_2b, UnknownException)
  245. STD_EXCEPTION(0x2c00, Trap_2c, UnknownException)
  246. STD_EXCEPTION(0x2d00, Trap_2d, UnknownException)
  247. STD_EXCEPTION(0x2e00, Trap_2e, UnknownException)
  248. STD_EXCEPTION(0x2f00, Trap_2f, UnknownException)
  249. .globl _end_of_vectors
  250. _end_of_vectors:
  251. . = 0x3000
  252. /*
  253. * This code finishes saving the registers to the exception frame
  254. * and jumps to the appropriate handler for the exception.
  255. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  256. */
  257. .globl transfer_to_handler
  258. transfer_to_handler:
  259. stw r22,_NIP(r21)
  260. lis r22,MSR_POW@h
  261. andc r23,r23,r22
  262. stw r23,_MSR(r21)
  263. SAVE_GPR(7, r21)
  264. SAVE_4GPRS(8, r21)
  265. SAVE_8GPRS(12, r21)
  266. SAVE_8GPRS(24, r21)
  267. mflr r23
  268. andi. r24,r23,0x3f00 /* get vector offset */
  269. stw r24,TRAP(r21)
  270. li r22,0
  271. stw r22,RESULT(r21)
  272. lwz r24,0(r23) /* virtual address of handler */
  273. lwz r23,4(r23) /* where to go when done */
  274. mtspr SRR0,r24
  275. mtspr SRR1,r20
  276. mtlr r23
  277. SYNC
  278. rfi /* jump to handler, enable MMU */
  279. int_return:
  280. mfmsr r28 /* Disable interrupts */
  281. li r4,0
  282. ori r4,r4,MSR_EE
  283. andc r28,r28,r4
  284. SYNC /* Some chip revs need this... */
  285. mtmsr r28
  286. SYNC
  287. lwz r2,_CTR(r1)
  288. lwz r0,_LINK(r1)
  289. mtctr r2
  290. mtlr r0
  291. lwz r2,_XER(r1)
  292. lwz r0,_CCR(r1)
  293. mtspr XER,r2
  294. mtcrf 0xFF,r0
  295. REST_10GPRS(3, r1)
  296. REST_10GPRS(13, r1)
  297. REST_8GPRS(23, r1)
  298. REST_GPR(31, r1)
  299. lwz r2,_NIP(r1) /* Restore environment */
  300. lwz r0,_MSR(r1)
  301. mtspr SRR0,r2
  302. mtspr SRR1,r0
  303. lwz r0,GPR0(r1)
  304. lwz r2,GPR2(r1)
  305. lwz r1,GPR1(r1)
  306. SYNC
  307. rfi
  308. /*
  309. * This code initialises the MPC5xxx processor core
  310. * (conforms to PowerPC 603e spec)
  311. * Note: expects original MSR contents to be in r5.
  312. */
  313. .globl init_5xx_core
  314. init_5xxx_core:
  315. /* Initialize machine status; enable machine check interrupt */
  316. /*--------------------------------------------------------------*/
  317. li r3, MSR_KERNEL /* Set ME and RI flags */
  318. rlwimi r3, r5, 0, 25, 25 /* preserve IP bit set by HRCW */
  319. #ifdef DEBUG
  320. rlwimi r3, r5, 0, 21, 22 /* debugger might set SE & BE bits */
  321. #endif
  322. SYNC /* Some chip revs need this... */
  323. mtmsr r3
  324. SYNC
  325. mtspr SRR1, r3 /* Make SRR1 match MSR */
  326. /* Initialize the Hardware Implementation-dependent Registers */
  327. /* HID0 also contains cache control */
  328. /*--------------------------------------------------------------*/
  329. lis r3, CONFIG_SYS_HID0_INIT@h
  330. ori r3, r3, CONFIG_SYS_HID0_INIT@l
  331. SYNC
  332. mtspr HID0, r3
  333. lis r3, CONFIG_SYS_HID0_FINAL@h
  334. ori r3, r3, CONFIG_SYS_HID0_FINAL@l
  335. SYNC
  336. mtspr HID0, r3
  337. /* clear all BAT's */
  338. /*--------------------------------------------------------------*/
  339. li r0, 0
  340. mtspr DBAT0U, r0
  341. mtspr DBAT0L, r0
  342. mtspr DBAT1U, r0
  343. mtspr DBAT1L, r0
  344. mtspr DBAT2U, r0
  345. mtspr DBAT2L, r0
  346. mtspr DBAT3U, r0
  347. mtspr DBAT3L, r0
  348. mtspr DBAT4U, r0
  349. mtspr DBAT4L, r0
  350. mtspr DBAT5U, r0
  351. mtspr DBAT5L, r0
  352. mtspr DBAT6U, r0
  353. mtspr DBAT6L, r0
  354. mtspr DBAT7U, r0
  355. mtspr DBAT7L, r0
  356. mtspr IBAT0U, r0
  357. mtspr IBAT0L, r0
  358. mtspr IBAT1U, r0
  359. mtspr IBAT1L, r0
  360. mtspr IBAT2U, r0
  361. mtspr IBAT2L, r0
  362. mtspr IBAT3U, r0
  363. mtspr IBAT3L, r0
  364. mtspr IBAT4U, r0
  365. mtspr IBAT4L, r0
  366. mtspr IBAT5U, r0
  367. mtspr IBAT5L, r0
  368. mtspr IBAT6U, r0
  369. mtspr IBAT6L, r0
  370. mtspr IBAT7U, r0
  371. mtspr IBAT7L, r0
  372. SYNC
  373. /* invalidate all tlb's */
  374. /* */
  375. /* From the 603e User Manual: "The 603e provides the ability to */
  376. /* invalidate a TLB entry. The TLB Invalidate Entry (tlbie) */
  377. /* instruction invalidates the TLB entry indexed by the EA, and */
  378. /* operates on both the instruction and data TLBs simultaneously*/
  379. /* invalidating four TLB entries (both sets in each TLB). The */
  380. /* index corresponds to bits 15-19 of the EA. To invalidate all */
  381. /* entries within both TLBs, 32 tlbie instructions should be */
  382. /* issued, incrementing this field by one each time." */
  383. /* */
  384. /* "Note that the tlbia instruction is not implemented on the */
  385. /* 603e." */
  386. /* */
  387. /* bits 15-19 correspond to addresses 0x00000000 to 0x0001F000 */
  388. /* incrementing by 0x1000 each time. The code below is sort of */
  389. /* based on code in "flush_tlbs" from arch/powerpc/kernel/head.S */
  390. /* */
  391. /*--------------------------------------------------------------*/
  392. li r3, 32
  393. mtctr r3
  394. li r3, 0
  395. 1: tlbie r3
  396. addi r3, r3, 0x1000
  397. bdnz 1b
  398. SYNC
  399. /* Done! */
  400. /*--------------------------------------------------------------*/
  401. blr
  402. /* Cache functions.
  403. *
  404. * Note: requires that all cache bits in
  405. * HID0 are in the low half word.
  406. */
  407. .globl icache_enable
  408. icache_enable:
  409. mfspr r3, HID0
  410. ori r3, r3, HID0_ICE
  411. lis r4, 0
  412. ori r4, r4, HID0_ILOCK
  413. andc r3, r3, r4
  414. ori r4, r3, HID0_ICFI
  415. isync
  416. mtspr HID0, r4 /* sets enable and invalidate, clears lock */
  417. isync
  418. mtspr HID0, r3 /* clears invalidate */
  419. blr
  420. .globl icache_disable
  421. icache_disable:
  422. mfspr r3, HID0
  423. lis r4, 0
  424. ori r4, r4, HID0_ICE|HID0_ILOCK
  425. andc r3, r3, r4
  426. ori r4, r3, HID0_ICFI
  427. isync
  428. mtspr HID0, r4 /* sets invalidate, clears enable and lock */
  429. isync
  430. mtspr HID0, r3 /* clears invalidate */
  431. blr
  432. .globl icache_status
  433. icache_status:
  434. mfspr r3, HID0
  435. rlwinm r3, r3, HID0_ICE_BITPOS + 1, 31, 31
  436. blr
  437. .globl dcache_enable
  438. dcache_enable:
  439. mfspr r3, HID0
  440. ori r3, r3, HID0_DCE
  441. lis r4, 0
  442. ori r4, r4, HID0_DLOCK
  443. andc r3, r3, r4
  444. ori r4, r3, HID0_DCI
  445. sync
  446. mtspr HID0, r4 /* sets enable and invalidate, clears lock */
  447. sync
  448. mtspr HID0, r3 /* clears invalidate */
  449. blr
  450. .globl dcache_disable
  451. dcache_disable:
  452. mfspr r3, HID0
  453. lis r4, 0
  454. ori r4, r4, HID0_DCE|HID0_DLOCK
  455. andc r3, r3, r4
  456. ori r4, r3, HID0_DCI
  457. sync
  458. mtspr HID0, r4 /* sets invalidate, clears enable and lock */
  459. sync
  460. mtspr HID0, r3 /* clears invalidate */
  461. blr
  462. .globl dcache_status
  463. dcache_status:
  464. mfspr r3, HID0
  465. rlwinm r3, r3, HID0_DCE_BITPOS + 1, 31, 31
  466. blr
  467. .globl get_svr
  468. get_svr:
  469. mfspr r3, SVR
  470. blr
  471. .globl get_pvr
  472. get_pvr:
  473. mfspr r3, PVR
  474. blr
  475. /*------------------------------------------------------------------------------*/
  476. /*
  477. * void relocate_code (addr_sp, gd, addr_moni)
  478. *
  479. * This "function" does not return, instead it continues in RAM
  480. * after relocating the monitor code.
  481. *
  482. * r3 = dest
  483. * r4 = src
  484. * r5 = length in bytes
  485. * r6 = cachelinesize
  486. */
  487. .globl relocate_code
  488. relocate_code:
  489. mr r1, r3 /* Set new stack pointer */
  490. mr r9, r4 /* Save copy of Global Data pointer */
  491. mr r10, r5 /* Save copy of Destination Address */
  492. GET_GOT
  493. mr r3, r5 /* Destination Address */
  494. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  495. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  496. lwz r5, GOT(__init_end)
  497. sub r5, r5, r4
  498. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  499. /*
  500. * Fix GOT pointer:
  501. *
  502. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  503. *
  504. * Offset:
  505. */
  506. sub r15, r10, r4
  507. /* First our own GOT */
  508. add r12, r12, r15
  509. /* then the one used by the C code */
  510. add r30, r30, r15
  511. /*
  512. * Now relocate code
  513. */
  514. cmplw cr1,r3,r4
  515. addi r0,r5,3
  516. srwi. r0,r0,2
  517. beq cr1,4f /* In place copy is not necessary */
  518. beq 7f /* Protect against 0 count */
  519. mtctr r0
  520. bge cr1,2f
  521. la r8,-4(r4)
  522. la r7,-4(r3)
  523. 1: lwzu r0,4(r8)
  524. stwu r0,4(r7)
  525. bdnz 1b
  526. b 4f
  527. 2: slwi r0,r0,2
  528. add r8,r4,r0
  529. add r7,r3,r0
  530. 3: lwzu r0,-4(r8)
  531. stwu r0,-4(r7)
  532. bdnz 3b
  533. /*
  534. * Now flush the cache: note that we must start from a cache aligned
  535. * address. Otherwise we might miss one cache line.
  536. */
  537. 4: cmpwi r6,0
  538. add r5,r3,r5
  539. beq 7f /* Always flush prefetch queue in any case */
  540. subi r0,r6,1
  541. andc r3,r3,r0
  542. mfspr r7,HID0 /* don't do dcbst if dcache is disabled */
  543. rlwinm r7,r7,HID0_DCE_BITPOS+1,31,31
  544. cmpwi r7,0
  545. beq 9f
  546. mr r4,r3
  547. 5: dcbst 0,r4
  548. add r4,r4,r6
  549. cmplw r4,r5
  550. blt 5b
  551. sync /* Wait for all dcbst to complete on bus */
  552. 9: mfspr r7,HID0 /* don't do icbi if icache is disabled */
  553. rlwinm r7,r7,HID0_ICE_BITPOS+1,31,31
  554. cmpwi r7,0
  555. beq 7f
  556. mr r4,r3
  557. 6: icbi 0,r4
  558. add r4,r4,r6
  559. cmplw r4,r5
  560. blt 6b
  561. 7: sync /* Wait for all icbi to complete on bus */
  562. isync
  563. /*
  564. * We are done. Do not return, instead branch to second part of board
  565. * initialization, now running from RAM.
  566. */
  567. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  568. mtlr r0
  569. blr
  570. in_ram:
  571. /*
  572. * Relocation Function, r12 point to got2+0x8000
  573. *
  574. * Adjust got2 pointers, no need to check for 0, this code
  575. * already puts a few entries in the table.
  576. */
  577. li r0,__got2_entries@sectoff@l
  578. la r3,GOT(_GOT2_TABLE_)
  579. lwz r11,GOT(_GOT2_TABLE_)
  580. mtctr r0
  581. sub r11,r3,r11
  582. addi r3,r3,-4
  583. 1: lwzu r0,4(r3)
  584. cmpwi r0,0
  585. beq- 2f
  586. add r0,r0,r11
  587. stw r0,0(r3)
  588. 2: bdnz 1b
  589. /*
  590. * Now adjust the fixups and the pointers to the fixups
  591. * in case we need to move ourselves again.
  592. */
  593. li r0,__fixup_entries@sectoff@l
  594. lwz r3,GOT(_FIXUP_TABLE_)
  595. cmpwi r0,0
  596. mtctr r0
  597. addi r3,r3,-4
  598. beq 4f
  599. 3: lwzu r4,4(r3)
  600. lwzux r0,r4,r11
  601. add r0,r0,r11
  602. stw r10,0(r3)
  603. stw r0,0(r4)
  604. bdnz 3b
  605. 4:
  606. clear_bss:
  607. /*
  608. * Now clear BSS segment
  609. */
  610. lwz r3,GOT(__bss_start)
  611. lwz r4,GOT(_end)
  612. cmplw 0, r3, r4
  613. beq 6f
  614. li r0, 0
  615. 5:
  616. stw r0, 0(r3)
  617. addi r3, r3, 4
  618. cmplw 0, r3, r4
  619. bne 5b
  620. 6:
  621. mr r3, r9 /* Global Data pointer */
  622. mr r4, r10 /* Destination Address */
  623. bl board_init_r
  624. /*
  625. * Copy exception vector code to low memory
  626. *
  627. * r3: dest_addr
  628. * r7: source address, r8: end address, r9: target address
  629. */
  630. .globl trap_init
  631. trap_init:
  632. mflr r4 /* save link register */
  633. GET_GOT
  634. lwz r7, GOT(_start)
  635. lwz r8, GOT(_end_of_vectors)
  636. li r9, 0x100 /* reset vector always at 0x100 */
  637. cmplw 0, r7, r8
  638. bgelr /* return if r7>=r8 - just in case */
  639. 1:
  640. lwz r0, 0(r7)
  641. stw r0, 0(r9)
  642. addi r7, r7, 4
  643. addi r9, r9, 4
  644. cmplw 0, r7, r8
  645. bne 1b
  646. /*
  647. * relocate `hdlr' and `int_return' entries
  648. */
  649. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  650. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  651. 2:
  652. bl trap_reloc
  653. addi r7, r7, 0x100 /* next exception vector */
  654. cmplw 0, r7, r8
  655. blt 2b
  656. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  657. bl trap_reloc
  658. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  659. bl trap_reloc
  660. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  661. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  662. 3:
  663. bl trap_reloc
  664. addi r7, r7, 0x100 /* next exception vector */
  665. cmplw 0, r7, r8
  666. blt 3b
  667. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  668. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  669. 4:
  670. bl trap_reloc
  671. addi r7, r7, 0x100 /* next exception vector */
  672. cmplw 0, r7, r8
  673. blt 4b
  674. mfmsr r3 /* now that the vectors have */
  675. lis r7, MSR_IP@h /* relocated into low memory */
  676. ori r7, r7, MSR_IP@l /* MSR[IP] can be turned off */
  677. andc r3, r3, r7 /* (if it was on) */
  678. SYNC /* Some chip revs need this... */
  679. mtmsr r3
  680. SYNC
  681. mtlr r4 /* restore link register */
  682. blr