pci_mpc5200.c 5.3 KB

123456789101112131415161718192021222324252627282930313233343536373839404142434445464748495051525354555657585960616263646566676869707172737475767778798081828384858687888990919293949596979899100101102103104105106107108109110111112113114115116117118119120121122123124125126127128129130131132133134135136137138139140141142143144145146147148149150151152153154155156157158159160161162163164165166167168169170171172173174175176177178179180181182183184185186187
  1. /*
  2. * (C) Copyright 2000-2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. #if defined(CONFIG_PCI)
  25. #include <asm/processor.h>
  26. #include <asm/io.h>
  27. #include <pci.h>
  28. #include <mpc5xxx.h>
  29. /* System RAM mapped over PCI */
  30. #define CONFIG_PCI_MEMORY_BUS CONFIG_SYS_SDRAM_BASE
  31. #define CONFIG_PCI_MEMORY_PHYS CONFIG_SYS_SDRAM_BASE
  32. #define CONFIG_PCI_MEMORY_SIZE (1024 * 1024 * 1024)
  33. /* PCIIWCR bit fields */
  34. #define IWCR_MEM (0 << 3)
  35. #define IWCR_IO (1 << 3)
  36. #define IWCR_READ (0 << 1)
  37. #define IWCR_READLINE (1 << 1)
  38. #define IWCR_READMULT (2 << 1)
  39. #define IWCR_EN (1 << 0)
  40. static int mpc5200_read_config_dword(struct pci_controller *hose,
  41. pci_dev_t dev, int offset, u32* value)
  42. {
  43. *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
  44. eieio();
  45. udelay(10);
  46. #if (defined CONFIG_PF5200 || defined CONFIG_CPCI5200)
  47. if (dev & 0x00ff0000) {
  48. u32 val;
  49. val = in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+2));
  50. udelay(10);
  51. val = val << 16;
  52. val |= in_le16((volatile u16 *)(CONFIG_PCI_IO_PHYS+0));
  53. *value = val;
  54. } else {
  55. *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
  56. }
  57. udelay(10);
  58. #else
  59. *value = in_le32((volatile u32 *)CONFIG_PCI_IO_PHYS);
  60. #endif
  61. eieio();
  62. *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
  63. udelay(10);
  64. return 0;
  65. }
  66. static int mpc5200_write_config_dword(struct pci_controller *hose,
  67. pci_dev_t dev, int offset, u32 value)
  68. {
  69. *(volatile u32 *)MPC5XXX_PCI_CAR = (1 << 31) | dev | offset;
  70. eieio();
  71. udelay(10);
  72. out_le32((volatile u32 *)CONFIG_PCI_IO_PHYS, value);
  73. eieio();
  74. *(volatile u32 *)MPC5XXX_PCI_CAR = 0;
  75. udelay(10);
  76. return 0;
  77. }
  78. void pci_mpc5xxx_init (struct pci_controller *hose)
  79. {
  80. hose->first_busno = 0;
  81. hose->last_busno = 0xff;
  82. /* System space */
  83. pci_set_region(hose->regions + 0,
  84. CONFIG_PCI_MEMORY_BUS,
  85. CONFIG_PCI_MEMORY_PHYS,
  86. CONFIG_PCI_MEMORY_SIZE,
  87. PCI_REGION_MEM | PCI_REGION_SYS_MEMORY);
  88. /* PCI memory space */
  89. pci_set_region(hose->regions + 1,
  90. CONFIG_PCI_MEM_BUS,
  91. CONFIG_PCI_MEM_PHYS,
  92. CONFIG_PCI_MEM_SIZE,
  93. PCI_REGION_MEM);
  94. /* PCI IO space */
  95. pci_set_region(hose->regions + 2,
  96. CONFIG_PCI_IO_BUS,
  97. CONFIG_PCI_IO_PHYS,
  98. CONFIG_PCI_IO_SIZE,
  99. PCI_REGION_IO);
  100. hose->region_count = 3;
  101. pci_register_hose(hose);
  102. /* GPIO Multiplexing - enable PCI */
  103. *(vu_long *)MPC5XXX_GPS_PORT_CONFIG &= ~(1 << 15);
  104. /* Set host bridge as pci master and enable memory decoding */
  105. *(vu_long *)MPC5XXX_PCI_CMD |=
  106. PCI_COMMAND_MASTER | PCI_COMMAND_MEMORY;
  107. /* Set maximum latency timer */
  108. *(vu_long *)MPC5XXX_PCI_CFG |= (0xf800);
  109. /* Set cache line size */
  110. *(vu_long *)MPC5XXX_PCI_CFG = (*(vu_long *)MPC5XXX_PCI_CFG & ~0xff) |
  111. (CONFIG_SYS_CACHELINE_SIZE / 4);
  112. /* Map MBAR to PCI space */
  113. *(vu_long *)MPC5XXX_PCI_BAR0 = CONFIG_SYS_MBAR;
  114. *(vu_long *)MPC5XXX_PCI_TBATR0 = CONFIG_SYS_MBAR | 1;
  115. /* Map RAM to PCI space */
  116. *(vu_long *)MPC5XXX_PCI_BAR1 = CONFIG_PCI_MEMORY_BUS | (1 << 3);
  117. *(vu_long *)MPC5XXX_PCI_TBATR1 = CONFIG_PCI_MEMORY_PHYS | 1;
  118. /* Park XLB on PCI */
  119. *(vu_long *)(MPC5XXX_XLBARB + 0x40) &= ~((7 << 8) | (3 << 5));
  120. *(vu_long *)(MPC5XXX_XLBARB + 0x40) |= (3 << 8) | (3 << 5);
  121. /* Disable interrupts from PCI controller */
  122. *(vu_long *)MPC5XXX_PCI_GSCR &= ~(7 << 12);
  123. *(vu_long *)MPC5XXX_PCI_ICR &= ~(7 << 24);
  124. /* Set PCI retry counter to 0 = infinite retry. */
  125. /* The default of 255 is too short for slow devices. */
  126. *(vu_long *)MPC5XXX_PCI_ICR &= 0xFFFFFF00;
  127. /* Disable initiator windows */
  128. *(vu_long *)MPC5XXX_PCI_IWCR = 0;
  129. /* Map PCI memory to physical space */
  130. *(vu_long *)MPC5XXX_PCI_IW0BTAR = CONFIG_PCI_MEM_PHYS |
  131. (((CONFIG_PCI_MEM_SIZE - 1) >> 8) & 0x00ff0000) |
  132. (CONFIG_PCI_MEM_BUS >> 16);
  133. *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_MEM | IWCR_READ | IWCR_EN) << 24;
  134. /* Map PCI I/O to physical space */
  135. *(vu_long *)MPC5XXX_PCI_IW1BTAR = CONFIG_PCI_IO_PHYS |
  136. (((CONFIG_PCI_IO_SIZE - 1) >> 8) & 0x00ff0000) |
  137. (CONFIG_PCI_IO_BUS >> 16);
  138. *(vu_long *)MPC5XXX_PCI_IWCR |= (IWCR_IO | IWCR_READ | IWCR_EN) << 16;
  139. /* Reset the PCI bus */
  140. *(vu_long *)MPC5XXX_PCI_GSCR |= 1;
  141. udelay(1000);
  142. *(vu_long *)MPC5XXX_PCI_GSCR &= ~1;
  143. udelay(1000);
  144. pci_set_ops(hose,
  145. pci_hose_read_config_byte_via_dword,
  146. pci_hose_read_config_word_via_dword,
  147. mpc5200_read_config_dword,
  148. pci_hose_write_config_byte_via_dword,
  149. pci_hose_write_config_word_via_dword,
  150. mpc5200_write_config_dword);
  151. udelay(1000);
  152. #ifdef CONFIG_PCI_SCAN_SHOW
  153. printf("PCI: Bus Dev VenId DevId Class Int\n");
  154. #endif
  155. hose->last_busno = pci_hose_scan(hose);
  156. }
  157. #endif /* CONFIG_PCI */