i2c.c 9.4 KB

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  1. /*
  2. * (C) Copyright 2003
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. */
  23. #include <common.h>
  24. DECLARE_GLOBAL_DATA_PTR;
  25. #ifdef CONFIG_HARD_I2C
  26. #include <mpc5xxx.h>
  27. #include <i2c.h>
  28. #if (CONFIG_SYS_I2C_MODULE == 2)
  29. #define I2C_BASE MPC5XXX_I2C2
  30. #elif (CONFIG_SYS_I2C_MODULE == 1)
  31. #define I2C_BASE MPC5XXX_I2C1
  32. #else
  33. #error CONFIG_SYS_I2C_MODULE is not properly configured
  34. #endif
  35. #define I2C_TIMEOUT 6667
  36. #define I2C_RETRIES 3
  37. struct mpc5xxx_i2c_tap {
  38. int scl2tap;
  39. int tap2tap;
  40. };
  41. static int mpc_reg_in (volatile u32 *reg);
  42. static void mpc_reg_out (volatile u32 *reg, int val, int mask);
  43. static int wait_for_bb (void);
  44. static int wait_for_pin (int *status);
  45. static int do_address (uchar chip, char rdwr_flag);
  46. static int send_bytes (uchar chip, char *buf, int len);
  47. static int receive_bytes (uchar chip, char *buf, int len);
  48. static int mpc_get_fdr (int);
  49. static int mpc_reg_in(volatile u32 *reg)
  50. {
  51. int ret = *reg >> 24;
  52. __asm__ __volatile__ ("eieio");
  53. return ret;
  54. }
  55. static void mpc_reg_out(volatile u32 *reg, int val, int mask)
  56. {
  57. int tmp;
  58. if (!mask) {
  59. *reg = val << 24;
  60. } else {
  61. tmp = mpc_reg_in(reg);
  62. *reg = ((tmp & ~mask) | (val & mask)) << 24;
  63. }
  64. __asm__ __volatile__ ("eieio");
  65. return;
  66. }
  67. static int wait_for_bb(void)
  68. {
  69. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  70. int timeout = I2C_TIMEOUT;
  71. int status;
  72. status = mpc_reg_in(&regs->msr);
  73. while (timeout-- && (status & I2C_BB)) {
  74. #if 1
  75. volatile int temp;
  76. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  77. temp = mpc_reg_in(&regs->mdr);
  78. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  79. mpc_reg_out(&regs->mcr, 0, 0);
  80. mpc_reg_out(&regs->mcr, I2C_EN, 0);
  81. #endif
  82. udelay(15);
  83. status = mpc_reg_in(&regs->msr);
  84. }
  85. return (status & I2C_BB);
  86. }
  87. static int wait_for_pin(int *status)
  88. {
  89. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  90. int timeout = I2C_TIMEOUT;
  91. *status = mpc_reg_in(&regs->msr);
  92. while (timeout-- && !(*status & I2C_IF)) {
  93. udelay(15);
  94. *status = mpc_reg_in(&regs->msr);
  95. }
  96. if (!(*status & I2C_IF)) {
  97. return -1;
  98. }
  99. mpc_reg_out(&regs->msr, 0, I2C_IF);
  100. return 0;
  101. }
  102. static int do_address(uchar chip, char rdwr_flag)
  103. {
  104. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  105. int status;
  106. chip <<= 1;
  107. if (rdwr_flag) {
  108. chip |= 1;
  109. }
  110. mpc_reg_out(&regs->mcr, I2C_TX, I2C_TX);
  111. mpc_reg_out(&regs->mdr, chip, 0);
  112. if (wait_for_pin(&status)) {
  113. return -2;
  114. }
  115. if (status & I2C_RXAK) {
  116. return -3;
  117. }
  118. return 0;
  119. }
  120. static int send_bytes(uchar chip, char *buf, int len)
  121. {
  122. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  123. int wrcount;
  124. int status;
  125. for (wrcount = 0; wrcount < len; ++wrcount) {
  126. mpc_reg_out(&regs->mdr, buf[wrcount], 0);
  127. if (wait_for_pin(&status)) {
  128. break;
  129. }
  130. if (status & I2C_RXAK) {
  131. break;
  132. }
  133. }
  134. return !(wrcount == len);
  135. }
  136. static int receive_bytes(uchar chip, char *buf, int len)
  137. {
  138. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  139. int dummy = 1;
  140. int rdcount = 0;
  141. int status;
  142. int i;
  143. mpc_reg_out(&regs->mcr, 0, I2C_TX);
  144. for (i = 0; i < len; ++i) {
  145. buf[rdcount] = mpc_reg_in(&regs->mdr);
  146. if (dummy) {
  147. dummy = 0;
  148. } else {
  149. rdcount++;
  150. }
  151. if (wait_for_pin(&status)) {
  152. return -4;
  153. }
  154. }
  155. mpc_reg_out(&regs->mcr, I2C_TXAK, I2C_TXAK);
  156. buf[rdcount++] = mpc_reg_in(&regs->mdr);
  157. if (wait_for_pin(&status)) {
  158. return -5;
  159. }
  160. mpc_reg_out(&regs->mcr, 0, I2C_TXAK);
  161. return 0;
  162. }
  163. #if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
  164. #define FDR510(x) (u8) (((x & 0x20) >> 3) | (x & 0x3))
  165. #define FDR432(x) (u8) ((x & 0x1C) >> 2)
  166. /*
  167. * Reset any i2c devices that may have been interrupted during a system reset.
  168. * Normally this would be accomplished by clocking the line until SCL and SDA
  169. * are released and then sending a start condtiion (From an Atmel datasheet).
  170. * There is no direct access to the i2c pins so instead create start commands
  171. * through the i2c interface. Send a start command then delay for the SDA Hold
  172. * time, repeat this by disabling/enabling the bus a total of 9 times.
  173. */
  174. static void send_reset(void)
  175. {
  176. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  177. int i;
  178. u32 delay;
  179. u8 fdr;
  180. int SDA_Tap[] = { 3, 3, 4, 4, 1, 1, 2, 2};
  181. struct mpc5xxx_i2c_tap scltap[] = {
  182. {4, 1},
  183. {4, 2},
  184. {6, 4},
  185. {6, 8},
  186. {14, 16},
  187. {30, 32},
  188. {62, 64},
  189. {126, 128}
  190. };
  191. fdr = (u8)mpc_reg_in(&regs->mfdr);
  192. delay = scltap[FDR432(fdr)].scl2tap + ((SDA_Tap[FDR510(fdr)] - 1) * \
  193. scltap[FDR432(fdr)].tap2tap) + 3;
  194. for (i = 0; i < 9; i++) {
  195. mpc_reg_out(&regs->mcr, I2C_EN|I2C_STA|I2C_TX, I2C_INIT_MASK);
  196. udelay(delay);
  197. mpc_reg_out(&regs->mcr, 0, I2C_INIT_MASK);
  198. udelay(delay);
  199. }
  200. mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK);
  201. }
  202. #endif /* CONFIG_SYS_I2c_INIT_MPC5XXX */
  203. /**************** I2C API ****************/
  204. void i2c_init(int speed, int saddr)
  205. {
  206. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  207. mpc_reg_out(&regs->mcr, 0, 0);
  208. mpc_reg_out(&regs->madr, saddr << 1, 0);
  209. /* Set clock
  210. */
  211. mpc_reg_out(&regs->mfdr, mpc_get_fdr(speed), 0);
  212. /* Enable module
  213. */
  214. mpc_reg_out(&regs->mcr, I2C_EN, I2C_INIT_MASK);
  215. mpc_reg_out(&regs->msr, 0, I2C_IF);
  216. #if defined(CONFIG_SYS_I2C_INIT_MPC5XXX)
  217. send_reset();
  218. #endif
  219. return;
  220. }
  221. static int mpc_get_fdr(int speed)
  222. {
  223. static int fdr = -1;
  224. if (fdr == -1) {
  225. ulong best_speed = 0;
  226. ulong divider;
  227. ulong ipb, scl;
  228. ulong bestmatch = 0xffffffffUL;
  229. int best_i = 0, best_j = 0, i, j;
  230. int SCL_Tap[] = { 9, 10, 12, 15, 5, 6, 7, 8};
  231. struct mpc5xxx_i2c_tap scltap[] = {
  232. {4, 1},
  233. {4, 2},
  234. {6, 4},
  235. {6, 8},
  236. {14, 16},
  237. {30, 32},
  238. {62, 64},
  239. {126, 128}
  240. };
  241. ipb = gd->ipb_clk;
  242. for (i = 7; i >= 0; i--) {
  243. for (j = 7; j >= 0; j--) {
  244. scl = 2 * (scltap[j].scl2tap +
  245. (SCL_Tap[i] - 1) * scltap[j].tap2tap + 2);
  246. if (ipb <= speed*scl) {
  247. if ((speed*scl - ipb) < bestmatch) {
  248. bestmatch = speed*scl - ipb;
  249. best_i = i;
  250. best_j = j;
  251. best_speed = ipb/scl;
  252. }
  253. }
  254. }
  255. }
  256. divider = (best_i & 3) | ((best_i & 4) << 3) | (best_j << 2);
  257. if (gd->flags & GD_FLG_RELOC) {
  258. fdr = divider;
  259. } else {
  260. if (gd->have_console)
  261. printf("%ld kHz, ", best_speed / 1000);
  262. return divider;
  263. }
  264. }
  265. return fdr;
  266. }
  267. int i2c_probe(uchar chip)
  268. {
  269. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  270. int i;
  271. for (i = 0; i < I2C_RETRIES; i++) {
  272. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  273. if (! do_address(chip, 0)) {
  274. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  275. udelay(500);
  276. break;
  277. }
  278. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  279. udelay(500);
  280. }
  281. return (i == I2C_RETRIES);
  282. }
  283. int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len)
  284. {
  285. char xaddr[4];
  286. struct mpc5xxx_i2c * regs = (struct mpc5xxx_i2c *)I2C_BASE;
  287. int ret = -1;
  288. xaddr[0] = (addr >> 24) & 0xFF;
  289. xaddr[1] = (addr >> 16) & 0xFF;
  290. xaddr[2] = (addr >> 8) & 0xFF;
  291. xaddr[3] = addr & 0xFF;
  292. if (wait_for_bb()) {
  293. if (gd->have_console)
  294. printf("i2c_read: bus is busy\n");
  295. goto Done;
  296. }
  297. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  298. if (do_address(chip, 0)) {
  299. if (gd->have_console)
  300. printf("i2c_read: failed to address chip\n");
  301. goto Done;
  302. }
  303. if (send_bytes(chip, &xaddr[4-alen], alen)) {
  304. if (gd->have_console)
  305. printf("i2c_read: send_bytes failed\n");
  306. goto Done;
  307. }
  308. mpc_reg_out(&regs->mcr, I2C_RSTA, I2C_RSTA);
  309. if (do_address(chip, 1)) {
  310. if (gd->have_console)
  311. printf("i2c_read: failed to address chip\n");
  312. goto Done;
  313. }
  314. if (receive_bytes(chip, (char *)buf, len)) {
  315. if (gd->have_console)
  316. printf("i2c_read: receive_bytes failed\n");
  317. goto Done;
  318. }
  319. ret = 0;
  320. Done:
  321. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  322. return ret;
  323. }
  324. int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len)
  325. {
  326. char xaddr[4];
  327. struct mpc5xxx_i2c *regs = (struct mpc5xxx_i2c *)I2C_BASE;
  328. int ret = -1;
  329. xaddr[0] = (addr >> 24) & 0xFF;
  330. xaddr[1] = (addr >> 16) & 0xFF;
  331. xaddr[2] = (addr >> 8) & 0xFF;
  332. xaddr[3] = addr & 0xFF;
  333. if (wait_for_bb()) {
  334. if (gd->have_console)
  335. printf("i2c_write: bus is busy\n");
  336. goto Done;
  337. }
  338. mpc_reg_out(&regs->mcr, I2C_STA, I2C_STA);
  339. if (do_address(chip, 0)) {
  340. if (gd->have_console)
  341. printf("i2c_write: failed to address chip\n");
  342. goto Done;
  343. }
  344. if (send_bytes(chip, &xaddr[4-alen], alen)) {
  345. if (gd->have_console)
  346. printf("i2c_write: send_bytes failed\n");
  347. goto Done;
  348. }
  349. if (send_bytes(chip, (char *)buf, len)) {
  350. if (gd->have_console)
  351. printf("i2c_write: send_bytes failed\n");
  352. goto Done;
  353. }
  354. ret = 0;
  355. Done:
  356. mpc_reg_out(&regs->mcr, 0, I2C_STA);
  357. return ret;
  358. }
  359. #endif /* CONFIG_HARD_I2C */