start.S 13 KB

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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000, 2001, 2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright (C) 2003 Martin Winistoerfer, martinwinistoerfer@gmx.ch.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /*
  26. * File: start.S
  27. *
  28. * Discription: startup code
  29. *
  30. */
  31. #include <config.h>
  32. #include <mpc5xx.h>
  33. #include <timestamp.h>
  34. #include <version.h>
  35. #define CONFIG_5xx 1 /* needed for Linux kernel header files */
  36. #define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */
  37. #include <ppc_asm.tmpl>
  38. #include <ppc_defs.h>
  39. #include <linux/config.h>
  40. #include <asm/processor.h>
  41. #ifndef CONFIG_IDENT_STRING
  42. #define CONFIG_IDENT_STRING ""
  43. #endif
  44. /* We don't have a MMU.
  45. */
  46. #undef MSR_KERNEL
  47. #define MSR_KERNEL ( MSR_ME | MSR_RI ) /* Machine Check and Recoverable Interr. */
  48. /*
  49. * Set up GOT: Global Offset Table
  50. *
  51. * Use r12 to access the GOT
  52. */
  53. START_GOT
  54. GOT_ENTRY(_GOT2_TABLE_)
  55. GOT_ENTRY(_FIXUP_TABLE_)
  56. GOT_ENTRY(_start)
  57. GOT_ENTRY(_start_of_vectors)
  58. GOT_ENTRY(_end_of_vectors)
  59. GOT_ENTRY(transfer_to_handler)
  60. GOT_ENTRY(__init_end)
  61. GOT_ENTRY(_end)
  62. GOT_ENTRY(__bss_start)
  63. END_GOT
  64. /*
  65. * r3 - 1st arg to board_init(): IMMP pointer
  66. * r4 - 2nd arg to board_init(): boot flag
  67. */
  68. .text
  69. .long 0x27051956 /* U-Boot Magic Number */
  70. .globl version_string
  71. version_string:
  72. .ascii U_BOOT_VERSION
  73. .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  74. .ascii CONFIG_IDENT_STRING, "\0"
  75. . = EXC_OFF_SYS_RESET
  76. .globl _start
  77. _start:
  78. mfspr r3, 638
  79. li r4, CONFIG_SYS_ISB /* Set ISB bit */
  80. or r3, r3, r4
  81. mtspr 638, r3
  82. li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
  83. b boot_cold
  84. . = EXC_OFF_SYS_RESET + 0x20
  85. .globl _start_warm
  86. _start_warm:
  87. li r21, BOOTFLAG_WARM /* Software reboot */
  88. b boot_warm
  89. boot_cold:
  90. boot_warm:
  91. /* Initialize machine status; enable machine check interrupt */
  92. /*----------------------------------------------------------------------*/
  93. li r3, MSR_KERNEL /* Set ME, RI flags */
  94. mtmsr r3
  95. mtspr SRR1, r3 /* Make SRR1 match MSR */
  96. /* Initialize debug port registers */
  97. /*----------------------------------------------------------------------*/
  98. xor r0, r0, r0 /* Clear R0 */
  99. mtspr LCTRL1, r0 /* Initialize debug port regs */
  100. mtspr LCTRL2, r0
  101. mtspr COUNTA, r0
  102. mtspr COUNTB, r0
  103. #if defined(CONFIG_PATI)
  104. /* the external flash access on PATI fails if programming the PLL to 40MHz.
  105. * Copy the PLL programming code to the internal RAM and execute it
  106. *----------------------------------------------------------------------*/
  107. lis r3, CONFIG_SYS_MONITOR_BASE@h
  108. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  109. addi r3, r3, pll_prog_code_start - _start + EXC_OFF_SYS_RESET
  110. lis r4, CONFIG_SYS_INIT_RAM_ADDR@h
  111. ori r4, r4, CONFIG_SYS_INIT_RAM_ADDR@l
  112. mtlr r4
  113. addis r5,0,0x0
  114. ori r5,r5,((pll_prog_code_end - pll_prog_code_start) >>2)
  115. mtctr r5
  116. addi r3, r3, -4
  117. addi r4, r4, -4
  118. 0:
  119. lwzu r0,4(r3)
  120. stwu r0,4(r4)
  121. bdnz 0b /* copy loop */
  122. blrl
  123. #endif
  124. /*
  125. * Calculate absolute address in FLASH and jump there
  126. *----------------------------------------------------------------------*/
  127. lis r3, CONFIG_SYS_MONITOR_BASE@h
  128. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  129. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  130. mtlr r3
  131. blr
  132. in_flash:
  133. /* Initialize some SPRs that are hard to access from C */
  134. /*----------------------------------------------------------------------*/
  135. lis r3, CONFIG_SYS_IMMR@h /* Pass IMMR as arg1 to C routine */
  136. lis r2, CONFIG_SYS_INIT_SP_ADDR@h
  137. ori r1, r2, CONFIG_SYS_INIT_SP_ADDR@l /* Set up the stack in internal SRAM */
  138. /* Note: R0 is still 0 here */
  139. stwu r0, -4(r1) /* Clear final stack frame so that */
  140. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  141. /*
  142. * Disable serialized ifetch and show cycles
  143. * (i.e. set processor to normal mode) for maximum
  144. * performance.
  145. */
  146. li r2, 0x0007
  147. mtspr ICTRL, r2
  148. /* Set up debug mode entry */
  149. lis r2, CONFIG_SYS_DER@h
  150. ori r2, r2, CONFIG_SYS_DER@l
  151. mtspr DER, r2
  152. /* Let the C-code set up the rest */
  153. /* */
  154. /* Be careful to keep code relocatable ! */
  155. /*----------------------------------------------------------------------*/
  156. GET_GOT /* initialize GOT access */
  157. /* r3: IMMR */
  158. bl cpu_init_f /* run low-level CPU init code (from Flash) */
  159. mr r3, r21
  160. /* r3: BOOTFLAG */
  161. bl board_init_f /* run 1st part of board init code (from Flash) */
  162. .globl _start_of_vectors
  163. _start_of_vectors:
  164. /* Machine check */
  165. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  166. /* Data Storage exception. "Never" generated on the 860. */
  167. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  168. /* Instruction Storage exception. "Never" generated on the 860. */
  169. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  170. /* External Interrupt exception. */
  171. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  172. /* Alignment exception. */
  173. . = 0x600
  174. Alignment:
  175. EXCEPTION_PROLOG(SRR0, SRR1)
  176. mfspr r4,DAR
  177. stw r4,_DAR(r21)
  178. mfspr r5,DSISR
  179. stw r5,_DSISR(r21)
  180. addi r3,r1,STACK_FRAME_OVERHEAD
  181. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  182. /* Program check exception */
  183. . = 0x700
  184. ProgramCheck:
  185. EXCEPTION_PROLOG(SRR0, SRR1)
  186. addi r3,r1,STACK_FRAME_OVERHEAD
  187. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  188. MSR_KERNEL, COPY_EE)
  189. /* FPU on MPC5xx available. We will use it later.
  190. */
  191. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  192. /* I guess we could implement decrementer, and may have
  193. * to someday for timekeeping.
  194. */
  195. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  196. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  197. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  198. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  199. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  200. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  201. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  202. /* On the MPC8xx, this is a software emulation interrupt. It occurs
  203. * for all unimplemented and illegal instructions.
  204. */
  205. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  206. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  207. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  208. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  209. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  210. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  211. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  212. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  213. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  214. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  215. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  216. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  217. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  218. STD_EXCEPTION(0x1d00, InstructionBreakpoint, DebugException)
  219. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  220. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  221. .globl _end_of_vectors
  222. _end_of_vectors:
  223. . = 0x2000
  224. /*
  225. * This code finishes saving the registers to the exception frame
  226. * and jumps to the appropriate handler for the exception.
  227. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  228. */
  229. .globl transfer_to_handler
  230. transfer_to_handler:
  231. stw r22,_NIP(r21)
  232. lis r22,MSR_POW@h
  233. andc r23,r23,r22
  234. stw r23,_MSR(r21)
  235. SAVE_GPR(7, r21)
  236. SAVE_4GPRS(8, r21)
  237. SAVE_8GPRS(12, r21)
  238. SAVE_8GPRS(24, r21)
  239. mflr r23
  240. andi. r24,r23,0x3f00 /* get vector offset */
  241. stw r24,TRAP(r21)
  242. li r22,0
  243. stw r22,RESULT(r21)
  244. mtspr SPRG2,r22 /* r1 is now kernel sp */
  245. lwz r24,0(r23) /* virtual address of handler */
  246. lwz r23,4(r23) /* where to go when done */
  247. mtspr SRR0,r24
  248. mtspr SRR1,r20
  249. mtlr r23
  250. SYNC
  251. rfi /* jump to handler, enable MMU */
  252. int_return:
  253. mfmsr r28 /* Disable interrupts */
  254. li r4,0
  255. ori r4,r4,MSR_EE
  256. andc r28,r28,r4
  257. SYNC /* Some chip revs need this... */
  258. mtmsr r28
  259. SYNC
  260. lwz r2,_CTR(r1)
  261. lwz r0,_LINK(r1)
  262. mtctr r2
  263. mtlr r0
  264. lwz r2,_XER(r1)
  265. lwz r0,_CCR(r1)
  266. mtspr XER,r2
  267. mtcrf 0xFF,r0
  268. REST_10GPRS(3, r1)
  269. REST_10GPRS(13, r1)
  270. REST_8GPRS(23, r1)
  271. REST_GPR(31, r1)
  272. lwz r2,_NIP(r1) /* Restore environment */
  273. lwz r0,_MSR(r1)
  274. mtspr SRR0,r2
  275. mtspr SRR1,r0
  276. lwz r0,GPR0(r1)
  277. lwz r2,GPR2(r1)
  278. lwz r1,GPR1(r1)
  279. SYNC
  280. rfi
  281. /*
  282. * unsigned int get_immr (unsigned int mask)
  283. *
  284. * return (mask ? (IMMR & mask) : IMMR);
  285. */
  286. .globl get_immr
  287. get_immr:
  288. mr r4,r3 /* save mask */
  289. mfspr r3, IMMR /* IMMR */
  290. cmpwi 0,r4,0 /* mask != 0 ? */
  291. beq 4f
  292. and r3,r3,r4 /* IMMR & mask */
  293. 4:
  294. blr
  295. .globl get_pvr
  296. get_pvr:
  297. mfspr r3, PVR
  298. blr
  299. /*------------------------------------------------------------------------------*/
  300. /*
  301. * void relocate_code (addr_sp, gd, addr_moni)
  302. *
  303. * This "function" does not return, instead it continues in RAM
  304. * after relocating the monitor code.
  305. *
  306. * r3 = dest
  307. * r4 = src
  308. * r5 = length in bytes
  309. * r6 = cachelinesize
  310. */
  311. .globl relocate_code
  312. relocate_code:
  313. mr r1, r3 /* Set new stack pointer in SRAM */
  314. mr r9, r4 /* Save copy of global data pointer in SRAM */
  315. mr r10, r5 /* Save copy of monitor destination Address in SRAM */
  316. GET_GOT
  317. mr r3, r5 /* Destination Address */
  318. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  319. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  320. lwz r5, GOT(__init_end)
  321. sub r5, r5, r4
  322. /*
  323. * Fix GOT pointer:
  324. *
  325. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  326. *
  327. * Offset:
  328. */
  329. sub r15, r10, r4
  330. /* First our own GOT */
  331. add r12, r12, r15
  332. /* the the one used by the C code */
  333. add r30, r30, r15
  334. /*
  335. * Now relocate code
  336. */
  337. cmplw cr1,r3,r4
  338. addi r0,r5,3
  339. srwi. r0,r0,2
  340. beq cr1,4f /* In place copy is not necessary */
  341. beq 4f /* Protect against 0 count */
  342. mtctr r0
  343. bge cr1,2f
  344. la r8,-4(r4)
  345. la r7,-4(r3)
  346. 1: lwzu r0,4(r8)
  347. stwu r0,4(r7)
  348. bdnz 1b
  349. b 4f
  350. 2: slwi r0,r0,2
  351. add r8,r4,r0
  352. add r7,r3,r0
  353. 3: lwzu r0,-4(r8)
  354. stwu r0,-4(r7)
  355. bdnz 3b
  356. 4: sync
  357. isync
  358. /*
  359. * We are done. Do not return, instead branch to second part of board
  360. * initialization, now running from RAM.
  361. */
  362. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  363. mtlr r0
  364. blr
  365. in_ram:
  366. /*
  367. * Relocation Function, r12 point to got2+0x8000
  368. *
  369. * Adjust got2 pointers, no need to check for 0, this code
  370. * already puts a few entries in the table.
  371. */
  372. li r0,__got2_entries@sectoff@l
  373. la r3,GOT(_GOT2_TABLE_)
  374. lwz r11,GOT(_GOT2_TABLE_)
  375. mtctr r0
  376. sub r11,r3,r11
  377. addi r3,r3,-4
  378. 1: lwzu r0,4(r3)
  379. cmpwi r0,0
  380. beq- 2f
  381. add r0,r0,r11
  382. stw r0,0(r3)
  383. 2: bdnz 1b
  384. /*
  385. * Now adjust the fixups and the pointers to the fixups
  386. * in case we need to move ourselves again.
  387. */
  388. li r0,__fixup_entries@sectoff@l
  389. lwz r3,GOT(_FIXUP_TABLE_)
  390. cmpwi r0,0
  391. mtctr r0
  392. addi r3,r3,-4
  393. beq 4f
  394. 3: lwzu r4,4(r3)
  395. lwzux r0,r4,r11
  396. add r0,r0,r11
  397. stw r10,0(r3)
  398. stw r0,0(r4)
  399. bdnz 3b
  400. 4:
  401. clear_bss:
  402. /*
  403. * Now clear BSS segment
  404. */
  405. lwz r3,GOT(__bss_start)
  406. lwz r4,GOT(_end)
  407. cmplw 0, r3, r4
  408. beq 6f
  409. li r0, 0
  410. 5:
  411. stw r0, 0(r3)
  412. addi r3, r3, 4
  413. cmplw 0, r3, r4
  414. bne 5b
  415. 6:
  416. mr r3, r9 /* Global Data pointer */
  417. mr r4, r10 /* Destination Address */
  418. bl board_init_r
  419. /*
  420. * Copy exception vector code to low memory
  421. *
  422. * r3: dest_addr
  423. * r7: source address, r8: end address, r9: target address
  424. */
  425. .globl trap_init
  426. trap_init:
  427. mflr r4 /* save link register */
  428. GET_GOT
  429. lwz r7, GOT(_start)
  430. lwz r8, GOT(_end_of_vectors)
  431. li r9, 0x100 /* reset vector always at 0x100 */
  432. cmplw 0, r7, r8
  433. bgelr /* return if r7>=r8 - just in case */
  434. 1:
  435. lwz r0, 0(r7)
  436. stw r0, 0(r9)
  437. addi r7, r7, 4
  438. addi r9, r9, 4
  439. cmplw 0, r7, r8
  440. bne 1b
  441. /*
  442. * relocate `hdlr' and `int_return' entries
  443. */
  444. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  445. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  446. 2:
  447. bl trap_reloc
  448. addi r7, r7, 0x100 /* next exception vector */
  449. cmplw 0, r7, r8
  450. blt 2b
  451. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  452. bl trap_reloc
  453. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  454. bl trap_reloc
  455. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  456. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  457. 3:
  458. bl trap_reloc
  459. addi r7, r7, 0x100 /* next exception vector */
  460. cmplw 0, r7, r8
  461. blt 3b
  462. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  463. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  464. 4:
  465. bl trap_reloc
  466. addi r7, r7, 0x100 /* next exception vector */
  467. cmplw 0, r7, r8
  468. blt 4b
  469. mtlr r4 /* restore link register */
  470. blr
  471. #if defined(CONFIG_PATI)
  472. /* Program the PLL */
  473. pll_prog_code_start:
  474. lis r4, (CONFIG_SYS_IMMR + 0x002fc384)@h
  475. ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc384)@l
  476. lis r3, (0x55ccaa33)@h
  477. ori r3, r3, (0x55ccaa33)@l
  478. stw r3, 0(r4)
  479. lis r4, (CONFIG_SYS_IMMR + 0x002fc284)@h
  480. ori r4, r4, (CONFIG_SYS_IMMR + 0x002fc284)@l
  481. lis r3, CONFIG_SYS_PLPRCR@h
  482. ori r3, r3, CONFIG_SYS_PLPRCR@l
  483. stw r3, 0(r4)
  484. addis r3,0,0x0
  485. ori r3,r3,0xA000
  486. mtctr r3
  487. ..spinlp:
  488. bdnz ..spinlp /* spin loop */
  489. blr
  490. pll_prog_code_end:
  491. nop
  492. blr
  493. #endif