spi.c 12 KB

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  1. /*
  2. * Copyright (c) 2001 Navin Boppuri / Prashant Patel
  3. * <nboppuri@trinetcommunication.com>,
  4. * <pmpatel@trinetcommunication.com>
  5. * Copyright (c) 2001 Gerd Mennchen <Gerd.Mennchen@icn.siemens.de>
  6. * Copyright (c) 2001 Wolfgang Denk, DENX Software Engineering, <wd@denx.de>.
  7. *
  8. * See file CREDITS for list of people who contributed to this
  9. * project.
  10. *
  11. * This program is free software; you can redistribute it and/or
  12. * modify it under the terms of the GNU General Public License as
  13. * published by the Free Software Foundation; either version 2 of
  14. * the License, or (at your option) any later version.
  15. *
  16. * This program is distributed in the hope that it will be useful,
  17. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  18. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  19. * GNU General Public License for more details.
  20. *
  21. * You should have received a copy of the GNU General Public License
  22. * along with this program; if not, write to the Free Software
  23. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  24. * MA 02111-1307 USA
  25. */
  26. /*
  27. * MPC5xx CPM SPI interface.
  28. *
  29. * Parts of this code are probably not portable and/or specific to
  30. * the board which I used for the tests. Please send fixes/complaints
  31. * to wd@denx.de
  32. *
  33. * Ported to MPC5xx
  34. * Copyright (c) 2003 Denis Peter, MPL AG Switzerland, d.petr@mpl.ch.
  35. */
  36. #include <common.h>
  37. #include <mpc5xx.h>
  38. #include <asm/5xx_immap.h>
  39. #include <linux/ctype.h>
  40. #include <malloc.h>
  41. #include <post.h>
  42. #include <net.h>
  43. #if defined(CONFIG_SPI)
  44. #undef DEBUG
  45. #define SPI_EEPROM_WREN 0x06
  46. #define SPI_EEPROM_RDSR 0x05
  47. #define SPI_EEPROM_READ 0x03
  48. #define SPI_EEPROM_WRITE 0x02
  49. #ifdef DEBUG
  50. #define DPRINT(a) printf a;
  51. /* -----------------------------------------------
  52. * Helper functions to peek into tx and rx buffers
  53. * ----------------------------------------------- */
  54. static const char * const hex_digit = "0123456789ABCDEF";
  55. static char quickhex (int i)
  56. {
  57. return hex_digit[i];
  58. }
  59. static void memdump (void *pv, int num)
  60. {
  61. int i;
  62. unsigned char *pc = (unsigned char *) pv;
  63. for (i = 0; i < num; i++)
  64. printf ("%c%c ", quickhex (pc[i] >> 4), quickhex (pc[i] & 0x0f));
  65. printf ("\t");
  66. for (i = 0; i < num; i++)
  67. printf ("%c", isprint (pc[i]) ? pc[i] : '.');
  68. printf ("\n");
  69. }
  70. #else /* !DEBUG */
  71. #define DPRINT(a)
  72. #endif /* DEBUG */
  73. /* -------------------
  74. * Function prototypes
  75. * ------------------- */
  76. void spi_init (void);
  77. ssize_t spi_read (uchar *, int, uchar *, int);
  78. ssize_t spi_write (uchar *, int, uchar *, int);
  79. ssize_t spi_xfer (size_t);
  80. /* **************************************************************************
  81. *
  82. * Function: spi_init_f
  83. *
  84. * Description: Init SPI-Controller (ROM part)
  85. *
  86. * return: ---
  87. *
  88. * *********************************************************************** */
  89. void spi_init_f (void)
  90. {
  91. int i;
  92. volatile immap_t *immr;
  93. volatile qsmcm5xx_t *qsmcm;
  94. immr = (immap_t *) CONFIG_SYS_IMMR;
  95. qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
  96. qsmcm->qsmcm_qsmcr = 0; /* all accesses enabled */
  97. qsmcm->qsmcm_qspi_il = 0; /* lowest IRQ */
  98. /* --------------------------------------------
  99. * GPIO or per. Function
  100. * PQSPAR[00] = 0 reserved
  101. * PQSPAR[01] = 1 [0x4000] -> PERI: (SPICS3)
  102. * PQSPAR[02] = 0 [0x0000] -> GPIO
  103. * PQSPAR[03] = 0 [0x0000] -> GPIO
  104. * PQSPAR[04] = 1 [0x0800] -> PERI: (SPICS0)
  105. * PQSPAR[05] = 0 reseved
  106. * PQSPAR[06] = 1 [0x0200] -> PERI: (SPIMOSI)
  107. * PQSPAR[07] = 1 [0x0100] -> PERI: (SPIMISO)
  108. * -------------------------------------------- */
  109. qsmcm->qsmcm_pqspar = 0x3 | (CONFIG_SYS_SPI_CS_USED << 3);
  110. /* --------------------------------------------
  111. * DDRQS[00] = 0 reserved
  112. * DDRQS[01] = 1 [0x0040] -> SPICS3 Output
  113. * DDRQS[02] = 0 [0x0000] -> GPIO Output
  114. * DDRQS[03] = 0 [0x0000] -> GPIO Output
  115. * DDRQS[04] = 1 [0x0008] -> SPICS0 Output
  116. * DDRQS[05] = 1 [0x0004] -> SPICLK Output
  117. * DDRQS[06] = 1 [0x0002] -> SPIMOSI Output
  118. * DDRQS[07] = 0 [0x0001] -> SPIMISO Input
  119. * -------------------------------------------- */
  120. qsmcm->qsmcm_ddrqs = 0x7E;
  121. /* --------------------------------------------
  122. * Base state for used SPI CS pins, if base = 0 active must be 1
  123. * PORTQS[00] = 0 reserved
  124. * PORTQS[01] = 0 reserved
  125. * PORTQS[02] = 0 reserved
  126. * PORTQS[03] = 0 reserved
  127. * PORTQS[04] = 0 [0x0000] RxD2
  128. * PORTQS[05] = 1 [0x0400] TxD2
  129. * PORTQS[06] = 0 [0x0000] RxD1
  130. * PORTQS[07] = 1 [0x0100] TxD1
  131. * PORTQS[08] = 0 reserved
  132. * PORTQS[09] = 0 [0x0000] -> SPICS3 Base Output
  133. * PORTQS[10] = 0 [0x0000] -> SPICS2 Base Output
  134. * PORTQS[11] = 0 [0x0000] -> SPICS1 Base Output
  135. * PORTQS[12] = 0 [0x0000] -> SPICS0 Base Output
  136. * PORTQS[13] = 0 [0x0004] -> SPICLK Output
  137. * PORTQS[14] = 0 [0x0002] -> SPIMOSI Output
  138. * PORTQS[15] = 0 [0x0001] -> SPIMISO Input
  139. * -------------------------------------------- */
  140. qsmcm->qsmcm_portqs |= (CONFIG_SYS_SPI_CS_BASE << 3);
  141. /* --------------------------------------------
  142. * Controll Register 0
  143. * SPCR0[00] = 1 (0x8000) Master
  144. * SPCR0[01] = 0 (0x0000) Wired-Or
  145. * SPCR0[2..5] = (0x2000) Bits per transfer (default 8)
  146. * SPCR0[06] = 0 (0x0000) Normal polarity
  147. * SPCR0[07] = 0 (0x0000) Normal Clock Phase
  148. * SPCR0[08..15] = 14 1.4MHz
  149. */
  150. qsmcm->qsmcm_spcr0=0xA00E;
  151. /* --------------------------------------------
  152. * Controll Register 1
  153. * SPCR1[00] = 0 (0x0000) QSPI enabled
  154. * SPCR1[1..7] = (0x7F00) Delay before Transfer
  155. * SPCR1[8..15] = (0x0000) Delay After transfer (204.8usec@40MHz)
  156. */
  157. qsmcm->qsmcm_spcr1=0x7F00;
  158. /* --------------------------------------------
  159. * Controll Register 2
  160. * SPCR2[00] = 0 (0x0000) SPI IRQs Disabeld
  161. * SPCR2[01] = 0 (0x0000) No Wrap around
  162. * SPCR2[02] = 0 (0x0000) Wrap to 0
  163. * SPCR2[3..7] = (0x0000) End Queue pointer = 0
  164. * SPCR2[8..10] = 0 (0x0000) reserved
  165. * SPCR2[11..15] = 0 (0x0000) NewQueue Address = 0
  166. */
  167. qsmcm->qsmcm_spcr2=0x0000;
  168. /* --------------------------------------------
  169. * Controll Register 3
  170. * SPCR3[00..04] = 0 (0x0000) reserved
  171. * SPCR3[05] = 0 (0x0000) Feedback disabled
  172. * SPCR3[06] = 0 (0x0000) IRQ on HALTA & MODF disabled
  173. * SPCR3[07] = 0 (0x0000) Not halted
  174. */
  175. qsmcm->qsmcm_spcr3=0x00;
  176. /* --------------------------------------------
  177. * SPSR (Controll Register 3) Read only/ reset Flags 08,09,10
  178. * SPCR3[08] = 1 (0x80) QSPI finished
  179. * SPCR3[09] = 1 (0x40) Mode Fault Flag
  180. * SPCR3[10] = 1 (0x20) HALTA
  181. * SPCR3[11..15] = 0 (0x0000) Last executed command
  182. */
  183. qsmcm->qsmcm_spsr=0xE0;
  184. /*-------------------------------------------
  185. * Setup RAM
  186. */
  187. for(i=0;i<32;i++) {
  188. qsmcm->qsmcm_recram[i]=0x0000;
  189. qsmcm->qsmcm_tranram[i]=0x0000;
  190. qsmcm->qsmcm_comdram[i]=0x00;
  191. }
  192. return;
  193. }
  194. /* **************************************************************************
  195. *
  196. * Function: spi_init_r
  197. * Dummy, all initializations have been done in spi_init_r
  198. * *********************************************************************** */
  199. void spi_init_r (void)
  200. {
  201. return;
  202. }
  203. /****************************************************************************
  204. * Function: spi_write
  205. **************************************************************************** */
  206. ssize_t short_spi_write (uchar *addr, int alen, uchar *buffer, int len)
  207. {
  208. int i,dlen;
  209. volatile immap_t *immr;
  210. volatile qsmcm5xx_t *qsmcm;
  211. immr = (immap_t *) CONFIG_SYS_IMMR;
  212. qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
  213. for(i=0;i<32;i++) {
  214. qsmcm->qsmcm_recram[i]=0x0000;
  215. qsmcm->qsmcm_tranram[i]=0x0000;
  216. qsmcm->qsmcm_comdram[i]=0x00;
  217. }
  218. qsmcm->qsmcm_tranram[0] = SPI_EEPROM_WREN; /* write enable */
  219. spi_xfer(1);
  220. i=0;
  221. qsmcm->qsmcm_tranram[i++] = SPI_EEPROM_WRITE; /* WRITE memory array */
  222. qsmcm->qsmcm_tranram[i++] = addr[0];
  223. qsmcm->qsmcm_tranram[i++] = addr[1];
  224. for(dlen=0;dlen<len;dlen++) {
  225. qsmcm->qsmcm_tranram[i+dlen] = buffer[dlen]; /* WRITE memory array */
  226. }
  227. /* transmit it */
  228. spi_xfer(i+dlen);
  229. /* ignore received data */
  230. for (i = 0; i < 1000; i++) {
  231. qsmcm->qsmcm_tranram[0] = SPI_EEPROM_RDSR; /* read status */
  232. qsmcm->qsmcm_tranram[1] = 0;
  233. spi_xfer(2);
  234. if (!(qsmcm->qsmcm_recram[1] & 1)) {
  235. break;
  236. }
  237. udelay(1000);
  238. }
  239. if (i >= 1000) {
  240. printf ("*** spi_write: Time out while writing!\n");
  241. }
  242. return len;
  243. }
  244. #define TRANSFER_LEN 16
  245. ssize_t spi_write (uchar *addr, int alen, uchar *buffer, int len)
  246. {
  247. int index,i,newlen;
  248. uchar newaddr[2];
  249. int curraddr;
  250. curraddr=(addr[alen-2]<<8)+addr[alen-1];
  251. i=len;
  252. index=0;
  253. do {
  254. newaddr[1]=(curraddr & 0xff);
  255. newaddr[0]=((curraddr>>8) & 0xff);
  256. if(i>TRANSFER_LEN) {
  257. newlen=TRANSFER_LEN;
  258. i-=TRANSFER_LEN;
  259. }
  260. else {
  261. newlen=i;
  262. i=0;
  263. }
  264. short_spi_write (newaddr, 2, &buffer[index], newlen);
  265. index+=newlen;
  266. curraddr+=newlen;
  267. }while(i);
  268. return (len);
  269. }
  270. /****************************************************************************
  271. * Function: spi_read
  272. **************************************************************************** */
  273. ssize_t short_spi_read (uchar *addr, int alen, uchar *buffer, int len)
  274. {
  275. int i;
  276. volatile immap_t *immr;
  277. volatile qsmcm5xx_t *qsmcm;
  278. immr = (immap_t *) CONFIG_SYS_IMMR;
  279. qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
  280. for(i=0;i<32;i++) {
  281. qsmcm->qsmcm_recram[i]=0x0000;
  282. qsmcm->qsmcm_tranram[i]=0x0000;
  283. qsmcm->qsmcm_comdram[i]=0x00;
  284. }
  285. i=0;
  286. qsmcm->qsmcm_tranram[i++] = (SPI_EEPROM_READ); /* READ memory array */
  287. qsmcm->qsmcm_tranram[i++] = addr[0] & 0xff;
  288. qsmcm->qsmcm_tranram[i++] = addr[1] & 0xff;
  289. spi_xfer(3 + len);
  290. for(i=0;i<len;i++) {
  291. *buffer++=(char)qsmcm->qsmcm_recram[i+3];
  292. }
  293. return len;
  294. }
  295. ssize_t spi_read (uchar *addr, int alen, uchar *buffer, int len)
  296. {
  297. int index,i,newlen;
  298. uchar newaddr[2];
  299. int curraddr;
  300. curraddr=(addr[alen-2]<<8)+addr[alen-1];
  301. i=len;
  302. index=0;
  303. do {
  304. newaddr[1]=(curraddr & 0xff);
  305. newaddr[0]=((curraddr>>8) & 0xff);
  306. if(i>TRANSFER_LEN) {
  307. newlen=TRANSFER_LEN;
  308. i-=TRANSFER_LEN;
  309. }
  310. else {
  311. newlen=i;
  312. i=0;
  313. }
  314. short_spi_read (newaddr, 2, &buffer[index], newlen);
  315. index+=newlen;
  316. curraddr+=newlen;
  317. }while(i);
  318. return (len);
  319. }
  320. /****************************************************************************
  321. * Function: spi_xfer
  322. **************************************************************************** */
  323. ssize_t spi_xfer (size_t count)
  324. {
  325. volatile immap_t *immr;
  326. volatile qsmcm5xx_t *qsmcm;
  327. int i;
  328. int tm;
  329. ushort status;
  330. immr = (immap_t *) CONFIG_SYS_IMMR;
  331. qsmcm = (qsmcm5xx_t *)&immr->im_qsmcm;
  332. DPRINT (("*** spi_xfer entered count %d***\n",count));
  333. /* Set CS for device */
  334. for(i=0;i<(count-1);i++)
  335. qsmcm->qsmcm_comdram[i] = 0x80 | CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
  336. qsmcm->qsmcm_comdram[i] = CONFIG_SYS_SPI_CS_ACT; /* CS3 is connected to the SPI EEPROM */
  337. qsmcm->qsmcm_spcr2=((count-1)&0x1F)<<8;
  338. DPRINT (("*** spi_xfer: Bytes to be xferred: %d ***\n", count));
  339. qsmcm->qsmcm_spsr=0xE0; /* clear all flags */
  340. /* start spi transfer */
  341. DPRINT (("*** spi_xfer: Performing transfer ...\n"));
  342. qsmcm->qsmcm_spcr1 |= 0x8000; /* Start transmit */
  343. /* --------------------------------
  344. * Wait for SPI transmit to get out
  345. * or time out (1 second = 1000 ms)
  346. * -------------------------------- */
  347. for (tm=0; tm<1000; ++tm) {
  348. status=qsmcm->qsmcm_spcr1;
  349. if((status & 0x8000)==0)
  350. break;
  351. udelay (1000);
  352. }
  353. if (tm >= 1000) {
  354. printf ("*** spi_xfer: Time out while xferring to/from SPI!\n");
  355. }
  356. #ifdef DEBUG
  357. printf ("\nspi_xfer: txbuf after xfer\n");
  358. memdump ((void *) qsmcm->qsmcm_tranram, 32); /* dump of txbuf before transmit */
  359. printf ("spi_xfer: rxbuf after xfer\n");
  360. memdump ((void *) qsmcm->qsmcm_recram, 32); /* dump of rxbuf after transmit */
  361. printf ("\nspi_xfer: commbuf after xfer\n");
  362. memdump ((void *) qsmcm->qsmcm_comdram, 32); /* dump of txbuf before transmit */
  363. printf ("\n");
  364. #endif
  365. return count;
  366. }
  367. #endif /* CONFIG_SPI */