speed.c 4.0 KB

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  1. /*
  2. * (C) Copyright 2000-2009
  3. * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
  4. *
  5. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. *
  25. * Based on the MPC83xx code.
  26. */
  27. #include <common.h>
  28. #include <command.h>
  29. #include <asm/io.h>
  30. #include <asm/processor.h>
  31. DECLARE_GLOBAL_DATA_PTR;
  32. static int spmf_mult[] = {
  33. 68, 1, 12, 16,
  34. 20, 24, 28, 32,
  35. 36, 40, 44, 48,
  36. 52, 56, 60, 64
  37. };
  38. static int cpmf_mult[][2] = {
  39. {0, 1}, {0, 1}, /* 0 and 1 are not valid */
  40. {1, 1}, {3, 2},
  41. {2, 1}, {5, 2},
  42. {3, 1}, {7, 2},
  43. {0, 1}, {0, 1}, /* and all above 7 are not valid too */
  44. {0, 1}, {0, 1},
  45. {0, 1}, {0, 1},
  46. {0, 1}, {0, 1}
  47. };
  48. static int sys_dividors[][2] = {
  49. {2, 1}, {5, 2}, {3, 1}, {7, 2}, {4, 1},
  50. {9, 2}, {5, 1}, {7, 1}, {6, 1}, {8, 1},
  51. {9, 1}, {11, 1}, {10, 1}, {12, 1}, {13, 1},
  52. {15, 1}, {14, 1}, {16, 1}, {17, 1}, {19, 1},
  53. {18, 1}, {20, 1}, {21, 1}, {23, 1}, {22, 1},
  54. {24, 1}, {25, 1}, {27, 1}, {26, 1}, {28, 1},
  55. {29, 1}, {31, 1}, {30, 1}, {32, 1}, {33, 1}
  56. };
  57. int get_clocks (void)
  58. {
  59. volatile immap_t *im = (immap_t *) CONFIG_SYS_IMMR;
  60. u8 spmf;
  61. u8 cpmf;
  62. u8 sys_div;
  63. u8 ips_div;
  64. u8 pci_div;
  65. u32 ref_clk = CONFIG_SYS_MPC512X_CLKIN;
  66. u32 spll;
  67. u32 sys_clk;
  68. u32 core_clk;
  69. u32 csb_clk;
  70. u32 ips_clk;
  71. u32 pci_clk;
  72. u32 reg;
  73. reg = in_be32(&im->sysconf.immrbar);
  74. if ((reg & IMMRBAR_BASE_ADDR) != (u32) im)
  75. return -1;
  76. reg = in_be32(&im->clk.spmr);
  77. spmf = (reg & SPMR_SPMF) >> SPMR_SPMF_SHIFT;
  78. spll = ref_clk * spmf_mult[spmf];
  79. reg = in_be32(&im->clk.scfr[1]);
  80. sys_div = (reg & SCFR2_SYS_DIV) >> SCFR2_SYS_DIV_SHIFT;
  81. sys_clk = (spll * sys_dividors[sys_div][1]) / sys_dividors[sys_div][0];
  82. csb_clk = sys_clk / 2;
  83. reg = in_be32(&im->clk.spmr);
  84. cpmf = (reg & SPMR_CPMF) >> SPMR_CPMF_SHIFT;
  85. core_clk = (csb_clk * cpmf_mult[cpmf][0]) / cpmf_mult[cpmf][1];
  86. reg = in_be32(&im->clk.scfr[0]);
  87. ips_div = (reg & SCFR1_IPS_DIV_MASK) >> SCFR1_IPS_DIV_SHIFT;
  88. if (ips_div != 0) {
  89. ips_clk = csb_clk / ips_div;
  90. } else {
  91. /* in case we cannot get a sane IPS divisor, fail gracefully */
  92. ips_clk = 0;
  93. }
  94. reg = in_be32(&im->clk.scfr[0]);
  95. pci_div = (reg & SCFR1_PCI_DIV_MASK) >> SCFR1_PCI_DIV_SHIFT;
  96. if (pci_div != 0) {
  97. pci_clk = csb_clk / pci_div;
  98. } else {
  99. /* in case we cannot get a sane IPS divisor, fail gracefully */
  100. pci_clk = 333333;
  101. }
  102. gd->ips_clk = ips_clk;
  103. gd->pci_clk = pci_clk;
  104. gd->csb_clk = csb_clk;
  105. gd->cpu_clk = core_clk;
  106. gd->bus_clk = csb_clk;
  107. return 0;
  108. }
  109. /********************************************
  110. * get_bus_freq
  111. * return system bus freq in Hz
  112. *********************************************/
  113. ulong get_bus_freq (ulong dummy)
  114. {
  115. return gd->csb_clk;
  116. }
  117. int do_clocks (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[])
  118. {
  119. char buf[32];
  120. printf("Clock configuration:\n");
  121. printf(" CPU: %-4s MHz\n", strmhz(buf, gd->cpu_clk));
  122. printf(" Coherent System Bus: %-4s MHz\n", strmhz(buf, gd->csb_clk));
  123. printf(" IPS Bus: %-4s MHz\n", strmhz(buf, gd->ips_clk));
  124. printf(" PCI: %-4s MHz\n", strmhz(buf, gd->pci_clk));
  125. printf(" DDR: %-4s MHz\n", strmhz(buf, 2*gd->csb_clk));
  126. return 0;
  127. }
  128. U_BOOT_CMD(clocks, 1, 0, do_clocks,
  129. "print clock configuration",
  130. " clocks"
  131. );
  132. int prt_mpc512x_clks (void)
  133. {
  134. do_clocks (NULL, 0, 0, NULL);
  135. return (0);
  136. }