cpu_init.c 2.5 KB

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  1. /*
  2. * Copyright (C) 2004-2006 Freescale Semiconductor, Inc.
  3. * Copyright (C) 2007-2009 DENX Software Engineering
  4. *
  5. * See file CREDITS for list of people who contributed to this
  6. * project.
  7. *
  8. * This program is free software; you can redistribute it and/or
  9. * modify it under the terms of the GNU General Public License as
  10. * published by the Free Software Foundation; either version 2 of
  11. * the License, or (at your option) any later version.
  12. *
  13. * This program is distributed in the hope that it will be useful,
  14. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  15. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  16. * GNU General Public License for more details.
  17. *
  18. * You should have received a copy of the GNU General Public License
  19. * along with this program; if not, write to the Free Software
  20. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  21. * MA 02111-1307 USA
  22. *
  23. * Derived from the MPC83xx code.
  24. *
  25. */
  26. #include <common.h>
  27. #include <asm/io.h>
  28. #include <asm/processor.h>
  29. DECLARE_GLOBAL_DATA_PTR;
  30. /*
  31. * Set up the memory map, initialize registers,
  32. */
  33. void cpu_init_f (volatile immap_t * im)
  34. {
  35. u32 ips_div;
  36. /* Pointer is writable since we allocated a register for it */
  37. gd = (gd_t *) (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET);
  38. /* Clear initial global data */
  39. memset ((void *) gd, 0, sizeof (gd_t));
  40. /* system performance tweaking */
  41. #ifdef CONFIG_SYS_ACR_PIPE_DEP
  42. /* Arbiter pipeline depth */
  43. out_be32(&im->arbiter.acr,
  44. (im->arbiter.acr & ~ACR_PIPE_DEP) |
  45. (CONFIG_SYS_ACR_PIPE_DEP << ACR_PIPE_DEP_SHIFT)
  46. );
  47. #endif
  48. #ifdef CONFIG_SYS_ACR_RPTCNT
  49. /* Arbiter repeat count */
  50. out_be32(im->arbiter.acr,
  51. (im->arbiter.acr & ~(ACR_RPTCNT)) |
  52. (CONFIG_SYS_ACR_RPTCNT << ACR_RPTCNT_SHIFT)
  53. );
  54. #endif
  55. /* RSR - Reset Status Register - clear all status */
  56. gd->reset_status = im->reset.rsr;
  57. out_be32(&im->reset.rsr, ~RSR_RES);
  58. /*
  59. * RMR - Reset Mode Register - enable checkstop reset
  60. */
  61. out_be32(&im->reset.rmr, RMR_CSRE & (1 << RMR_CSRE_SHIFT));
  62. /* Set IPS-CSB divider: IPS = 1/2 CSB */
  63. ips_div = in_be32(&im->clk.scfr[0]);
  64. ips_div &= ~(SCFR1_IPS_DIV_MASK);
  65. ips_div |= SCFR1_IPS_DIV << SCFR1_IPS_DIV_SHIFT;
  66. out_be32(&im->clk.scfr[0], ips_div);
  67. /*
  68. * Enable Time Base/Decrementer
  69. *
  70. * NOTICE: TB needs to be enabled as early as possible in order to
  71. * have udelay() working; if not enabled, usually leads to a hang, like
  72. * during FLASH chip identification etc.
  73. */
  74. setbits_be32(&im->sysconf.spcr, SPCR_TBEN);
  75. }
  76. int cpu_init_r (void)
  77. {
  78. return 0;
  79. }