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  1. /*
  2. * Copyright (C) 1998 Dan Malek <dmalek@jlc.net>
  3. * Copyright (C) 1999 Magnus Damm <kieraypc01.p.y.kie.era.ericsson.se>
  4. * Copyright (C) 2000,2001,2002 Wolfgang Denk <wd@denx.de>
  5. * Copyright (C) 2001 Josh Huber <huber@mclx.com>
  6. *
  7. * See file CREDITS for list of people who contributed to this
  8. * project.
  9. *
  10. * This program is free software; you can redistribute it and/or
  11. * modify it under the terms of the GNU General Public License as
  12. * published by the Free Software Foundation; either version 2 of
  13. * the License, or (at your option) any later version.
  14. *
  15. * This program is distributed in the hope that it will be useful,
  16. * but WITHOUT ANY WARRANTY; without even the implied warranty of
  17. * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
  18. * GNU General Public License for more details.
  19. *
  20. * You should have received a copy of the GNU General Public License
  21. * along with this program; if not, write to the Free Software
  22. * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
  23. * MA 02111-1307 USA
  24. */
  25. /* U-Boot - Startup Code for PowerPC based Embedded Boards
  26. *
  27. *
  28. * The processor starts at 0xfff00100 and the code is executed
  29. * from flash. The code is organized to be at an other address
  30. * in memory, but as long we don't jump around before relocating.
  31. * board_init lies at a quite high address and when the cpu has
  32. * jumped there, everything is ok.
  33. */
  34. #include <config.h>
  35. #include <74xx_7xx.h>
  36. #include <timestamp.h>
  37. #include <version.h>
  38. #include <ppc_asm.tmpl>
  39. #include <ppc_defs.h>
  40. #include <asm/cache.h>
  41. #include <asm/mmu.h>
  42. #if !defined(CONFIG_DB64360) && \
  43. !defined(CONFIG_DB64460) && \
  44. !defined(CONFIG_CPCI750) && \
  45. !defined(CONFIG_P3Mx)
  46. #include <galileo/gt64260R.h>
  47. #endif
  48. #ifndef CONFIG_IDENT_STRING
  49. #define CONFIG_IDENT_STRING ""
  50. #endif
  51. /* We don't want the MMU yet.
  52. */
  53. #undef MSR_KERNEL
  54. /* Machine Check and Recoverable Interr. */
  55. #define MSR_KERNEL ( MSR_ME | MSR_RI )
  56. /*
  57. * Set up GOT: Global Offset Table
  58. *
  59. * Use r12 to access the GOT
  60. */
  61. START_GOT
  62. GOT_ENTRY(_GOT2_TABLE_)
  63. GOT_ENTRY(_FIXUP_TABLE_)
  64. GOT_ENTRY(_start)
  65. GOT_ENTRY(_start_of_vectors)
  66. GOT_ENTRY(_end_of_vectors)
  67. GOT_ENTRY(transfer_to_handler)
  68. GOT_ENTRY(__init_end)
  69. GOT_ENTRY(_end)
  70. GOT_ENTRY(__bss_start)
  71. END_GOT
  72. /*
  73. * r3 - 1st arg to board_init(): IMMP pointer
  74. * r4 - 2nd arg to board_init(): boot flag
  75. */
  76. .text
  77. .long 0x27051956 /* U-Boot Magic Number */
  78. .globl version_string
  79. version_string:
  80. .ascii U_BOOT_VERSION
  81. .ascii " (", U_BOOT_DATE, " - ", U_BOOT_TIME, ")"
  82. .ascii CONFIG_IDENT_STRING, "\0"
  83. . = EXC_OFF_SYS_RESET
  84. .globl _start
  85. _start:
  86. li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH */
  87. b boot_cold
  88. sync
  89. . = EXC_OFF_SYS_RESET + 0x10
  90. .globl _start_warm
  91. _start_warm:
  92. li r21, BOOTFLAG_WARM /* Software reboot */
  93. b boot_warm
  94. sync
  95. /* the boot code is located below the exception table */
  96. .globl _start_of_vectors
  97. _start_of_vectors:
  98. /* Machine check */
  99. STD_EXCEPTION(0x200, MachineCheck, MachineCheckException)
  100. /* Data Storage exception. "Never" generated on the 860. */
  101. STD_EXCEPTION(0x300, DataStorage, UnknownException)
  102. /* Instruction Storage exception. "Never" generated on the 860. */
  103. STD_EXCEPTION(0x400, InstStorage, UnknownException)
  104. /* External Interrupt exception. */
  105. STD_EXCEPTION(0x500, ExtInterrupt, external_interrupt)
  106. /* Alignment exception. */
  107. . = 0x600
  108. Alignment:
  109. EXCEPTION_PROLOG(SRR0, SRR1)
  110. mfspr r4,DAR
  111. stw r4,_DAR(r21)
  112. mfspr r5,DSISR
  113. stw r5,_DSISR(r21)
  114. addi r3,r1,STACK_FRAME_OVERHEAD
  115. EXC_XFER_TEMPLATE(Alignment, AlignmentException, MSR_KERNEL, COPY_EE)
  116. /* Program check exception */
  117. . = 0x700
  118. ProgramCheck:
  119. EXCEPTION_PROLOG(SRR0, SRR1)
  120. addi r3,r1,STACK_FRAME_OVERHEAD
  121. EXC_XFER_TEMPLATE(ProgramCheck, ProgramCheckException,
  122. MSR_KERNEL, COPY_EE)
  123. /* No FPU on MPC8xx. This exception is not supposed to happen.
  124. */
  125. STD_EXCEPTION(0x800, FPUnavailable, UnknownException)
  126. /* I guess we could implement decrementer, and may have
  127. * to someday for timekeeping.
  128. */
  129. STD_EXCEPTION(0x900, Decrementer, timer_interrupt)
  130. STD_EXCEPTION(0xa00, Trap_0a, UnknownException)
  131. STD_EXCEPTION(0xb00, Trap_0b, UnknownException)
  132. STD_EXCEPTION(0xc00, SystemCall, UnknownException)
  133. STD_EXCEPTION(0xd00, SingleStep, UnknownException)
  134. STD_EXCEPTION(0xe00, Trap_0e, UnknownException)
  135. STD_EXCEPTION(0xf00, Trap_0f, UnknownException)
  136. /*
  137. * On the MPC8xx, this is a software emulation interrupt. It
  138. * occurs for all unimplemented and illegal instructions.
  139. */
  140. STD_EXCEPTION(0x1000, SoftEmu, SoftEmuException)
  141. STD_EXCEPTION(0x1100, InstructionTLBMiss, UnknownException)
  142. STD_EXCEPTION(0x1200, DataTLBMiss, UnknownException)
  143. STD_EXCEPTION(0x1300, InstructionTLBError, UnknownException)
  144. STD_EXCEPTION(0x1400, DataTLBError, UnknownException)
  145. STD_EXCEPTION(0x1500, Reserved5, UnknownException)
  146. STD_EXCEPTION(0x1600, Reserved6, UnknownException)
  147. STD_EXCEPTION(0x1700, Reserved7, UnknownException)
  148. STD_EXCEPTION(0x1800, Reserved8, UnknownException)
  149. STD_EXCEPTION(0x1900, Reserved9, UnknownException)
  150. STD_EXCEPTION(0x1a00, ReservedA, UnknownException)
  151. STD_EXCEPTION(0x1b00, ReservedB, UnknownException)
  152. STD_EXCEPTION(0x1c00, DataBreakpoint, UnknownException)
  153. STD_EXCEPTION(0x1d00, InstructionBreakpoint, UnknownException)
  154. STD_EXCEPTION(0x1e00, PeripheralBreakpoint, UnknownException)
  155. STD_EXCEPTION(0x1f00, DevPortBreakpoint, UnknownException)
  156. .globl _end_of_vectors
  157. _end_of_vectors:
  158. . = 0x2000
  159. boot_cold:
  160. boot_warm:
  161. /* disable everything */
  162. li r0, 0
  163. mtspr HID0, r0
  164. sync
  165. mtmsr 0
  166. bl invalidate_bats
  167. sync
  168. #ifdef CONFIG_SYS_L2
  169. /* init the L2 cache */
  170. addis r3, r0, L2_INIT@h
  171. ori r3, r3, L2_INIT@l
  172. sync
  173. mtspr l2cr, r3
  174. #endif
  175. #if defined(CONFIG_ALTIVEC) && defined(CONFIG_74xx)
  176. .long 0x7e00066c
  177. /*
  178. * dssall instruction, gas doesn't have it yet
  179. * ...for altivec, data stream stop all this probably
  180. * isn't needed unless we warm (software) reboot U-Boot
  181. */
  182. #endif
  183. #ifdef CONFIG_SYS_L2
  184. /* invalidate the L2 cache */
  185. bl l2cache_invalidate
  186. sync
  187. #endif
  188. #ifdef CONFIG_SYS_BOARD_ASM_INIT
  189. /* do early init */
  190. bl board_asm_init
  191. #endif
  192. /*
  193. * Calculate absolute address in FLASH and jump there
  194. *------------------------------------------------------*/
  195. lis r3, CONFIG_SYS_MONITOR_BASE@h
  196. ori r3, r3, CONFIG_SYS_MONITOR_BASE@l
  197. addi r3, r3, in_flash - _start + EXC_OFF_SYS_RESET
  198. mtlr r3
  199. blr
  200. in_flash:
  201. /* let the C-code set up the rest */
  202. /* */
  203. /* Be careful to keep code relocatable ! */
  204. /*------------------------------------------------------*/
  205. /* perform low-level init */
  206. /* sdram init, galileo init, etc */
  207. /* r3: NHR bit from HID0 */
  208. /* setup the bats */
  209. bl setup_bats
  210. sync
  211. /*
  212. * Cache must be enabled here for stack-in-cache trick.
  213. * This means we need to enable the BATS.
  214. * This means:
  215. * 1) for the EVB, original gt regs need to be mapped
  216. * 2) need to have an IBAT for the 0xf region,
  217. * we are running there!
  218. * Cache should be turned on after BATs, since by default
  219. * everything is write-through.
  220. * The init-mem BAT can be reused after reloc. The old
  221. * gt-regs BAT can be reused after board_init_f calls
  222. * board_early_init_f (EVB only).
  223. */
  224. #if !defined(CONFIG_BAB7xx) && !defined(CONFIG_ELPPC) && !defined(CONFIG_P3Mx)
  225. /* enable address translation */
  226. bl enable_addr_trans
  227. sync
  228. /* enable and invalidate the data cache */
  229. bl l1dcache_enable
  230. sync
  231. #endif
  232. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  233. bl lock_ram_in_cache
  234. sync
  235. #endif
  236. /* set up the stack pointer in our newly created
  237. * cache-ram (r1) */
  238. lis r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@h
  239. ori r1, r1, (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_GBL_DATA_OFFSET)@l
  240. li r0, 0 /* Make room for stack frame header and */
  241. stwu r0, -4(r1) /* clear final stack frame so that */
  242. stwu r0, -4(r1) /* stack backtraces terminate cleanly */
  243. GET_GOT /* initialize GOT access */
  244. /* run low-level CPU init code (from Flash) */
  245. bl cpu_init_f
  246. sync
  247. mr r3, r21
  248. /* r3: BOOTFLAG */
  249. /* run 1st part of board init code (from Flash) */
  250. bl board_init_f
  251. sync
  252. /* NOTREACHED */
  253. .globl invalidate_bats
  254. invalidate_bats:
  255. /* invalidate BATs */
  256. mtspr IBAT0U, r0
  257. mtspr IBAT1U, r0
  258. mtspr IBAT2U, r0
  259. mtspr IBAT3U, r0
  260. #ifdef CONFIG_HIGH_BATS
  261. mtspr IBAT4U, r0
  262. mtspr IBAT5U, r0
  263. mtspr IBAT6U, r0
  264. mtspr IBAT7U, r0
  265. #endif
  266. isync
  267. mtspr DBAT0U, r0
  268. mtspr DBAT1U, r0
  269. mtspr DBAT2U, r0
  270. mtspr DBAT3U, r0
  271. #ifdef CONFIG_HIGH_BATS
  272. mtspr DBAT4U, r0
  273. mtspr DBAT5U, r0
  274. mtspr DBAT6U, r0
  275. mtspr DBAT7U, r0
  276. #endif
  277. isync
  278. sync
  279. blr
  280. /* setup_bats - set them up to some initial state */
  281. .globl setup_bats
  282. setup_bats:
  283. addis r0, r0, 0x0000
  284. /* IBAT 0 */
  285. addis r4, r0, CONFIG_SYS_IBAT0L@h
  286. ori r4, r4, CONFIG_SYS_IBAT0L@l
  287. addis r3, r0, CONFIG_SYS_IBAT0U@h
  288. ori r3, r3, CONFIG_SYS_IBAT0U@l
  289. mtspr IBAT0L, r4
  290. mtspr IBAT0U, r3
  291. isync
  292. /* DBAT 0 */
  293. addis r4, r0, CONFIG_SYS_DBAT0L@h
  294. ori r4, r4, CONFIG_SYS_DBAT0L@l
  295. addis r3, r0, CONFIG_SYS_DBAT0U@h
  296. ori r3, r3, CONFIG_SYS_DBAT0U@l
  297. mtspr DBAT0L, r4
  298. mtspr DBAT0U, r3
  299. isync
  300. /* IBAT 1 */
  301. addis r4, r0, CONFIG_SYS_IBAT1L@h
  302. ori r4, r4, CONFIG_SYS_IBAT1L@l
  303. addis r3, r0, CONFIG_SYS_IBAT1U@h
  304. ori r3, r3, CONFIG_SYS_IBAT1U@l
  305. mtspr IBAT1L, r4
  306. mtspr IBAT1U, r3
  307. isync
  308. /* DBAT 1 */
  309. addis r4, r0, CONFIG_SYS_DBAT1L@h
  310. ori r4, r4, CONFIG_SYS_DBAT1L@l
  311. addis r3, r0, CONFIG_SYS_DBAT1U@h
  312. ori r3, r3, CONFIG_SYS_DBAT1U@l
  313. mtspr DBAT1L, r4
  314. mtspr DBAT1U, r3
  315. isync
  316. /* IBAT 2 */
  317. addis r4, r0, CONFIG_SYS_IBAT2L@h
  318. ori r4, r4, CONFIG_SYS_IBAT2L@l
  319. addis r3, r0, CONFIG_SYS_IBAT2U@h
  320. ori r3, r3, CONFIG_SYS_IBAT2U@l
  321. mtspr IBAT2L, r4
  322. mtspr IBAT2U, r3
  323. isync
  324. /* DBAT 2 */
  325. addis r4, r0, CONFIG_SYS_DBAT2L@h
  326. ori r4, r4, CONFIG_SYS_DBAT2L@l
  327. addis r3, r0, CONFIG_SYS_DBAT2U@h
  328. ori r3, r3, CONFIG_SYS_DBAT2U@l
  329. mtspr DBAT2L, r4
  330. mtspr DBAT2U, r3
  331. isync
  332. /* IBAT 3 */
  333. addis r4, r0, CONFIG_SYS_IBAT3L@h
  334. ori r4, r4, CONFIG_SYS_IBAT3L@l
  335. addis r3, r0, CONFIG_SYS_IBAT3U@h
  336. ori r3, r3, CONFIG_SYS_IBAT3U@l
  337. mtspr IBAT3L, r4
  338. mtspr IBAT3U, r3
  339. isync
  340. /* DBAT 3 */
  341. addis r4, r0, CONFIG_SYS_DBAT3L@h
  342. ori r4, r4, CONFIG_SYS_DBAT3L@l
  343. addis r3, r0, CONFIG_SYS_DBAT3U@h
  344. ori r3, r3, CONFIG_SYS_DBAT3U@l
  345. mtspr DBAT3L, r4
  346. mtspr DBAT3U, r3
  347. isync
  348. #ifdef CONFIG_HIGH_BATS
  349. /* IBAT 4 */
  350. addis r4, r0, CONFIG_SYS_IBAT4L@h
  351. ori r4, r4, CONFIG_SYS_IBAT4L@l
  352. addis r3, r0, CONFIG_SYS_IBAT4U@h
  353. ori r3, r3, CONFIG_SYS_IBAT4U@l
  354. mtspr IBAT4L, r4
  355. mtspr IBAT4U, r3
  356. isync
  357. /* DBAT 4 */
  358. addis r4, r0, CONFIG_SYS_DBAT4L@h
  359. ori r4, r4, CONFIG_SYS_DBAT4L@l
  360. addis r3, r0, CONFIG_SYS_DBAT4U@h
  361. ori r3, r3, CONFIG_SYS_DBAT4U@l
  362. mtspr DBAT4L, r4
  363. mtspr DBAT4U, r3
  364. isync
  365. /* IBAT 5 */
  366. addis r4, r0, CONFIG_SYS_IBAT5L@h
  367. ori r4, r4, CONFIG_SYS_IBAT5L@l
  368. addis r3, r0, CONFIG_SYS_IBAT5U@h
  369. ori r3, r3, CONFIG_SYS_IBAT5U@l
  370. mtspr IBAT5L, r4
  371. mtspr IBAT5U, r3
  372. isync
  373. /* DBAT 5 */
  374. addis r4, r0, CONFIG_SYS_DBAT5L@h
  375. ori r4, r4, CONFIG_SYS_DBAT5L@l
  376. addis r3, r0, CONFIG_SYS_DBAT5U@h
  377. ori r3, r3, CONFIG_SYS_DBAT5U@l
  378. mtspr DBAT5L, r4
  379. mtspr DBAT5U, r3
  380. isync
  381. /* IBAT 6 */
  382. addis r4, r0, CONFIG_SYS_IBAT6L@h
  383. ori r4, r4, CONFIG_SYS_IBAT6L@l
  384. addis r3, r0, CONFIG_SYS_IBAT6U@h
  385. ori r3, r3, CONFIG_SYS_IBAT6U@l
  386. mtspr IBAT6L, r4
  387. mtspr IBAT6U, r3
  388. isync
  389. /* DBAT 6 */
  390. addis r4, r0, CONFIG_SYS_DBAT6L@h
  391. ori r4, r4, CONFIG_SYS_DBAT6L@l
  392. addis r3, r0, CONFIG_SYS_DBAT6U@h
  393. ori r3, r3, CONFIG_SYS_DBAT6U@l
  394. mtspr DBAT6L, r4
  395. mtspr DBAT6U, r3
  396. isync
  397. /* IBAT 7 */
  398. addis r4, r0, CONFIG_SYS_IBAT7L@h
  399. ori r4, r4, CONFIG_SYS_IBAT7L@l
  400. addis r3, r0, CONFIG_SYS_IBAT7U@h
  401. ori r3, r3, CONFIG_SYS_IBAT7U@l
  402. mtspr IBAT7L, r4
  403. mtspr IBAT7U, r3
  404. isync
  405. /* DBAT 7 */
  406. addis r4, r0, CONFIG_SYS_DBAT7L@h
  407. ori r4, r4, CONFIG_SYS_DBAT7L@l
  408. addis r3, r0, CONFIG_SYS_DBAT7U@h
  409. ori r3, r3, CONFIG_SYS_DBAT7U@l
  410. mtspr DBAT7L, r4
  411. mtspr DBAT7U, r3
  412. isync
  413. #endif
  414. /* bats are done, now invalidate the TLBs */
  415. addis r3, 0, 0x0000
  416. addis r5, 0, 0x4 /* upper bound of 0x00040000 for 7400/750 */
  417. isync
  418. tlblp:
  419. tlbie r3
  420. sync
  421. addi r3, r3, 0x1000
  422. cmp 0, 0, r3, r5
  423. blt tlblp
  424. blr
  425. .globl enable_addr_trans
  426. enable_addr_trans:
  427. /* enable address translation */
  428. mfmsr r5
  429. ori r5, r5, (MSR_IR | MSR_DR)
  430. mtmsr r5
  431. isync
  432. blr
  433. .globl disable_addr_trans
  434. disable_addr_trans:
  435. /* disable address translation */
  436. mflr r4
  437. mfmsr r3
  438. andi. r0, r3, (MSR_IR | MSR_DR)
  439. beqlr
  440. andc r3, r3, r0
  441. mtspr SRR0, r4
  442. mtspr SRR1, r3
  443. rfi
  444. /*
  445. * This code finishes saving the registers to the exception frame
  446. * and jumps to the appropriate handler for the exception.
  447. * Register r21 is pointer into trap frame, r1 has new stack pointer.
  448. */
  449. .globl transfer_to_handler
  450. transfer_to_handler:
  451. stw r22,_NIP(r21)
  452. lis r22,MSR_POW@h
  453. andc r23,r23,r22
  454. stw r23,_MSR(r21)
  455. SAVE_GPR(7, r21)
  456. SAVE_4GPRS(8, r21)
  457. SAVE_8GPRS(12, r21)
  458. SAVE_8GPRS(24, r21)
  459. mflr r23
  460. andi. r24,r23,0x3f00 /* get vector offset */
  461. stw r24,TRAP(r21)
  462. li r22,0
  463. stw r22,RESULT(r21)
  464. mtspr SPRG2,r22 /* r1 is now kernel sp */
  465. lwz r24,0(r23) /* virtual address of handler */
  466. lwz r23,4(r23) /* where to go when done */
  467. mtspr SRR0,r24
  468. mtspr SRR1,r20
  469. mtlr r23
  470. SYNC
  471. rfi /* jump to handler, enable MMU */
  472. int_return:
  473. mfmsr r28 /* Disable interrupts */
  474. li r4,0
  475. ori r4,r4,MSR_EE
  476. andc r28,r28,r4
  477. SYNC /* Some chip revs need this... */
  478. mtmsr r28
  479. SYNC
  480. lwz r2,_CTR(r1)
  481. lwz r0,_LINK(r1)
  482. mtctr r2
  483. mtlr r0
  484. lwz r2,_XER(r1)
  485. lwz r0,_CCR(r1)
  486. mtspr XER,r2
  487. mtcrf 0xFF,r0
  488. REST_10GPRS(3, r1)
  489. REST_10GPRS(13, r1)
  490. REST_8GPRS(23, r1)
  491. REST_GPR(31, r1)
  492. lwz r2,_NIP(r1) /* Restore environment */
  493. lwz r0,_MSR(r1)
  494. mtspr SRR0,r2
  495. mtspr SRR1,r0
  496. lwz r0,GPR0(r1)
  497. lwz r2,GPR2(r1)
  498. lwz r1,GPR1(r1)
  499. SYNC
  500. rfi
  501. .globl dc_read
  502. dc_read:
  503. blr
  504. .globl get_pvr
  505. get_pvr:
  506. mfspr r3, PVR
  507. blr
  508. /*-----------------------------------------------------------------------*/
  509. /*
  510. * void relocate_code (addr_sp, gd, addr_moni)
  511. *
  512. * This "function" does not return, instead it continues in RAM
  513. * after relocating the monitor code.
  514. *
  515. * r3 = dest
  516. * r4 = src
  517. * r5 = length in bytes
  518. * r6 = cachelinesize
  519. */
  520. .globl relocate_code
  521. relocate_code:
  522. mr r1, r3 /* Set new stack pointer */
  523. mr r9, r4 /* Save copy of Global Data pointer */
  524. mr r10, r5 /* Save copy of Destination Address */
  525. GET_GOT
  526. mr r3, r5 /* Destination Address */
  527. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  528. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  529. lwz r5, GOT(__init_end)
  530. sub r5, r5, r4
  531. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  532. /*
  533. * Fix GOT pointer:
  534. *
  535. * New GOT-PTR = (old GOT-PTR - CONFIG_SYS_MONITOR_BASE) + Destination Address
  536. *
  537. * Offset:
  538. */
  539. sub r15, r10, r4
  540. /* First our own GOT */
  541. add r12, r12, r15
  542. /* then the one used by the C code */
  543. add r30, r30, r15
  544. /*
  545. * Now relocate code
  546. */
  547. #ifdef CONFIG_ECC
  548. bl board_relocate_rom
  549. sync
  550. mr r3, r10 /* Destination Address */
  551. lis r4, CONFIG_SYS_MONITOR_BASE@h /* Source Address */
  552. ori r4, r4, CONFIG_SYS_MONITOR_BASE@l
  553. lwz r5, GOT(__init_end)
  554. sub r5, r5, r4
  555. li r6, CONFIG_SYS_CACHELINE_SIZE /* Cache Line Size */
  556. #else
  557. cmplw cr1,r3,r4
  558. addi r0,r5,3
  559. srwi. r0,r0,2
  560. beq cr1,4f /* In place copy is not necessary */
  561. beq 7f /* Protect against 0 count */
  562. mtctr r0
  563. bge cr1,2f
  564. la r8,-4(r4)
  565. la r7,-4(r3)
  566. 1: lwzu r0,4(r8)
  567. stwu r0,4(r7)
  568. bdnz 1b
  569. b 4f
  570. 2: slwi r0,r0,2
  571. add r8,r4,r0
  572. add r7,r3,r0
  573. 3: lwzu r0,-4(r8)
  574. stwu r0,-4(r7)
  575. bdnz 3b
  576. #endif
  577. /*
  578. * Now flush the cache: note that we must start from a cache aligned
  579. * address. Otherwise we might miss one cache line.
  580. */
  581. 4: cmpwi r6,0
  582. add r5,r3,r5
  583. beq 7f /* Always flush prefetch queue in any case */
  584. subi r0,r6,1
  585. andc r3,r3,r0
  586. mr r4,r3
  587. 5: dcbst 0,r4
  588. add r4,r4,r6
  589. cmplw r4,r5
  590. blt 5b
  591. sync /* Wait for all dcbst to complete on bus */
  592. mr r4,r3
  593. 6: icbi 0,r4
  594. add r4,r4,r6
  595. cmplw r4,r5
  596. blt 6b
  597. 7: sync /* Wait for all icbi to complete on bus */
  598. isync
  599. /*
  600. * We are done. Do not return, instead branch to second part of board
  601. * initialization, now running from RAM.
  602. */
  603. addi r0, r10, in_ram - _start + EXC_OFF_SYS_RESET
  604. mtlr r0
  605. blr
  606. in_ram:
  607. #ifdef CONFIG_ECC
  608. bl board_init_ecc
  609. #endif
  610. /*
  611. * Relocation Function, r12 point to got2+0x8000
  612. *
  613. * Adjust got2 pointers, no need to check for 0, this code
  614. * already puts a few entries in the table.
  615. */
  616. li r0,__got2_entries@sectoff@l
  617. la r3,GOT(_GOT2_TABLE_)
  618. lwz r11,GOT(_GOT2_TABLE_)
  619. mtctr r0
  620. sub r11,r3,r11
  621. addi r3,r3,-4
  622. 1: lwzu r0,4(r3)
  623. cmpwi r0,0
  624. beq- 2f
  625. add r0,r0,r11
  626. stw r0,0(r3)
  627. 2: bdnz 1b
  628. /*
  629. * Now adjust the fixups and the pointers to the fixups
  630. * in case we need to move ourselves again.
  631. */
  632. li r0,__fixup_entries@sectoff@l
  633. lwz r3,GOT(_FIXUP_TABLE_)
  634. cmpwi r0,0
  635. mtctr r0
  636. addi r3,r3,-4
  637. beq 4f
  638. 3: lwzu r4,4(r3)
  639. lwzux r0,r4,r11
  640. add r0,r0,r11
  641. stw r10,0(r3)
  642. stw r0,0(r4)
  643. bdnz 3b
  644. 4:
  645. /* clear_bss: */
  646. /*
  647. * Now clear BSS segment
  648. */
  649. lwz r3,GOT(__bss_start)
  650. lwz r4,GOT(_end)
  651. cmplw 0, r3, r4
  652. beq 6f
  653. li r0, 0
  654. 5:
  655. stw r0, 0(r3)
  656. addi r3, r3, 4
  657. cmplw 0, r3, r4
  658. bne 5b
  659. 6:
  660. mr r3, r10 /* Destination Address */
  661. #if defined(CONFIG_AMIGAONEG3SE) || \
  662. defined(CONFIG_DB64360) || \
  663. defined(CONFIG_DB64460) || \
  664. defined(CONFIG_CPCI750) || \
  665. defined(CONFIG_PPMC7XX) || \
  666. defined(CONFIG_P3Mx)
  667. mr r4, r9 /* Use RAM copy of the global data */
  668. #endif
  669. bl after_reloc
  670. /* not reached - end relocate_code */
  671. /*-----------------------------------------------------------------------*/
  672. /*
  673. * Copy exception vector code to low memory
  674. *
  675. * r3: dest_addr
  676. * r7: source address, r8: end address, r9: target address
  677. */
  678. .globl trap_init
  679. trap_init:
  680. mflr r4 /* save link register */
  681. GET_GOT
  682. lwz r7, GOT(_start)
  683. lwz r8, GOT(_end_of_vectors)
  684. li r9, 0x100 /* reset vector always at 0x100 */
  685. cmplw 0, r7, r8
  686. bgelr /* return if r7>=r8 - just in case */
  687. 1:
  688. lwz r0, 0(r7)
  689. stw r0, 0(r9)
  690. addi r7, r7, 4
  691. addi r9, r9, 4
  692. cmplw 0, r7, r8
  693. bne 1b
  694. /*
  695. * relocate `hdlr' and `int_return' entries
  696. */
  697. li r7, .L_MachineCheck - _start + EXC_OFF_SYS_RESET
  698. li r8, Alignment - _start + EXC_OFF_SYS_RESET
  699. 2:
  700. bl trap_reloc
  701. addi r7, r7, 0x100 /* next exception vector */
  702. cmplw 0, r7, r8
  703. blt 2b
  704. li r7, .L_Alignment - _start + EXC_OFF_SYS_RESET
  705. bl trap_reloc
  706. li r7, .L_ProgramCheck - _start + EXC_OFF_SYS_RESET
  707. bl trap_reloc
  708. li r7, .L_FPUnavailable - _start + EXC_OFF_SYS_RESET
  709. li r8, SystemCall - _start + EXC_OFF_SYS_RESET
  710. 3:
  711. bl trap_reloc
  712. addi r7, r7, 0x100 /* next exception vector */
  713. cmplw 0, r7, r8
  714. blt 3b
  715. li r7, .L_SingleStep - _start + EXC_OFF_SYS_RESET
  716. li r8, _end_of_vectors - _start + EXC_OFF_SYS_RESET
  717. 4:
  718. bl trap_reloc
  719. addi r7, r7, 0x100 /* next exception vector */
  720. cmplw 0, r7, r8
  721. blt 4b
  722. /* enable execptions from RAM vectors */
  723. mfmsr r7
  724. li r8,MSR_IP
  725. andc r7,r7,r8
  726. mtmsr r7
  727. mtlr r4 /* restore link register */
  728. blr
  729. #ifdef CONFIG_SYS_INIT_RAM_LOCK
  730. lock_ram_in_cache:
  731. /* Allocate Initial RAM in data cache.
  732. */
  733. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  734. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  735. li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
  736. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  737. mtctr r4
  738. 1:
  739. dcbz r0, r3
  740. addi r3, r3, 32
  741. bdnz 1b
  742. /* Lock the data cache */
  743. mfspr r0, HID0
  744. ori r0, r0, 0x1000
  745. sync
  746. mtspr HID0, r0
  747. sync
  748. blr
  749. .globl unlock_ram_in_cache
  750. unlock_ram_in_cache:
  751. /* invalidate the INIT_RAM section */
  752. lis r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@h
  753. ori r3, r3, (CONFIG_SYS_INIT_RAM_ADDR & ~31)@l
  754. li r4, ((CONFIG_SYS_INIT_RAM_END & ~31) + \
  755. (CONFIG_SYS_INIT_RAM_ADDR & 31) + 31) / 32
  756. mtctr r4
  757. 1: icbi r0, r3
  758. addi r3, r3, 32
  759. bdnz 1b
  760. sync /* Wait for all icbi to complete on bus */
  761. isync
  762. /* Unlock the data cache and invalidate it */
  763. mfspr r0, HID0
  764. li r3,0x1000
  765. andc r0,r0,r3
  766. li r3,0x0400
  767. or r0,r0,r3
  768. sync
  769. mtspr HID0, r0
  770. sync
  771. blr
  772. #endif