cache.S 8.0 KB

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  1. #include <config.h>
  2. #include <74xx_7xx.h>
  3. #include <version.h>
  4. #include <ppc_asm.tmpl>
  5. #include <ppc_defs.h>
  6. #include <asm/cache.h>
  7. #include <asm/mmu.h>
  8. #ifndef CACHE_LINE_SIZE
  9. # define CACHE_LINE_SIZE L1_CACHE_BYTES
  10. #endif
  11. #if CACHE_LINE_SIZE == 128
  12. #define LG_CACHE_LINE_SIZE 7
  13. #elif CACHE_LINE_SIZE == 32
  14. #define LG_CACHE_LINE_SIZE 5
  15. #elif CACHE_LINE_SIZE == 16
  16. #define LG_CACHE_LINE_SIZE 4
  17. #elif CACHE_LINE_SIZE == 8
  18. #define LG_CACHE_LINE_SIZE 3
  19. #else
  20. # error "Invalid cache line size!"
  21. #endif
  22. /*
  23. * Invalidate L1 instruction cache.
  24. */
  25. _GLOBAL(invalidate_l1_instruction_cache)
  26. mfspr r3,PVR
  27. rlwinm r3,r3,16,16,31
  28. cmpi 0,r3,1
  29. beqlr /* for 601, do nothing */
  30. /* 603/604 processor - use invalidate-all bit in HID0 */
  31. mfspr r3,HID0
  32. ori r3,r3,HID0_ICFI
  33. mtspr HID0,r3
  34. isync
  35. blr
  36. /*
  37. * Invalidate L1 data cache.
  38. */
  39. _GLOBAL(invalidate_l1_data_cache)
  40. mfspr r3,HID0
  41. ori r3,r3,HID0_DCFI
  42. mtspr HID0,r3
  43. isync
  44. blr
  45. /*
  46. * Flush data cache.
  47. */
  48. _GLOBAL(flush_dcache)
  49. lis r3,0
  50. lis r5,CACHE_LINE_SIZE
  51. flush:
  52. cmp 0,1,r3,r5
  53. bge done
  54. lwz r5,0(r3)
  55. lis r5,CACHE_LINE_SIZE
  56. addi r3,r3,0x4
  57. b flush
  58. done:
  59. blr
  60. /*
  61. * Write any modified data cache blocks out to memory
  62. * and invalidate the corresponding instruction cache blocks.
  63. * This is a no-op on the 601.
  64. *
  65. * flush_icache_range(unsigned long start, unsigned long stop)
  66. */
  67. _GLOBAL(flush_icache_range)
  68. mfspr r5,PVR
  69. rlwinm r5,r5,16,16,31
  70. cmpi 0,r5,1
  71. beqlr /* for 601, do nothing */
  72. li r5,CACHE_LINE_SIZE-1
  73. andc r3,r3,r5
  74. subf r4,r3,r4
  75. add r4,r4,r5
  76. srwi. r4,r4,LG_CACHE_LINE_SIZE
  77. beqlr
  78. mtctr r4
  79. mr r6,r3
  80. 1: dcbst 0,r3
  81. addi r3,r3,CACHE_LINE_SIZE
  82. bdnz 1b
  83. sync /* wait for dcbst's to get to ram */
  84. mtctr r4
  85. 2: icbi 0,r6
  86. addi r6,r6,CACHE_LINE_SIZE
  87. bdnz 2b
  88. sync /* additional sync needed on g4 */
  89. isync
  90. blr
  91. /*
  92. * Write any modified data cache blocks out to memory.
  93. * Does not invalidate the corresponding cache lines (especially for
  94. * any corresponding instruction cache).
  95. *
  96. * clean_dcache_range(unsigned long start, unsigned long stop)
  97. */
  98. _GLOBAL(clean_dcache_range)
  99. li r5,CACHE_LINE_SIZE-1
  100. andc r3,r3,r5 /* align r3 down to cache line */
  101. subf r4,r3,r4 /* r4 = offset of stop from start of cache line */
  102. add r4,r4,r5 /* r4 += cache_line_size-1 */
  103. srwi. r4,r4,LG_CACHE_LINE_SIZE /* r4 = number of cache lines to flush */
  104. beqlr /* if r4 == 0 return */
  105. mtctr r4 /* ctr = r4 */
  106. sync
  107. 1: dcbst 0,r3
  108. addi r3,r3,CACHE_LINE_SIZE
  109. bdnz 1b
  110. sync /* wait for dcbst's to get to ram */
  111. blr
  112. /*
  113. * Write any modified data cache blocks out to memory
  114. * and invalidate the corresponding instruction cache blocks.
  115. *
  116. * flush_dcache_range(unsigned long start, unsigned long stop)
  117. */
  118. _GLOBAL(flush_dcache_range)
  119. li r5,CACHE_LINE_SIZE-1
  120. andc r3,r3,r5
  121. subf r4,r3,r4
  122. add r4,r4,r5
  123. srwi. r4,r4,LG_CACHE_LINE_SIZE
  124. beqlr
  125. mtctr r4
  126. sync
  127. 1: dcbf 0,r3
  128. addi r3,r3,CACHE_LINE_SIZE
  129. bdnz 1b
  130. sync /* wait for dcbf's to get to ram */
  131. blr
  132. /*
  133. * Like above, but invalidate the D-cache. This is used by the 8xx
  134. * to invalidate the cache so the PPC core doesn't get stale data
  135. * from the CPM (no cache snooping here :-).
  136. *
  137. * invalidate_dcache_range(unsigned long start, unsigned long stop)
  138. */
  139. _GLOBAL(invalidate_dcache_range)
  140. li r5,CACHE_LINE_SIZE-1
  141. andc r3,r3,r5
  142. subf r4,r3,r4
  143. add r4,r4,r5
  144. srwi. r4,r4,LG_CACHE_LINE_SIZE
  145. beqlr
  146. mtctr r4
  147. sync
  148. 1: dcbi 0,r3
  149. addi r3,r3,CACHE_LINE_SIZE
  150. bdnz 1b
  151. sync /* wait for dcbi's to get to ram */
  152. blr
  153. /*
  154. * Flush a particular page from the data cache to RAM.
  155. * Note: this is necessary because the instruction cache does *not*
  156. * snoop from the data cache.
  157. * This is a no-op on the 601 which has a unified cache.
  158. *
  159. * void __flush_page_to_ram(void *page)
  160. */
  161. _GLOBAL(__flush_page_to_ram)
  162. mfspr r5,PVR
  163. rlwinm r5,r5,16,16,31
  164. cmpi 0,r5,1
  165. beqlr /* for 601, do nothing */
  166. rlwinm r3,r3,0,0,19 /* Get page base address */
  167. li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
  168. mtctr r4
  169. mr r6,r3
  170. 0: dcbst 0,r3 /* Write line to ram */
  171. addi r3,r3,CACHE_LINE_SIZE
  172. bdnz 0b
  173. sync
  174. mtctr r4
  175. 1: icbi 0,r6
  176. addi r6,r6,CACHE_LINE_SIZE
  177. bdnz 1b
  178. sync
  179. isync
  180. blr
  181. /*
  182. * Flush a particular page from the instruction cache.
  183. * Note: this is necessary because the instruction cache does *not*
  184. * snoop from the data cache.
  185. * This is a no-op on the 601 which has a unified cache.
  186. *
  187. * void __flush_icache_page(void *page)
  188. */
  189. _GLOBAL(__flush_icache_page)
  190. mfspr r5,PVR
  191. rlwinm r5,r5,16,16,31
  192. cmpi 0,r5,1
  193. beqlr /* for 601, do nothing */
  194. li r4,4096/CACHE_LINE_SIZE /* Number of lines in a page */
  195. mtctr r4
  196. 1: icbi 0,r3
  197. addi r3,r3,CACHE_LINE_SIZE
  198. bdnz 1b
  199. sync
  200. isync
  201. blr
  202. /*
  203. * Clear a page using the dcbz instruction, which doesn't cause any
  204. * memory traffic (except to write out any cache lines which get
  205. * displaced). This only works on cacheable memory.
  206. */
  207. _GLOBAL(clear_page)
  208. li r0,4096/CACHE_LINE_SIZE
  209. mtctr r0
  210. 1: dcbz 0,r3
  211. addi r3,r3,CACHE_LINE_SIZE
  212. bdnz 1b
  213. blr
  214. /*
  215. * Enable L1 Instruction cache
  216. */
  217. _GLOBAL(icache_enable)
  218. mfspr r3, HID0
  219. li r5, HID0_ICFI|HID0_ILOCK
  220. andc r3, r3, r5
  221. ori r3, r3, HID0_ICE
  222. ori r5, r3, HID0_ICFI
  223. mtspr HID0, r5
  224. mtspr HID0, r3
  225. isync
  226. blr
  227. /*
  228. * Disable L1 Instruction cache
  229. */
  230. _GLOBAL(icache_disable)
  231. mflr r4
  232. bl invalidate_l1_instruction_cache /* uses r3 */
  233. sync
  234. mtlr r4
  235. mfspr r3, HID0
  236. li r5, 0
  237. ori r5, r5, HID0_ICE
  238. andc r3, r3, r5
  239. mtspr HID0, r3
  240. isync
  241. blr
  242. /*
  243. * Is instruction cache enabled?
  244. */
  245. _GLOBAL(icache_status)
  246. mfspr r3, HID0
  247. andi. r3, r3, HID0_ICE
  248. blr
  249. _GLOBAL(l1dcache_enable)
  250. mfspr r3, HID0
  251. li r5, HID0_DCFI|HID0_DLOCK
  252. andc r3, r3, r5
  253. mtspr HID0, r3 /* no invalidate, unlock */
  254. ori r3, r3, HID0_DCE
  255. ori r5, r3, HID0_DCFI
  256. mtspr HID0, r5 /* enable + invalidate */
  257. mtspr HID0, r3 /* enable */
  258. sync
  259. blr
  260. /*
  261. * Enable data cache(s) - L1 and optionally L2
  262. * Calls l2cache_enable. LR saved in r5
  263. */
  264. _GLOBAL(dcache_enable)
  265. mfspr r3, HID0
  266. li r5, HID0_DCFI|HID0_DLOCK
  267. andc r3, r3, r5
  268. mtspr HID0, r3 /* no invalidate, unlock */
  269. ori r3, r3, HID0_DCE
  270. ori r5, r3, HID0_DCFI
  271. mtspr HID0, r5 /* enable + invalidate */
  272. mtspr HID0, r3 /* enable */
  273. sync
  274. #ifdef CONFIG_SYS_L2
  275. mflr r5
  276. bl l2cache_enable /* uses r3 and r4 */
  277. sync
  278. mtlr r5
  279. #endif
  280. blr
  281. /*
  282. * Disable data cache(s) - L1 and optionally L2
  283. * Calls flush_dcache and l2cache_disable_no_flush.
  284. * LR saved in r4
  285. */
  286. _GLOBAL(dcache_disable)
  287. mflr r4 /* save link register */
  288. bl flush_dcache /* uses r3 and r5 */
  289. sync
  290. mfspr r3, HID0
  291. li r5, HID0_DCFI|HID0_DLOCK
  292. andc r3, r3, r5
  293. mtspr HID0, r3 /* no invalidate, unlock */
  294. li r5, HID0_DCE|HID0_DCFI
  295. andc r3, r3, r5 /* no enable, no invalidate */
  296. mtspr HID0, r3
  297. sync
  298. #ifdef CONFIG_SYS_L2
  299. bl l2cache_disable_no_flush /* uses r3 */
  300. #endif
  301. mtlr r4 /* restore link register */
  302. blr
  303. /*
  304. * Is data cache enabled?
  305. */
  306. _GLOBAL(dcache_status)
  307. mfspr r3, HID0
  308. andi. r3, r3, HID0_DCE
  309. blr
  310. /*
  311. * Invalidate L2 cache using L2I and polling L2IP or L2I
  312. */
  313. _GLOBAL(l2cache_invalidate)
  314. sync
  315. mfspr r3, l2cr
  316. oris r3, r3, L2CR_L2I@h
  317. sync
  318. mtspr l2cr, r3
  319. sync
  320. mfspr r3, PVR
  321. sync
  322. rlwinm r3, r3, 16,16,31
  323. cmpli 0,r3,0x8000 /* 7451, 7441 */
  324. beq 0,inv_7450
  325. cmpli 0,r3,0x8001 /* 7455, 7445 */
  326. beq 0,inv_7450
  327. cmpli 0,r3,0x8002 /* 7457, 7447 */
  328. beq 0,inv_7450
  329. cmpli 0,r3,0x8003 /* 7447A */
  330. beq 0,inv_7450
  331. cmpli 0,r3,0x8004 /* 7448 */
  332. beq 0,inv_7450
  333. invl2:
  334. mfspr r3, l2cr
  335. andi. r3, r3, L2CR_L2IP
  336. bne invl2
  337. /* turn off the global invalidate bit */
  338. mfspr r3, l2cr
  339. rlwinm r3, r3, 0, 11, 9
  340. sync
  341. mtspr l2cr, r3
  342. sync
  343. blr
  344. inv_7450:
  345. mfspr r3, l2cr
  346. andis. r3, r3, L2CR_L2I@h
  347. bne inv_7450
  348. blr
  349. /*
  350. * Enable L2 cache
  351. * Calls l2cache_invalidate. LR is saved in r4
  352. */
  353. _GLOBAL(l2cache_enable)
  354. mflr r4 /* save link register */
  355. bl l2cache_invalidate /* uses r3 */
  356. sync
  357. lis r3, L2_ENABLE@h
  358. ori r3, r3, L2_ENABLE@l
  359. mtspr l2cr, r3
  360. isync
  361. mtlr r4 /* restore link register */
  362. blr
  363. /*
  364. * Disable L2 cache
  365. * Calls flush_dcache. LR is saved in r4
  366. */
  367. _GLOBAL(l2cache_disable)
  368. mflr r4 /* save link register */
  369. bl flush_dcache /* uses r3 and r5 */
  370. sync
  371. mtlr r4 /* restore link register */
  372. l2cache_disable_no_flush: /* provide way to disable L2 w/o flushing */
  373. lis r3, L2_INIT@h
  374. ori r3, r3, L2_INIT@l
  375. mtspr l2cr, r3
  376. isync
  377. blr