pxa3xx_nand.c 47 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * drivers/mtd/nand/raw/pxa3xx_nand.c
  4. *
  5. * Copyright © 2005 Intel Corporation
  6. * Copyright © 2006 Marvell International Ltd.
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <fdtdec.h>
  11. #include <nand.h>
  12. #include <linux/errno.h>
  13. #include <asm/io.h>
  14. #include <asm/arch/cpu.h>
  15. #include <linux/mtd/mtd.h>
  16. #include <linux/mtd/rawnand.h>
  17. #include <linux/types.h>
  18. #include "pxa3xx_nand.h"
  19. DECLARE_GLOBAL_DATA_PTR;
  20. #define TIMEOUT_DRAIN_FIFO 5 /* in ms */
  21. #define CHIP_DELAY_TIMEOUT 200
  22. #define NAND_STOP_DELAY 40
  23. /*
  24. * Define a buffer size for the initial command that detects the flash device:
  25. * STATUS, READID and PARAM.
  26. * ONFI param page is 256 bytes, and there are three redundant copies
  27. * to be read. JEDEC param page is 512 bytes, and there are also three
  28. * redundant copies to be read.
  29. * Hence this buffer should be at least 512 x 3. Let's pick 2048.
  30. */
  31. #define INIT_BUFFER_SIZE 2048
  32. /* registers and bit definitions */
  33. #define NDCR (0x00) /* Control register */
  34. #define NDTR0CS0 (0x04) /* Timing Parameter 0 for CS0 */
  35. #define NDTR1CS0 (0x0C) /* Timing Parameter 1 for CS0 */
  36. #define NDSR (0x14) /* Status Register */
  37. #define NDPCR (0x18) /* Page Count Register */
  38. #define NDBDR0 (0x1C) /* Bad Block Register 0 */
  39. #define NDBDR1 (0x20) /* Bad Block Register 1 */
  40. #define NDECCCTRL (0x28) /* ECC control */
  41. #define NDDB (0x40) /* Data Buffer */
  42. #define NDCB0 (0x48) /* Command Buffer0 */
  43. #define NDCB1 (0x4C) /* Command Buffer1 */
  44. #define NDCB2 (0x50) /* Command Buffer2 */
  45. #define NDCR_SPARE_EN (0x1 << 31)
  46. #define NDCR_ECC_EN (0x1 << 30)
  47. #define NDCR_DMA_EN (0x1 << 29)
  48. #define NDCR_ND_RUN (0x1 << 28)
  49. #define NDCR_DWIDTH_C (0x1 << 27)
  50. #define NDCR_DWIDTH_M (0x1 << 26)
  51. #define NDCR_PAGE_SZ (0x1 << 24)
  52. #define NDCR_NCSX (0x1 << 23)
  53. #define NDCR_ND_MODE (0x3 << 21)
  54. #define NDCR_NAND_MODE (0x0)
  55. #define NDCR_CLR_PG_CNT (0x1 << 20)
  56. #define NFCV1_NDCR_ARB_CNTL (0x1 << 19)
  57. #define NDCR_RD_ID_CNT_MASK (0x7 << 16)
  58. #define NDCR_RD_ID_CNT(x) (((x) << 16) & NDCR_RD_ID_CNT_MASK)
  59. #define NDCR_RA_START (0x1 << 15)
  60. #define NDCR_PG_PER_BLK (0x1 << 14)
  61. #define NDCR_ND_ARB_EN (0x1 << 12)
  62. #define NDCR_INT_MASK (0xFFF)
  63. #define NDSR_MASK (0xfff)
  64. #define NDSR_ERR_CNT_OFF (16)
  65. #define NDSR_ERR_CNT_MASK (0x1f)
  66. #define NDSR_ERR_CNT(sr) ((sr >> NDSR_ERR_CNT_OFF) & NDSR_ERR_CNT_MASK)
  67. #define NDSR_RDY (0x1 << 12)
  68. #define NDSR_FLASH_RDY (0x1 << 11)
  69. #define NDSR_CS0_PAGED (0x1 << 10)
  70. #define NDSR_CS1_PAGED (0x1 << 9)
  71. #define NDSR_CS0_CMDD (0x1 << 8)
  72. #define NDSR_CS1_CMDD (0x1 << 7)
  73. #define NDSR_CS0_BBD (0x1 << 6)
  74. #define NDSR_CS1_BBD (0x1 << 5)
  75. #define NDSR_UNCORERR (0x1 << 4)
  76. #define NDSR_CORERR (0x1 << 3)
  77. #define NDSR_WRDREQ (0x1 << 2)
  78. #define NDSR_RDDREQ (0x1 << 1)
  79. #define NDSR_WRCMDREQ (0x1)
  80. #define NDCB0_LEN_OVRD (0x1 << 28)
  81. #define NDCB0_ST_ROW_EN (0x1 << 26)
  82. #define NDCB0_AUTO_RS (0x1 << 25)
  83. #define NDCB0_CSEL (0x1 << 24)
  84. #define NDCB0_EXT_CMD_TYPE_MASK (0x7 << 29)
  85. #define NDCB0_EXT_CMD_TYPE(x) (((x) << 29) & NDCB0_EXT_CMD_TYPE_MASK)
  86. #define NDCB0_CMD_TYPE_MASK (0x7 << 21)
  87. #define NDCB0_CMD_TYPE(x) (((x) << 21) & NDCB0_CMD_TYPE_MASK)
  88. #define NDCB0_NC (0x1 << 20)
  89. #define NDCB0_DBC (0x1 << 19)
  90. #define NDCB0_ADDR_CYC_MASK (0x7 << 16)
  91. #define NDCB0_ADDR_CYC(x) (((x) << 16) & NDCB0_ADDR_CYC_MASK)
  92. #define NDCB0_CMD2_MASK (0xff << 8)
  93. #define NDCB0_CMD1_MASK (0xff)
  94. #define NDCB0_ADDR_CYC_SHIFT (16)
  95. #define EXT_CMD_TYPE_DISPATCH 6 /* Command dispatch */
  96. #define EXT_CMD_TYPE_NAKED_RW 5 /* Naked read or Naked write */
  97. #define EXT_CMD_TYPE_READ 4 /* Read */
  98. #define EXT_CMD_TYPE_DISP_WR 4 /* Command dispatch with write */
  99. #define EXT_CMD_TYPE_FINAL 3 /* Final command */
  100. #define EXT_CMD_TYPE_LAST_RW 1 /* Last naked read/write */
  101. #define EXT_CMD_TYPE_MONO 0 /* Monolithic read/write */
  102. /*
  103. * This should be large enough to read 'ONFI' and 'JEDEC'.
  104. * Let's use 7 bytes, which is the maximum ID count supported
  105. * by the controller (see NDCR_RD_ID_CNT_MASK).
  106. */
  107. #define READ_ID_BYTES 7
  108. /* macros for registers read/write */
  109. #define nand_writel(info, off, val) \
  110. writel((val), (info)->mmio_base + (off))
  111. #define nand_readl(info, off) \
  112. readl((info)->mmio_base + (off))
  113. /* error code and state */
  114. enum {
  115. ERR_NONE = 0,
  116. ERR_DMABUSERR = -1,
  117. ERR_SENDCMD = -2,
  118. ERR_UNCORERR = -3,
  119. ERR_BBERR = -4,
  120. ERR_CORERR = -5,
  121. };
  122. enum {
  123. STATE_IDLE = 0,
  124. STATE_PREPARED,
  125. STATE_CMD_HANDLE,
  126. STATE_DMA_READING,
  127. STATE_DMA_WRITING,
  128. STATE_DMA_DONE,
  129. STATE_PIO_READING,
  130. STATE_PIO_WRITING,
  131. STATE_CMD_DONE,
  132. STATE_READY,
  133. };
  134. enum pxa3xx_nand_variant {
  135. PXA3XX_NAND_VARIANT_PXA,
  136. PXA3XX_NAND_VARIANT_ARMADA370,
  137. };
  138. struct pxa3xx_nand_host {
  139. struct nand_chip chip;
  140. void *info_data;
  141. /* page size of attached chip */
  142. int use_ecc;
  143. int cs;
  144. /* calculated from pxa3xx_nand_flash data */
  145. unsigned int col_addr_cycles;
  146. unsigned int row_addr_cycles;
  147. };
  148. struct pxa3xx_nand_info {
  149. struct nand_hw_control controller;
  150. struct pxa3xx_nand_platform_data *pdata;
  151. struct clk *clk;
  152. void __iomem *mmio_base;
  153. unsigned long mmio_phys;
  154. int cmd_complete, dev_ready;
  155. unsigned int buf_start;
  156. unsigned int buf_count;
  157. unsigned int buf_size;
  158. unsigned int data_buff_pos;
  159. unsigned int oob_buff_pos;
  160. unsigned char *data_buff;
  161. unsigned char *oob_buff;
  162. struct pxa3xx_nand_host *host[NUM_CHIP_SELECT];
  163. unsigned int state;
  164. /*
  165. * This driver supports NFCv1 (as found in PXA SoC)
  166. * and NFCv2 (as found in Armada 370/XP SoC).
  167. */
  168. enum pxa3xx_nand_variant variant;
  169. int cs;
  170. int use_ecc; /* use HW ECC ? */
  171. int ecc_bch; /* using BCH ECC? */
  172. int use_spare; /* use spare ? */
  173. int need_wait;
  174. /* Amount of real data per full chunk */
  175. unsigned int chunk_size;
  176. /* Amount of spare data per full chunk */
  177. unsigned int spare_size;
  178. /* Number of full chunks (i.e chunk_size + spare_size) */
  179. unsigned int nfullchunks;
  180. /*
  181. * Total number of chunks. If equal to nfullchunks, then there
  182. * are only full chunks. Otherwise, there is one last chunk of
  183. * size (last_chunk_size + last_spare_size)
  184. */
  185. unsigned int ntotalchunks;
  186. /* Amount of real data in the last chunk */
  187. unsigned int last_chunk_size;
  188. /* Amount of spare data in the last chunk */
  189. unsigned int last_spare_size;
  190. unsigned int ecc_size;
  191. unsigned int ecc_err_cnt;
  192. unsigned int max_bitflips;
  193. int retcode;
  194. /*
  195. * Variables only valid during command
  196. * execution. step_chunk_size and step_spare_size is the
  197. * amount of real data and spare data in the current
  198. * chunk. cur_chunk is the current chunk being
  199. * read/programmed.
  200. */
  201. unsigned int step_chunk_size;
  202. unsigned int step_spare_size;
  203. unsigned int cur_chunk;
  204. /* cached register value */
  205. uint32_t reg_ndcr;
  206. uint32_t ndtr0cs0;
  207. uint32_t ndtr1cs0;
  208. /* generated NDCBx register values */
  209. uint32_t ndcb0;
  210. uint32_t ndcb1;
  211. uint32_t ndcb2;
  212. uint32_t ndcb3;
  213. };
  214. static struct pxa3xx_nand_timing timing[] = {
  215. /*
  216. * tCH Enable signal hold time
  217. * tCS Enable signal setup time
  218. * tWH ND_nWE high duration
  219. * tWP ND_nWE pulse time
  220. * tRH ND_nRE high duration
  221. * tRP ND_nRE pulse width
  222. * tR ND_nWE high to ND_nRE low for read
  223. * tWHR ND_nWE high to ND_nRE low for status read
  224. * tAR ND_ALE low to ND_nRE low delay
  225. */
  226. /*ch cs wh wp rh rp r whr ar */
  227. { 40, 80, 60, 100, 80, 100, 90000, 400, 40, },
  228. { 10, 0, 20, 40, 30, 40, 11123, 110, 10, },
  229. { 10, 25, 15, 25, 15, 30, 25000, 60, 10, },
  230. { 10, 35, 15, 25, 15, 25, 25000, 60, 10, },
  231. { 5, 20, 10, 12, 10, 12, 25000, 60, 10, },
  232. };
  233. static struct pxa3xx_nand_flash builtin_flash_types[] = {
  234. /*
  235. * chip_id
  236. * flash_width Width of Flash memory (DWIDTH_M)
  237. * dfc_width Width of flash controller(DWIDTH_C)
  238. * *timing
  239. * http://www.linux-mtd.infradead.org/nand-data/nanddata.html
  240. */
  241. { 0x46ec, 16, 16, &timing[1] },
  242. { 0xdaec, 8, 8, &timing[1] },
  243. { 0xd7ec, 8, 8, &timing[1] },
  244. { 0xa12c, 8, 8, &timing[2] },
  245. { 0xb12c, 16, 16, &timing[2] },
  246. { 0xdc2c, 8, 8, &timing[2] },
  247. { 0xcc2c, 16, 16, &timing[2] },
  248. { 0xba20, 16, 16, &timing[3] },
  249. { 0xda98, 8, 8, &timing[4] },
  250. };
  251. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  252. static u8 bbt_pattern[] = {'M', 'V', 'B', 'b', 't', '0' };
  253. static u8 bbt_mirror_pattern[] = {'1', 't', 'b', 'B', 'V', 'M' };
  254. static struct nand_bbt_descr bbt_main_descr = {
  255. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  256. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  257. .offs = 8,
  258. .len = 6,
  259. .veroffs = 14,
  260. .maxblocks = 8, /* Last 8 blocks in each chip */
  261. .pattern = bbt_pattern
  262. };
  263. static struct nand_bbt_descr bbt_mirror_descr = {
  264. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE
  265. | NAND_BBT_2BIT | NAND_BBT_VERSION,
  266. .offs = 8,
  267. .len = 6,
  268. .veroffs = 14,
  269. .maxblocks = 8, /* Last 8 blocks in each chip */
  270. .pattern = bbt_mirror_pattern
  271. };
  272. #endif
  273. static struct nand_ecclayout ecc_layout_2KB_bch4bit = {
  274. .eccbytes = 32,
  275. .eccpos = {
  276. 32, 33, 34, 35, 36, 37, 38, 39,
  277. 40, 41, 42, 43, 44, 45, 46, 47,
  278. 48, 49, 50, 51, 52, 53, 54, 55,
  279. 56, 57, 58, 59, 60, 61, 62, 63},
  280. .oobfree = { {2, 30} }
  281. };
  282. static struct nand_ecclayout ecc_layout_2KB_bch8bit = {
  283. .eccbytes = 64,
  284. .eccpos = {
  285. 64, 65, 66, 67, 68, 69, 70, 71,
  286. 72, 73, 74, 75, 76, 77, 78, 79,
  287. 80, 81, 82, 83, 84, 85, 86, 87,
  288. 88, 89, 90, 91, 92, 93, 94, 95,
  289. 96, 97, 98, 99, 100, 101, 102, 103,
  290. 104, 105, 106, 107, 108, 109, 110, 111,
  291. 112, 113, 114, 115, 116, 117, 118, 119,
  292. 120, 121, 122, 123, 124, 125, 126, 127},
  293. .oobfree = { {1, 4}, {6, 26} }
  294. };
  295. static struct nand_ecclayout ecc_layout_4KB_bch4bit = {
  296. .eccbytes = 64,
  297. .eccpos = {
  298. 32, 33, 34, 35, 36, 37, 38, 39,
  299. 40, 41, 42, 43, 44, 45, 46, 47,
  300. 48, 49, 50, 51, 52, 53, 54, 55,
  301. 56, 57, 58, 59, 60, 61, 62, 63,
  302. 96, 97, 98, 99, 100, 101, 102, 103,
  303. 104, 105, 106, 107, 108, 109, 110, 111,
  304. 112, 113, 114, 115, 116, 117, 118, 119,
  305. 120, 121, 122, 123, 124, 125, 126, 127},
  306. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  307. .oobfree = { {6, 26}, { 64, 32} }
  308. };
  309. static struct nand_ecclayout ecc_layout_8KB_bch4bit = {
  310. .eccbytes = 128,
  311. .eccpos = {
  312. 32, 33, 34, 35, 36, 37, 38, 39,
  313. 40, 41, 42, 43, 44, 45, 46, 47,
  314. 48, 49, 50, 51, 52, 53, 54, 55,
  315. 56, 57, 58, 59, 60, 61, 62, 63,
  316. 96, 97, 98, 99, 100, 101, 102, 103,
  317. 104, 105, 106, 107, 108, 109, 110, 111,
  318. 112, 113, 114, 115, 116, 117, 118, 119,
  319. 120, 121, 122, 123, 124, 125, 126, 127,
  320. 160, 161, 162, 163, 164, 165, 166, 167,
  321. 168, 169, 170, 171, 172, 173, 174, 175,
  322. 176, 177, 178, 179, 180, 181, 182, 183,
  323. 184, 185, 186, 187, 188, 189, 190, 191,
  324. 224, 225, 226, 227, 228, 229, 230, 231,
  325. 232, 233, 234, 235, 236, 237, 238, 239,
  326. 240, 241, 242, 243, 244, 245, 246, 247,
  327. 248, 249, 250, 251, 252, 253, 254, 255},
  328. /* Bootrom looks in bytes 0 & 5 for bad blocks */
  329. .oobfree = { {1, 4}, {6, 26}, { 64, 32}, {128, 32}, {192, 32} }
  330. };
  331. static struct nand_ecclayout ecc_layout_4KB_bch8bit = {
  332. .eccbytes = 128,
  333. .eccpos = {
  334. 32, 33, 34, 35, 36, 37, 38, 39,
  335. 40, 41, 42, 43, 44, 45, 46, 47,
  336. 48, 49, 50, 51, 52, 53, 54, 55,
  337. 56, 57, 58, 59, 60, 61, 62, 63},
  338. .oobfree = { }
  339. };
  340. static struct nand_ecclayout ecc_layout_8KB_bch8bit = {
  341. .eccbytes = 256,
  342. .eccpos = {},
  343. /* HW ECC handles all ECC data and all spare area is free for OOB */
  344. .oobfree = {{0, 160} }
  345. };
  346. #define NDTR0_tCH(c) (min((c), 7) << 19)
  347. #define NDTR0_tCS(c) (min((c), 7) << 16)
  348. #define NDTR0_tWH(c) (min((c), 7) << 11)
  349. #define NDTR0_tWP(c) (min((c), 7) << 8)
  350. #define NDTR0_tRH(c) (min((c), 7) << 3)
  351. #define NDTR0_tRP(c) (min((c), 7) << 0)
  352. #define NDTR1_tR(c) (min((c), 65535) << 16)
  353. #define NDTR1_tWHR(c) (min((c), 15) << 4)
  354. #define NDTR1_tAR(c) (min((c), 15) << 0)
  355. /* convert nano-seconds to nand flash controller clock cycles */
  356. #define ns2cycle(ns, clk) (int)((ns) * (clk / 1000000) / 1000)
  357. static enum pxa3xx_nand_variant pxa3xx_nand_get_variant(void)
  358. {
  359. /* We only support the Armada 370/XP/38x for now */
  360. return PXA3XX_NAND_VARIANT_ARMADA370;
  361. }
  362. static void pxa3xx_nand_set_timing(struct pxa3xx_nand_host *host,
  363. const struct pxa3xx_nand_timing *t)
  364. {
  365. struct pxa3xx_nand_info *info = host->info_data;
  366. unsigned long nand_clk = mvebu_get_nand_clock();
  367. uint32_t ndtr0, ndtr1;
  368. ndtr0 = NDTR0_tCH(ns2cycle(t->tCH, nand_clk)) |
  369. NDTR0_tCS(ns2cycle(t->tCS, nand_clk)) |
  370. NDTR0_tWH(ns2cycle(t->tWH, nand_clk)) |
  371. NDTR0_tWP(ns2cycle(t->tWP, nand_clk)) |
  372. NDTR0_tRH(ns2cycle(t->tRH, nand_clk)) |
  373. NDTR0_tRP(ns2cycle(t->tRP, nand_clk));
  374. ndtr1 = NDTR1_tR(ns2cycle(t->tR, nand_clk)) |
  375. NDTR1_tWHR(ns2cycle(t->tWHR, nand_clk)) |
  376. NDTR1_tAR(ns2cycle(t->tAR, nand_clk));
  377. info->ndtr0cs0 = ndtr0;
  378. info->ndtr1cs0 = ndtr1;
  379. nand_writel(info, NDTR0CS0, ndtr0);
  380. nand_writel(info, NDTR1CS0, ndtr1);
  381. }
  382. static void pxa3xx_nand_set_sdr_timing(struct pxa3xx_nand_host *host,
  383. const struct nand_sdr_timings *t)
  384. {
  385. struct pxa3xx_nand_info *info = host->info_data;
  386. struct nand_chip *chip = &host->chip;
  387. unsigned long nand_clk = mvebu_get_nand_clock();
  388. uint32_t ndtr0, ndtr1;
  389. u32 tCH_min = DIV_ROUND_UP(t->tCH_min, 1000);
  390. u32 tCS_min = DIV_ROUND_UP(t->tCS_min, 1000);
  391. u32 tWH_min = DIV_ROUND_UP(t->tWH_min, 1000);
  392. u32 tWP_min = DIV_ROUND_UP(t->tWC_min - t->tWH_min, 1000);
  393. u32 tREH_min = DIV_ROUND_UP(t->tREH_min, 1000);
  394. u32 tRP_min = DIV_ROUND_UP(t->tRC_min - t->tREH_min, 1000);
  395. u32 tR = chip->chip_delay * 1000;
  396. u32 tWHR_min = DIV_ROUND_UP(t->tWHR_min, 1000);
  397. u32 tAR_min = DIV_ROUND_UP(t->tAR_min, 1000);
  398. /* fallback to a default value if tR = 0 */
  399. if (!tR)
  400. tR = 20000;
  401. ndtr0 = NDTR0_tCH(ns2cycle(tCH_min, nand_clk)) |
  402. NDTR0_tCS(ns2cycle(tCS_min, nand_clk)) |
  403. NDTR0_tWH(ns2cycle(tWH_min, nand_clk)) |
  404. NDTR0_tWP(ns2cycle(tWP_min, nand_clk)) |
  405. NDTR0_tRH(ns2cycle(tREH_min, nand_clk)) |
  406. NDTR0_tRP(ns2cycle(tRP_min, nand_clk));
  407. ndtr1 = NDTR1_tR(ns2cycle(tR, nand_clk)) |
  408. NDTR1_tWHR(ns2cycle(tWHR_min, nand_clk)) |
  409. NDTR1_tAR(ns2cycle(tAR_min, nand_clk));
  410. info->ndtr0cs0 = ndtr0;
  411. info->ndtr1cs0 = ndtr1;
  412. nand_writel(info, NDTR0CS0, ndtr0);
  413. nand_writel(info, NDTR1CS0, ndtr1);
  414. }
  415. static int pxa3xx_nand_init_timings(struct pxa3xx_nand_host *host)
  416. {
  417. const struct nand_sdr_timings *timings;
  418. struct nand_chip *chip = &host->chip;
  419. struct pxa3xx_nand_info *info = host->info_data;
  420. const struct pxa3xx_nand_flash *f = NULL;
  421. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  422. int mode, id, ntypes, i;
  423. mode = onfi_get_async_timing_mode(chip);
  424. if (mode == ONFI_TIMING_MODE_UNKNOWN) {
  425. ntypes = ARRAY_SIZE(builtin_flash_types);
  426. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  427. id = chip->read_byte(mtd);
  428. id |= chip->read_byte(mtd) << 0x8;
  429. for (i = 0; i < ntypes; i++) {
  430. f = &builtin_flash_types[i];
  431. if (f->chip_id == id)
  432. break;
  433. }
  434. if (i == ntypes) {
  435. dev_err(&info->pdev->dev, "Error: timings not found\n");
  436. return -EINVAL;
  437. }
  438. pxa3xx_nand_set_timing(host, f->timing);
  439. if (f->flash_width == 16) {
  440. info->reg_ndcr |= NDCR_DWIDTH_M;
  441. chip->options |= NAND_BUSWIDTH_16;
  442. }
  443. info->reg_ndcr |= (f->dfc_width == 16) ? NDCR_DWIDTH_C : 0;
  444. } else {
  445. mode = fls(mode) - 1;
  446. if (mode < 0)
  447. mode = 0;
  448. timings = onfi_async_timing_mode_to_sdr_timings(mode);
  449. if (IS_ERR(timings))
  450. return PTR_ERR(timings);
  451. pxa3xx_nand_set_sdr_timing(host, timings);
  452. }
  453. return 0;
  454. }
  455. /**
  456. * NOTE: it is a must to set ND_RUN first, then write
  457. * command buffer, otherwise, it does not work.
  458. * We enable all the interrupt at the same time, and
  459. * let pxa3xx_nand_irq to handle all logic.
  460. */
  461. static void pxa3xx_nand_start(struct pxa3xx_nand_info *info)
  462. {
  463. uint32_t ndcr;
  464. ndcr = info->reg_ndcr;
  465. if (info->use_ecc) {
  466. ndcr |= NDCR_ECC_EN;
  467. if (info->ecc_bch)
  468. nand_writel(info, NDECCCTRL, 0x1);
  469. } else {
  470. ndcr &= ~NDCR_ECC_EN;
  471. if (info->ecc_bch)
  472. nand_writel(info, NDECCCTRL, 0x0);
  473. }
  474. ndcr &= ~NDCR_DMA_EN;
  475. if (info->use_spare)
  476. ndcr |= NDCR_SPARE_EN;
  477. else
  478. ndcr &= ~NDCR_SPARE_EN;
  479. ndcr |= NDCR_ND_RUN;
  480. /* clear status bits and run */
  481. nand_writel(info, NDSR, NDSR_MASK);
  482. nand_writel(info, NDCR, 0);
  483. nand_writel(info, NDCR, ndcr);
  484. }
  485. static void disable_int(struct pxa3xx_nand_info *info, uint32_t int_mask)
  486. {
  487. uint32_t ndcr;
  488. ndcr = nand_readl(info, NDCR);
  489. nand_writel(info, NDCR, ndcr | int_mask);
  490. }
  491. static void drain_fifo(struct pxa3xx_nand_info *info, void *data, int len)
  492. {
  493. if (info->ecc_bch) {
  494. u32 ts;
  495. /*
  496. * According to the datasheet, when reading from NDDB
  497. * with BCH enabled, after each 32 bytes reads, we
  498. * have to make sure that the NDSR.RDDREQ bit is set.
  499. *
  500. * Drain the FIFO 8 32 bits reads at a time, and skip
  501. * the polling on the last read.
  502. */
  503. while (len > 8) {
  504. readsl(info->mmio_base + NDDB, data, 8);
  505. ts = get_timer(0);
  506. while (!(nand_readl(info, NDSR) & NDSR_RDDREQ)) {
  507. if (get_timer(ts) > TIMEOUT_DRAIN_FIFO) {
  508. dev_err(&info->pdev->dev,
  509. "Timeout on RDDREQ while draining the FIFO\n");
  510. return;
  511. }
  512. }
  513. data += 32;
  514. len -= 8;
  515. }
  516. }
  517. readsl(info->mmio_base + NDDB, data, len);
  518. }
  519. static void handle_data_pio(struct pxa3xx_nand_info *info)
  520. {
  521. switch (info->state) {
  522. case STATE_PIO_WRITING:
  523. if (info->step_chunk_size)
  524. writesl(info->mmio_base + NDDB,
  525. info->data_buff + info->data_buff_pos,
  526. DIV_ROUND_UP(info->step_chunk_size, 4));
  527. if (info->step_spare_size)
  528. writesl(info->mmio_base + NDDB,
  529. info->oob_buff + info->oob_buff_pos,
  530. DIV_ROUND_UP(info->step_spare_size, 4));
  531. break;
  532. case STATE_PIO_READING:
  533. if (info->step_chunk_size)
  534. drain_fifo(info,
  535. info->data_buff + info->data_buff_pos,
  536. DIV_ROUND_UP(info->step_chunk_size, 4));
  537. if (info->step_spare_size)
  538. drain_fifo(info,
  539. info->oob_buff + info->oob_buff_pos,
  540. DIV_ROUND_UP(info->step_spare_size, 4));
  541. break;
  542. default:
  543. dev_err(&info->pdev->dev, "%s: invalid state %d\n", __func__,
  544. info->state);
  545. BUG();
  546. }
  547. /* Update buffer pointers for multi-page read/write */
  548. info->data_buff_pos += info->step_chunk_size;
  549. info->oob_buff_pos += info->step_spare_size;
  550. }
  551. static void pxa3xx_nand_irq_thread(struct pxa3xx_nand_info *info)
  552. {
  553. handle_data_pio(info);
  554. info->state = STATE_CMD_DONE;
  555. nand_writel(info, NDSR, NDSR_WRDREQ | NDSR_RDDREQ);
  556. }
  557. static irqreturn_t pxa3xx_nand_irq(struct pxa3xx_nand_info *info)
  558. {
  559. unsigned int status, is_completed = 0, is_ready = 0;
  560. unsigned int ready, cmd_done;
  561. irqreturn_t ret = IRQ_HANDLED;
  562. if (info->cs == 0) {
  563. ready = NDSR_FLASH_RDY;
  564. cmd_done = NDSR_CS0_CMDD;
  565. } else {
  566. ready = NDSR_RDY;
  567. cmd_done = NDSR_CS1_CMDD;
  568. }
  569. /* TODO - find out why we need the delay during write operation. */
  570. ndelay(1);
  571. status = nand_readl(info, NDSR);
  572. if (status & NDSR_UNCORERR)
  573. info->retcode = ERR_UNCORERR;
  574. if (status & NDSR_CORERR) {
  575. info->retcode = ERR_CORERR;
  576. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370 &&
  577. info->ecc_bch)
  578. info->ecc_err_cnt = NDSR_ERR_CNT(status);
  579. else
  580. info->ecc_err_cnt = 1;
  581. /*
  582. * Each chunk composing a page is corrected independently,
  583. * and we need to store maximum number of corrected bitflips
  584. * to return it to the MTD layer in ecc.read_page().
  585. */
  586. info->max_bitflips = max_t(unsigned int,
  587. info->max_bitflips,
  588. info->ecc_err_cnt);
  589. }
  590. if (status & (NDSR_RDDREQ | NDSR_WRDREQ)) {
  591. info->state = (status & NDSR_RDDREQ) ?
  592. STATE_PIO_READING : STATE_PIO_WRITING;
  593. /* Call the IRQ thread in U-Boot directly */
  594. pxa3xx_nand_irq_thread(info);
  595. return 0;
  596. }
  597. if (status & cmd_done) {
  598. info->state = STATE_CMD_DONE;
  599. is_completed = 1;
  600. }
  601. if (status & ready) {
  602. info->state = STATE_READY;
  603. is_ready = 1;
  604. }
  605. /*
  606. * Clear all status bit before issuing the next command, which
  607. * can and will alter the status bits and will deserve a new
  608. * interrupt on its own. This lets the controller exit the IRQ
  609. */
  610. nand_writel(info, NDSR, status);
  611. if (status & NDSR_WRCMDREQ) {
  612. status &= ~NDSR_WRCMDREQ;
  613. info->state = STATE_CMD_HANDLE;
  614. /*
  615. * Command buffer registers NDCB{0-2} (and optionally NDCB3)
  616. * must be loaded by writing directly either 12 or 16
  617. * bytes directly to NDCB0, four bytes at a time.
  618. *
  619. * Direct write access to NDCB1, NDCB2 and NDCB3 is ignored
  620. * but each NDCBx register can be read.
  621. */
  622. nand_writel(info, NDCB0, info->ndcb0);
  623. nand_writel(info, NDCB0, info->ndcb1);
  624. nand_writel(info, NDCB0, info->ndcb2);
  625. /* NDCB3 register is available in NFCv2 (Armada 370/XP SoC) */
  626. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  627. nand_writel(info, NDCB0, info->ndcb3);
  628. }
  629. if (is_completed)
  630. info->cmd_complete = 1;
  631. if (is_ready)
  632. info->dev_ready = 1;
  633. return ret;
  634. }
  635. static inline int is_buf_blank(uint8_t *buf, size_t len)
  636. {
  637. for (; len > 0; len--)
  638. if (*buf++ != 0xff)
  639. return 0;
  640. return 1;
  641. }
  642. static void set_command_address(struct pxa3xx_nand_info *info,
  643. unsigned int page_size, uint16_t column, int page_addr)
  644. {
  645. /* small page addr setting */
  646. if (page_size < info->chunk_size) {
  647. info->ndcb1 = ((page_addr & 0xFFFFFF) << 8)
  648. | (column & 0xFF);
  649. info->ndcb2 = 0;
  650. } else {
  651. info->ndcb1 = ((page_addr & 0xFFFF) << 16)
  652. | (column & 0xFFFF);
  653. if (page_addr & 0xFF0000)
  654. info->ndcb2 = (page_addr & 0xFF0000) >> 16;
  655. else
  656. info->ndcb2 = 0;
  657. }
  658. }
  659. static void prepare_start_command(struct pxa3xx_nand_info *info, int command)
  660. {
  661. struct pxa3xx_nand_host *host = info->host[info->cs];
  662. struct mtd_info *mtd = nand_to_mtd(&host->chip);
  663. /* reset data and oob column point to handle data */
  664. info->buf_start = 0;
  665. info->buf_count = 0;
  666. info->data_buff_pos = 0;
  667. info->oob_buff_pos = 0;
  668. info->step_chunk_size = 0;
  669. info->step_spare_size = 0;
  670. info->cur_chunk = 0;
  671. info->use_ecc = 0;
  672. info->use_spare = 1;
  673. info->retcode = ERR_NONE;
  674. info->ecc_err_cnt = 0;
  675. info->ndcb3 = 0;
  676. info->need_wait = 0;
  677. switch (command) {
  678. case NAND_CMD_READ0:
  679. case NAND_CMD_READOOB:
  680. case NAND_CMD_PAGEPROG:
  681. info->use_ecc = 1;
  682. break;
  683. case NAND_CMD_PARAM:
  684. info->use_spare = 0;
  685. break;
  686. default:
  687. info->ndcb1 = 0;
  688. info->ndcb2 = 0;
  689. break;
  690. }
  691. /*
  692. * If we are about to issue a read command, or about to set
  693. * the write address, then clean the data buffer.
  694. */
  695. if (command == NAND_CMD_READ0 ||
  696. command == NAND_CMD_READOOB ||
  697. command == NAND_CMD_SEQIN) {
  698. info->buf_count = mtd->writesize + mtd->oobsize;
  699. memset(info->data_buff, 0xFF, info->buf_count);
  700. }
  701. }
  702. static int prepare_set_command(struct pxa3xx_nand_info *info, int command,
  703. int ext_cmd_type, uint16_t column, int page_addr)
  704. {
  705. int addr_cycle, exec_cmd;
  706. struct pxa3xx_nand_host *host;
  707. struct mtd_info *mtd;
  708. host = info->host[info->cs];
  709. mtd = nand_to_mtd(&host->chip);
  710. addr_cycle = 0;
  711. exec_cmd = 1;
  712. if (info->cs != 0)
  713. info->ndcb0 = NDCB0_CSEL;
  714. else
  715. info->ndcb0 = 0;
  716. if (command == NAND_CMD_SEQIN)
  717. exec_cmd = 0;
  718. addr_cycle = NDCB0_ADDR_CYC(host->row_addr_cycles
  719. + host->col_addr_cycles);
  720. switch (command) {
  721. case NAND_CMD_READOOB:
  722. case NAND_CMD_READ0:
  723. info->buf_start = column;
  724. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  725. | addr_cycle
  726. | NAND_CMD_READ0;
  727. if (command == NAND_CMD_READOOB)
  728. info->buf_start += mtd->writesize;
  729. if (info->cur_chunk < info->nfullchunks) {
  730. info->step_chunk_size = info->chunk_size;
  731. info->step_spare_size = info->spare_size;
  732. } else {
  733. info->step_chunk_size = info->last_chunk_size;
  734. info->step_spare_size = info->last_spare_size;
  735. }
  736. /*
  737. * Multiple page read needs an 'extended command type' field,
  738. * which is either naked-read or last-read according to the
  739. * state.
  740. */
  741. if (mtd->writesize == info->chunk_size) {
  742. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8);
  743. } else if (mtd->writesize > info->chunk_size) {
  744. info->ndcb0 |= NDCB0_DBC | (NAND_CMD_READSTART << 8)
  745. | NDCB0_LEN_OVRD
  746. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  747. info->ndcb3 = info->step_chunk_size +
  748. info->step_spare_size;
  749. }
  750. set_command_address(info, mtd->writesize, column, page_addr);
  751. break;
  752. case NAND_CMD_SEQIN:
  753. info->buf_start = column;
  754. set_command_address(info, mtd->writesize, 0, page_addr);
  755. /*
  756. * Multiple page programming needs to execute the initial
  757. * SEQIN command that sets the page address.
  758. */
  759. if (mtd->writesize > info->chunk_size) {
  760. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  761. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  762. | addr_cycle
  763. | command;
  764. exec_cmd = 1;
  765. }
  766. break;
  767. case NAND_CMD_PAGEPROG:
  768. if (is_buf_blank(info->data_buff,
  769. (mtd->writesize + mtd->oobsize))) {
  770. exec_cmd = 0;
  771. break;
  772. }
  773. if (info->cur_chunk < info->nfullchunks) {
  774. info->step_chunk_size = info->chunk_size;
  775. info->step_spare_size = info->spare_size;
  776. } else {
  777. info->step_chunk_size = info->last_chunk_size;
  778. info->step_spare_size = info->last_spare_size;
  779. }
  780. /* Second command setting for large pages */
  781. if (mtd->writesize > info->chunk_size) {
  782. /*
  783. * Multiple page write uses the 'extended command'
  784. * field. This can be used to issue a command dispatch
  785. * or a naked-write depending on the current stage.
  786. */
  787. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  788. | NDCB0_LEN_OVRD
  789. | NDCB0_EXT_CMD_TYPE(ext_cmd_type);
  790. info->ndcb3 = info->step_chunk_size +
  791. info->step_spare_size;
  792. /*
  793. * This is the command dispatch that completes a chunked
  794. * page program operation.
  795. */
  796. if (info->cur_chunk == info->ntotalchunks) {
  797. info->ndcb0 = NDCB0_CMD_TYPE(0x1)
  798. | NDCB0_EXT_CMD_TYPE(ext_cmd_type)
  799. | command;
  800. info->ndcb1 = 0;
  801. info->ndcb2 = 0;
  802. info->ndcb3 = 0;
  803. }
  804. } else {
  805. info->ndcb0 |= NDCB0_CMD_TYPE(0x1)
  806. | NDCB0_AUTO_RS
  807. | NDCB0_ST_ROW_EN
  808. | NDCB0_DBC
  809. | (NAND_CMD_PAGEPROG << 8)
  810. | NAND_CMD_SEQIN
  811. | addr_cycle;
  812. }
  813. break;
  814. case NAND_CMD_PARAM:
  815. info->buf_count = INIT_BUFFER_SIZE;
  816. info->ndcb0 |= NDCB0_CMD_TYPE(0)
  817. | NDCB0_ADDR_CYC(1)
  818. | NDCB0_LEN_OVRD
  819. | command;
  820. info->ndcb1 = (column & 0xFF);
  821. info->ndcb3 = INIT_BUFFER_SIZE;
  822. info->step_chunk_size = INIT_BUFFER_SIZE;
  823. break;
  824. case NAND_CMD_READID:
  825. info->buf_count = READ_ID_BYTES;
  826. info->ndcb0 |= NDCB0_CMD_TYPE(3)
  827. | NDCB0_ADDR_CYC(1)
  828. | command;
  829. info->ndcb1 = (column & 0xFF);
  830. info->step_chunk_size = 8;
  831. break;
  832. case NAND_CMD_STATUS:
  833. info->buf_count = 1;
  834. info->ndcb0 |= NDCB0_CMD_TYPE(4)
  835. | NDCB0_ADDR_CYC(1)
  836. | command;
  837. info->step_chunk_size = 8;
  838. break;
  839. case NAND_CMD_ERASE1:
  840. info->ndcb0 |= NDCB0_CMD_TYPE(2)
  841. | NDCB0_AUTO_RS
  842. | NDCB0_ADDR_CYC(3)
  843. | NDCB0_DBC
  844. | (NAND_CMD_ERASE2 << 8)
  845. | NAND_CMD_ERASE1;
  846. info->ndcb1 = page_addr;
  847. info->ndcb2 = 0;
  848. break;
  849. case NAND_CMD_RESET:
  850. info->ndcb0 |= NDCB0_CMD_TYPE(5)
  851. | command;
  852. break;
  853. case NAND_CMD_ERASE2:
  854. exec_cmd = 0;
  855. break;
  856. default:
  857. exec_cmd = 0;
  858. dev_err(&info->pdev->dev, "non-supported command %x\n",
  859. command);
  860. break;
  861. }
  862. return exec_cmd;
  863. }
  864. static void nand_cmdfunc(struct mtd_info *mtd, unsigned command,
  865. int column, int page_addr)
  866. {
  867. struct nand_chip *chip = mtd_to_nand(mtd);
  868. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  869. struct pxa3xx_nand_info *info = host->info_data;
  870. int exec_cmd;
  871. /*
  872. * if this is a x16 device ,then convert the input
  873. * "byte" address into a "word" address appropriate
  874. * for indexing a word-oriented device
  875. */
  876. if (info->reg_ndcr & NDCR_DWIDTH_M)
  877. column /= 2;
  878. /*
  879. * There may be different NAND chip hooked to
  880. * different chip select, so check whether
  881. * chip select has been changed, if yes, reset the timing
  882. */
  883. if (info->cs != host->cs) {
  884. info->cs = host->cs;
  885. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  886. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  887. }
  888. prepare_start_command(info, command);
  889. info->state = STATE_PREPARED;
  890. exec_cmd = prepare_set_command(info, command, 0, column, page_addr);
  891. if (exec_cmd) {
  892. u32 ts;
  893. info->cmd_complete = 0;
  894. info->dev_ready = 0;
  895. info->need_wait = 1;
  896. pxa3xx_nand_start(info);
  897. ts = get_timer(0);
  898. while (1) {
  899. u32 status;
  900. status = nand_readl(info, NDSR);
  901. if (status)
  902. pxa3xx_nand_irq(info);
  903. if (info->cmd_complete)
  904. break;
  905. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  906. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  907. return;
  908. }
  909. }
  910. }
  911. info->state = STATE_IDLE;
  912. }
  913. static void nand_cmdfunc_extended(struct mtd_info *mtd,
  914. const unsigned command,
  915. int column, int page_addr)
  916. {
  917. struct nand_chip *chip = mtd_to_nand(mtd);
  918. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  919. struct pxa3xx_nand_info *info = host->info_data;
  920. int exec_cmd, ext_cmd_type;
  921. /*
  922. * if this is a x16 device then convert the input
  923. * "byte" address into a "word" address appropriate
  924. * for indexing a word-oriented device
  925. */
  926. if (info->reg_ndcr & NDCR_DWIDTH_M)
  927. column /= 2;
  928. /*
  929. * There may be different NAND chip hooked to
  930. * different chip select, so check whether
  931. * chip select has been changed, if yes, reset the timing
  932. */
  933. if (info->cs != host->cs) {
  934. info->cs = host->cs;
  935. nand_writel(info, NDTR0CS0, info->ndtr0cs0);
  936. nand_writel(info, NDTR1CS0, info->ndtr1cs0);
  937. }
  938. /* Select the extended command for the first command */
  939. switch (command) {
  940. case NAND_CMD_READ0:
  941. case NAND_CMD_READOOB:
  942. ext_cmd_type = EXT_CMD_TYPE_MONO;
  943. break;
  944. case NAND_CMD_SEQIN:
  945. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  946. break;
  947. case NAND_CMD_PAGEPROG:
  948. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  949. break;
  950. default:
  951. ext_cmd_type = 0;
  952. break;
  953. }
  954. prepare_start_command(info, command);
  955. /*
  956. * Prepare the "is ready" completion before starting a command
  957. * transaction sequence. If the command is not executed the
  958. * completion will be completed, see below.
  959. *
  960. * We can do that inside the loop because the command variable
  961. * is invariant and thus so is the exec_cmd.
  962. */
  963. info->need_wait = 1;
  964. info->dev_ready = 0;
  965. do {
  966. u32 ts;
  967. info->state = STATE_PREPARED;
  968. exec_cmd = prepare_set_command(info, command, ext_cmd_type,
  969. column, page_addr);
  970. if (!exec_cmd) {
  971. info->need_wait = 0;
  972. info->dev_ready = 1;
  973. break;
  974. }
  975. info->cmd_complete = 0;
  976. pxa3xx_nand_start(info);
  977. ts = get_timer(0);
  978. while (1) {
  979. u32 status;
  980. status = nand_readl(info, NDSR);
  981. if (status)
  982. pxa3xx_nand_irq(info);
  983. if (info->cmd_complete)
  984. break;
  985. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  986. dev_err(&info->pdev->dev, "Wait timeout!!!\n");
  987. return;
  988. }
  989. }
  990. /* Only a few commands need several steps */
  991. if (command != NAND_CMD_PAGEPROG &&
  992. command != NAND_CMD_READ0 &&
  993. command != NAND_CMD_READOOB)
  994. break;
  995. info->cur_chunk++;
  996. /* Check if the sequence is complete */
  997. if (info->cur_chunk == info->ntotalchunks &&
  998. command != NAND_CMD_PAGEPROG)
  999. break;
  1000. /*
  1001. * After a splitted program command sequence has issued
  1002. * the command dispatch, the command sequence is complete.
  1003. */
  1004. if (info->cur_chunk == (info->ntotalchunks + 1) &&
  1005. command == NAND_CMD_PAGEPROG &&
  1006. ext_cmd_type == EXT_CMD_TYPE_DISPATCH)
  1007. break;
  1008. if (command == NAND_CMD_READ0 || command == NAND_CMD_READOOB) {
  1009. /* Last read: issue a 'last naked read' */
  1010. if (info->cur_chunk == info->ntotalchunks - 1)
  1011. ext_cmd_type = EXT_CMD_TYPE_LAST_RW;
  1012. else
  1013. ext_cmd_type = EXT_CMD_TYPE_NAKED_RW;
  1014. /*
  1015. * If a splitted program command has no more data to transfer,
  1016. * the command dispatch must be issued to complete.
  1017. */
  1018. } else if (command == NAND_CMD_PAGEPROG &&
  1019. info->cur_chunk == info->ntotalchunks) {
  1020. ext_cmd_type = EXT_CMD_TYPE_DISPATCH;
  1021. }
  1022. } while (1);
  1023. info->state = STATE_IDLE;
  1024. }
  1025. static int pxa3xx_nand_write_page_hwecc(struct mtd_info *mtd,
  1026. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  1027. int page)
  1028. {
  1029. chip->write_buf(mtd, buf, mtd->writesize);
  1030. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1031. return 0;
  1032. }
  1033. static int pxa3xx_nand_read_page_hwecc(struct mtd_info *mtd,
  1034. struct nand_chip *chip, uint8_t *buf, int oob_required,
  1035. int page)
  1036. {
  1037. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1038. struct pxa3xx_nand_info *info = host->info_data;
  1039. chip->read_buf(mtd, buf, mtd->writesize);
  1040. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1041. if (info->retcode == ERR_CORERR && info->use_ecc) {
  1042. mtd->ecc_stats.corrected += info->ecc_err_cnt;
  1043. } else if (info->retcode == ERR_UNCORERR) {
  1044. /*
  1045. * for blank page (all 0xff), HW will calculate its ECC as
  1046. * 0, which is different from the ECC information within
  1047. * OOB, ignore such uncorrectable errors
  1048. */
  1049. if (is_buf_blank(buf, mtd->writesize))
  1050. info->retcode = ERR_NONE;
  1051. else
  1052. mtd->ecc_stats.failed++;
  1053. }
  1054. return info->max_bitflips;
  1055. }
  1056. static uint8_t pxa3xx_nand_read_byte(struct mtd_info *mtd)
  1057. {
  1058. struct nand_chip *chip = mtd_to_nand(mtd);
  1059. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1060. struct pxa3xx_nand_info *info = host->info_data;
  1061. char retval = 0xFF;
  1062. if (info->buf_start < info->buf_count)
  1063. /* Has just send a new command? */
  1064. retval = info->data_buff[info->buf_start++];
  1065. return retval;
  1066. }
  1067. static u16 pxa3xx_nand_read_word(struct mtd_info *mtd)
  1068. {
  1069. struct nand_chip *chip = mtd_to_nand(mtd);
  1070. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1071. struct pxa3xx_nand_info *info = host->info_data;
  1072. u16 retval = 0xFFFF;
  1073. if (!(info->buf_start & 0x01) && info->buf_start < info->buf_count) {
  1074. retval = *((u16 *)(info->data_buff+info->buf_start));
  1075. info->buf_start += 2;
  1076. }
  1077. return retval;
  1078. }
  1079. static void pxa3xx_nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  1080. {
  1081. struct nand_chip *chip = mtd_to_nand(mtd);
  1082. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1083. struct pxa3xx_nand_info *info = host->info_data;
  1084. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1085. memcpy(buf, info->data_buff + info->buf_start, real_len);
  1086. info->buf_start += real_len;
  1087. }
  1088. static void pxa3xx_nand_write_buf(struct mtd_info *mtd,
  1089. const uint8_t *buf, int len)
  1090. {
  1091. struct nand_chip *chip = mtd_to_nand(mtd);
  1092. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1093. struct pxa3xx_nand_info *info = host->info_data;
  1094. int real_len = min_t(size_t, len, info->buf_count - info->buf_start);
  1095. memcpy(info->data_buff + info->buf_start, buf, real_len);
  1096. info->buf_start += real_len;
  1097. }
  1098. static void pxa3xx_nand_select_chip(struct mtd_info *mtd, int chip)
  1099. {
  1100. return;
  1101. }
  1102. static int pxa3xx_nand_waitfunc(struct mtd_info *mtd, struct nand_chip *this)
  1103. {
  1104. struct nand_chip *chip = mtd_to_nand(mtd);
  1105. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1106. struct pxa3xx_nand_info *info = host->info_data;
  1107. if (info->need_wait) {
  1108. u32 ts;
  1109. info->need_wait = 0;
  1110. ts = get_timer(0);
  1111. while (1) {
  1112. u32 status;
  1113. status = nand_readl(info, NDSR);
  1114. if (status)
  1115. pxa3xx_nand_irq(info);
  1116. if (info->dev_ready)
  1117. break;
  1118. if (get_timer(ts) > CHIP_DELAY_TIMEOUT) {
  1119. dev_err(&info->pdev->dev, "Ready timeout!!!\n");
  1120. return NAND_STATUS_FAIL;
  1121. }
  1122. }
  1123. }
  1124. /* pxa3xx_nand_send_command has waited for command complete */
  1125. if (this->state == FL_WRITING || this->state == FL_ERASING) {
  1126. if (info->retcode == ERR_NONE)
  1127. return 0;
  1128. else
  1129. return NAND_STATUS_FAIL;
  1130. }
  1131. return NAND_STATUS_READY;
  1132. }
  1133. static int pxa3xx_nand_config_ident(struct pxa3xx_nand_info *info)
  1134. {
  1135. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1136. /* Configure default flash values */
  1137. info->reg_ndcr = 0x0; /* enable all interrupts */
  1138. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1139. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1140. info->reg_ndcr |= NDCR_SPARE_EN;
  1141. return 0;
  1142. }
  1143. static void pxa3xx_nand_config_tail(struct pxa3xx_nand_info *info)
  1144. {
  1145. struct pxa3xx_nand_host *host = info->host[info->cs];
  1146. struct mtd_info *mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1147. struct nand_chip *chip = mtd_to_nand(mtd);
  1148. info->reg_ndcr |= (host->col_addr_cycles == 2) ? NDCR_RA_START : 0;
  1149. info->reg_ndcr |= (chip->page_shift == 6) ? NDCR_PG_PER_BLK : 0;
  1150. info->reg_ndcr |= (mtd->writesize == 2048) ? NDCR_PAGE_SZ : 0;
  1151. }
  1152. static void pxa3xx_nand_detect_config(struct pxa3xx_nand_info *info)
  1153. {
  1154. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1155. uint32_t ndcr = nand_readl(info, NDCR);
  1156. /* Set an initial chunk size */
  1157. info->chunk_size = ndcr & NDCR_PAGE_SZ ? 2048 : 512;
  1158. info->reg_ndcr = ndcr &
  1159. ~(NDCR_INT_MASK | NDCR_ND_ARB_EN | NFCV1_NDCR_ARB_CNTL);
  1160. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1161. info->ndtr0cs0 = nand_readl(info, NDTR0CS0);
  1162. info->ndtr1cs0 = nand_readl(info, NDTR1CS0);
  1163. }
  1164. static int pxa3xx_nand_init_buff(struct pxa3xx_nand_info *info)
  1165. {
  1166. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1167. if (info->data_buff == NULL)
  1168. return -ENOMEM;
  1169. return 0;
  1170. }
  1171. static int pxa3xx_nand_sensing(struct pxa3xx_nand_host *host)
  1172. {
  1173. struct pxa3xx_nand_info *info = host->info_data;
  1174. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1175. struct mtd_info *mtd;
  1176. struct nand_chip *chip;
  1177. const struct nand_sdr_timings *timings;
  1178. int ret;
  1179. mtd = nand_to_mtd(&info->host[info->cs]->chip);
  1180. chip = mtd_to_nand(mtd);
  1181. /* configure default flash values */
  1182. info->reg_ndcr = 0x0; /* enable all interrupts */
  1183. info->reg_ndcr |= (pdata->enable_arbiter) ? NDCR_ND_ARB_EN : 0;
  1184. info->reg_ndcr |= NDCR_RD_ID_CNT(READ_ID_BYTES);
  1185. info->reg_ndcr |= NDCR_SPARE_EN; /* enable spare by default */
  1186. /* use the common timing to make a try */
  1187. timings = onfi_async_timing_mode_to_sdr_timings(0);
  1188. if (IS_ERR(timings))
  1189. return PTR_ERR(timings);
  1190. pxa3xx_nand_set_sdr_timing(host, timings);
  1191. chip->cmdfunc(mtd, NAND_CMD_RESET, 0, 0);
  1192. ret = chip->waitfunc(mtd, chip);
  1193. if (ret & NAND_STATUS_FAIL)
  1194. return -ENODEV;
  1195. return 0;
  1196. }
  1197. static int pxa_ecc_init(struct pxa3xx_nand_info *info,
  1198. struct nand_ecc_ctrl *ecc,
  1199. int strength, int ecc_stepsize, int page_size)
  1200. {
  1201. if (strength == 1 && ecc_stepsize == 512 && page_size == 2048) {
  1202. info->nfullchunks = 1;
  1203. info->ntotalchunks = 1;
  1204. info->chunk_size = 2048;
  1205. info->spare_size = 40;
  1206. info->ecc_size = 24;
  1207. ecc->mode = NAND_ECC_HW;
  1208. ecc->size = 512;
  1209. ecc->strength = 1;
  1210. } else if (strength == 1 && ecc_stepsize == 512 && page_size == 512) {
  1211. info->nfullchunks = 1;
  1212. info->ntotalchunks = 1;
  1213. info->chunk_size = 512;
  1214. info->spare_size = 8;
  1215. info->ecc_size = 8;
  1216. ecc->mode = NAND_ECC_HW;
  1217. ecc->size = 512;
  1218. ecc->strength = 1;
  1219. /*
  1220. * Required ECC: 4-bit correction per 512 bytes
  1221. * Select: 16-bit correction per 2048 bytes
  1222. */
  1223. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 2048) {
  1224. info->ecc_bch = 1;
  1225. info->nfullchunks = 1;
  1226. info->ntotalchunks = 1;
  1227. info->chunk_size = 2048;
  1228. info->spare_size = 32;
  1229. info->ecc_size = 32;
  1230. ecc->mode = NAND_ECC_HW;
  1231. ecc->size = info->chunk_size;
  1232. ecc->layout = &ecc_layout_2KB_bch4bit;
  1233. ecc->strength = 16;
  1234. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 4096) {
  1235. info->ecc_bch = 1;
  1236. info->nfullchunks = 2;
  1237. info->ntotalchunks = 2;
  1238. info->chunk_size = 2048;
  1239. info->spare_size = 32;
  1240. info->ecc_size = 32;
  1241. ecc->mode = NAND_ECC_HW;
  1242. ecc->size = info->chunk_size;
  1243. ecc->layout = &ecc_layout_4KB_bch4bit;
  1244. ecc->strength = 16;
  1245. } else if (strength == 4 && ecc_stepsize == 512 && page_size == 8192) {
  1246. info->ecc_bch = 1;
  1247. info->nfullchunks = 4;
  1248. info->ntotalchunks = 4;
  1249. info->chunk_size = 2048;
  1250. info->spare_size = 32;
  1251. info->ecc_size = 32;
  1252. ecc->mode = NAND_ECC_HW;
  1253. ecc->size = info->chunk_size;
  1254. ecc->layout = &ecc_layout_8KB_bch4bit;
  1255. ecc->strength = 16;
  1256. /*
  1257. * Required ECC: 8-bit correction per 512 bytes
  1258. * Select: 16-bit correction per 1024 bytes
  1259. */
  1260. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 2048) {
  1261. info->ecc_bch = 1;
  1262. info->nfullchunks = 1;
  1263. info->ntotalchunks = 2;
  1264. info->chunk_size = 1024;
  1265. info->spare_size = 0;
  1266. info->last_chunk_size = 1024;
  1267. info->last_spare_size = 64;
  1268. info->ecc_size = 32;
  1269. ecc->mode = NAND_ECC_HW;
  1270. ecc->size = info->chunk_size;
  1271. ecc->layout = &ecc_layout_2KB_bch8bit;
  1272. ecc->strength = 16;
  1273. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 4096) {
  1274. info->ecc_bch = 1;
  1275. info->nfullchunks = 4;
  1276. info->ntotalchunks = 5;
  1277. info->chunk_size = 1024;
  1278. info->spare_size = 0;
  1279. info->last_chunk_size = 0;
  1280. info->last_spare_size = 64;
  1281. info->ecc_size = 32;
  1282. ecc->mode = NAND_ECC_HW;
  1283. ecc->size = info->chunk_size;
  1284. ecc->layout = &ecc_layout_4KB_bch8bit;
  1285. ecc->strength = 16;
  1286. } else if (strength == 8 && ecc_stepsize == 512 && page_size == 8192) {
  1287. info->ecc_bch = 1;
  1288. info->nfullchunks = 8;
  1289. info->ntotalchunks = 9;
  1290. info->chunk_size = 1024;
  1291. info->spare_size = 0;
  1292. info->last_chunk_size = 0;
  1293. info->last_spare_size = 160;
  1294. info->ecc_size = 32;
  1295. ecc->mode = NAND_ECC_HW;
  1296. ecc->size = info->chunk_size;
  1297. ecc->layout = &ecc_layout_8KB_bch8bit;
  1298. ecc->strength = 16;
  1299. } else {
  1300. dev_err(&info->pdev->dev,
  1301. "ECC strength %d at page size %d is not supported\n",
  1302. strength, page_size);
  1303. return -ENODEV;
  1304. }
  1305. return 0;
  1306. }
  1307. static int pxa3xx_nand_scan(struct mtd_info *mtd)
  1308. {
  1309. struct nand_chip *chip = mtd_to_nand(mtd);
  1310. struct pxa3xx_nand_host *host = nand_get_controller_data(chip);
  1311. struct pxa3xx_nand_info *info = host->info_data;
  1312. struct pxa3xx_nand_platform_data *pdata = info->pdata;
  1313. int ret;
  1314. uint16_t ecc_strength, ecc_step;
  1315. if (pdata->keep_config) {
  1316. pxa3xx_nand_detect_config(info);
  1317. } else {
  1318. ret = pxa3xx_nand_config_ident(info);
  1319. if (ret)
  1320. return ret;
  1321. ret = pxa3xx_nand_sensing(host);
  1322. if (ret) {
  1323. dev_info(&info->pdev->dev,
  1324. "There is no chip on cs %d!\n",
  1325. info->cs);
  1326. return ret;
  1327. }
  1328. }
  1329. /* Device detection must be done with ECC disabled */
  1330. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370)
  1331. nand_writel(info, NDECCCTRL, 0x0);
  1332. if (nand_scan_ident(mtd, 1, NULL))
  1333. return -ENODEV;
  1334. if (!pdata->keep_config) {
  1335. ret = pxa3xx_nand_init_timings(host);
  1336. if (ret) {
  1337. dev_err(&info->pdev->dev,
  1338. "Failed to set timings: %d\n", ret);
  1339. return ret;
  1340. }
  1341. }
  1342. #ifdef CONFIG_SYS_NAND_USE_FLASH_BBT
  1343. /*
  1344. * We'll use a bad block table stored in-flash and don't
  1345. * allow writing the bad block marker to the flash.
  1346. */
  1347. chip->bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_NO_OOB_BBM;
  1348. chip->bbt_td = &bbt_main_descr;
  1349. chip->bbt_md = &bbt_mirror_descr;
  1350. #endif
  1351. if (pdata->ecc_strength && pdata->ecc_step_size) {
  1352. ecc_strength = pdata->ecc_strength;
  1353. ecc_step = pdata->ecc_step_size;
  1354. } else {
  1355. ecc_strength = chip->ecc_strength_ds;
  1356. ecc_step = chip->ecc_step_ds;
  1357. }
  1358. /* Set default ECC strength requirements on non-ONFI devices */
  1359. if (ecc_strength < 1 && ecc_step < 1) {
  1360. ecc_strength = 1;
  1361. ecc_step = 512;
  1362. }
  1363. ret = pxa_ecc_init(info, &chip->ecc, ecc_strength,
  1364. ecc_step, mtd->writesize);
  1365. if (ret)
  1366. return ret;
  1367. /*
  1368. * If the page size is bigger than the FIFO size, let's check
  1369. * we are given the right variant and then switch to the extended
  1370. * (aka split) command handling,
  1371. */
  1372. if (mtd->writesize > info->chunk_size) {
  1373. if (info->variant == PXA3XX_NAND_VARIANT_ARMADA370) {
  1374. chip->cmdfunc = nand_cmdfunc_extended;
  1375. } else {
  1376. dev_err(&info->pdev->dev,
  1377. "unsupported page size on this variant\n");
  1378. return -ENODEV;
  1379. }
  1380. }
  1381. /* calculate addressing information */
  1382. if (mtd->writesize >= 2048)
  1383. host->col_addr_cycles = 2;
  1384. else
  1385. host->col_addr_cycles = 1;
  1386. /* release the initial buffer */
  1387. kfree(info->data_buff);
  1388. /* allocate the real data + oob buffer */
  1389. info->buf_size = mtd->writesize + mtd->oobsize;
  1390. ret = pxa3xx_nand_init_buff(info);
  1391. if (ret)
  1392. return ret;
  1393. info->oob_buff = info->data_buff + mtd->writesize;
  1394. if ((mtd->size >> chip->page_shift) > 65536)
  1395. host->row_addr_cycles = 3;
  1396. else
  1397. host->row_addr_cycles = 2;
  1398. if (!pdata->keep_config)
  1399. pxa3xx_nand_config_tail(info);
  1400. return nand_scan_tail(mtd);
  1401. }
  1402. static int alloc_nand_resource(struct pxa3xx_nand_info *info)
  1403. {
  1404. struct pxa3xx_nand_platform_data *pdata;
  1405. struct pxa3xx_nand_host *host;
  1406. struct nand_chip *chip = NULL;
  1407. struct mtd_info *mtd;
  1408. int ret, cs;
  1409. pdata = info->pdata;
  1410. if (pdata->num_cs <= 0)
  1411. return -ENODEV;
  1412. info->variant = pxa3xx_nand_get_variant();
  1413. for (cs = 0; cs < pdata->num_cs; cs++) {
  1414. chip = (struct nand_chip *)
  1415. ((u8 *)&info[1] + sizeof(*host) * cs);
  1416. mtd = nand_to_mtd(chip);
  1417. host = (struct pxa3xx_nand_host *)chip;
  1418. info->host[cs] = host;
  1419. host->cs = cs;
  1420. host->info_data = info;
  1421. mtd->owner = THIS_MODULE;
  1422. nand_set_controller_data(chip, host);
  1423. chip->ecc.read_page = pxa3xx_nand_read_page_hwecc;
  1424. chip->ecc.write_page = pxa3xx_nand_write_page_hwecc;
  1425. chip->controller = &info->controller;
  1426. chip->waitfunc = pxa3xx_nand_waitfunc;
  1427. chip->select_chip = pxa3xx_nand_select_chip;
  1428. chip->read_word = pxa3xx_nand_read_word;
  1429. chip->read_byte = pxa3xx_nand_read_byte;
  1430. chip->read_buf = pxa3xx_nand_read_buf;
  1431. chip->write_buf = pxa3xx_nand_write_buf;
  1432. chip->options |= NAND_NO_SUBPAGE_WRITE;
  1433. chip->cmdfunc = nand_cmdfunc;
  1434. }
  1435. /* Allocate a buffer to allow flash detection */
  1436. info->buf_size = INIT_BUFFER_SIZE;
  1437. info->data_buff = kmalloc(info->buf_size, GFP_KERNEL);
  1438. if (info->data_buff == NULL) {
  1439. ret = -ENOMEM;
  1440. goto fail_disable_clk;
  1441. }
  1442. /* initialize all interrupts to be disabled */
  1443. disable_int(info, NDSR_MASK);
  1444. return 0;
  1445. kfree(info->data_buff);
  1446. fail_disable_clk:
  1447. return ret;
  1448. }
  1449. static int pxa3xx_nand_probe_dt(struct pxa3xx_nand_info *info)
  1450. {
  1451. struct pxa3xx_nand_platform_data *pdata;
  1452. const void *blob = gd->fdt_blob;
  1453. int node = -1;
  1454. pdata = kzalloc(sizeof(*pdata), GFP_KERNEL);
  1455. if (!pdata)
  1456. return -ENOMEM;
  1457. /* Get address decoding nodes from the FDT blob */
  1458. do {
  1459. node = fdt_node_offset_by_compatible(blob, node,
  1460. "marvell,mvebu-pxa3xx-nand");
  1461. if (node < 0)
  1462. break;
  1463. /* Bypass disabeld nodes */
  1464. if (!fdtdec_get_is_enabled(blob, node))
  1465. continue;
  1466. /* Get the first enabled NAND controler base address */
  1467. info->mmio_base =
  1468. (void __iomem *)fdtdec_get_addr_size_auto_noparent(
  1469. blob, node, "reg", 0, NULL, true);
  1470. pdata->num_cs = fdtdec_get_int(blob, node, "num-cs", 1);
  1471. if (pdata->num_cs != 1) {
  1472. pr_err("pxa3xx driver supports single CS only\n");
  1473. break;
  1474. }
  1475. if (fdtdec_get_bool(blob, node, "nand-enable-arbiter"))
  1476. pdata->enable_arbiter = 1;
  1477. if (fdtdec_get_bool(blob, node, "nand-keep-config"))
  1478. pdata->keep_config = 1;
  1479. /*
  1480. * ECC parameters.
  1481. * If these are not set, they will be selected according
  1482. * to the detected flash type.
  1483. */
  1484. /* ECC strength */
  1485. pdata->ecc_strength = fdtdec_get_int(blob, node,
  1486. "nand-ecc-strength", 0);
  1487. /* ECC step size */
  1488. pdata->ecc_step_size = fdtdec_get_int(blob, node,
  1489. "nand-ecc-step-size", 0);
  1490. info->pdata = pdata;
  1491. /* Currently support only a single NAND controller */
  1492. return 0;
  1493. } while (node >= 0);
  1494. return -EINVAL;
  1495. }
  1496. static int pxa3xx_nand_probe(struct pxa3xx_nand_info *info)
  1497. {
  1498. struct pxa3xx_nand_platform_data *pdata;
  1499. int ret, cs, probe_success;
  1500. ret = pxa3xx_nand_probe_dt(info);
  1501. if (ret)
  1502. return ret;
  1503. pdata = info->pdata;
  1504. ret = alloc_nand_resource(info);
  1505. if (ret) {
  1506. dev_err(&pdev->dev, "alloc nand resource failed\n");
  1507. return ret;
  1508. }
  1509. probe_success = 0;
  1510. for (cs = 0; cs < pdata->num_cs; cs++) {
  1511. struct mtd_info *mtd = nand_to_mtd(&info->host[cs]->chip);
  1512. /*
  1513. * The mtd name matches the one used in 'mtdparts' kernel
  1514. * parameter. This name cannot be changed or otherwise
  1515. * user's mtd partitions configuration would get broken.
  1516. */
  1517. mtd->name = "pxa3xx_nand-0";
  1518. info->cs = cs;
  1519. ret = pxa3xx_nand_scan(mtd);
  1520. if (ret) {
  1521. dev_info(&pdev->dev, "failed to scan nand at cs %d\n",
  1522. cs);
  1523. continue;
  1524. }
  1525. if (nand_register(cs, mtd))
  1526. continue;
  1527. probe_success = 1;
  1528. }
  1529. if (!probe_success)
  1530. return -ENODEV;
  1531. return 0;
  1532. }
  1533. /*
  1534. * Main initialization routine
  1535. */
  1536. void board_nand_init(void)
  1537. {
  1538. struct pxa3xx_nand_info *info;
  1539. struct pxa3xx_nand_host *host;
  1540. int ret;
  1541. info = kzalloc(sizeof(*info) +
  1542. sizeof(*host) * CONFIG_SYS_MAX_NAND_DEVICE,
  1543. GFP_KERNEL);
  1544. if (!info)
  1545. return;
  1546. ret = pxa3xx_nand_probe(info);
  1547. if (ret)
  1548. return;
  1549. }