nand_base.c 121 KB

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  1. /*
  2. * Overview:
  3. * This is the generic MTD driver for NAND flash devices. It should be
  4. * capable of working with almost all NAND chips currently available.
  5. *
  6. * Additional technical information is available on
  7. * http://www.linux-mtd.infradead.org/doc/nand.html
  8. *
  9. * Copyright (C) 2000 Steven J. Hill (sjhill@realitydiluted.com)
  10. * 2002-2006 Thomas Gleixner (tglx@linutronix.de)
  11. *
  12. * Credits:
  13. * David Woodhouse for adding multichip support
  14. *
  15. * Aleph One Ltd. and Toby Churchill Ltd. for supporting the
  16. * rework for 2K page size chips
  17. *
  18. * TODO:
  19. * Enable cached programming for 2k page size chips
  20. * Check, if mtd->ecctype should be set to MTD_ECC_HW
  21. * if we have HW ECC support.
  22. * BBT table is not serialized, has to be fixed
  23. *
  24. * This program is free software; you can redistribute it and/or modify
  25. * it under the terms of the GNU General Public License version 2 as
  26. * published by the Free Software Foundation.
  27. *
  28. */
  29. #define pr_fmt(fmt) KBUILD_MODNAME ": " fmt
  30. #include <common.h>
  31. #if CONFIG_IS_ENABLED(OF_CONTROL)
  32. #include <fdtdec.h>
  33. #endif
  34. #include <malloc.h>
  35. #include <watchdog.h>
  36. #include <linux/err.h>
  37. #include <linux/compat.h>
  38. #include <linux/mtd/mtd.h>
  39. #include <linux/mtd/rawnand.h>
  40. #include <linux/mtd/nand_ecc.h>
  41. #include <linux/mtd/nand_bch.h>
  42. #ifdef CONFIG_MTD_PARTITIONS
  43. #include <linux/mtd/partitions.h>
  44. #endif
  45. #include <asm/io.h>
  46. #include <linux/errno.h>
  47. /* Define default oob placement schemes for large and small page devices */
  48. static struct nand_ecclayout nand_oob_8 = {
  49. .eccbytes = 3,
  50. .eccpos = {0, 1, 2},
  51. .oobfree = {
  52. {.offset = 3,
  53. .length = 2},
  54. {.offset = 6,
  55. .length = 2} }
  56. };
  57. static struct nand_ecclayout nand_oob_16 = {
  58. .eccbytes = 6,
  59. .eccpos = {0, 1, 2, 3, 6, 7},
  60. .oobfree = {
  61. {.offset = 8,
  62. . length = 8} }
  63. };
  64. static struct nand_ecclayout nand_oob_64 = {
  65. .eccbytes = 24,
  66. .eccpos = {
  67. 40, 41, 42, 43, 44, 45, 46, 47,
  68. 48, 49, 50, 51, 52, 53, 54, 55,
  69. 56, 57, 58, 59, 60, 61, 62, 63},
  70. .oobfree = {
  71. {.offset = 2,
  72. .length = 38} }
  73. };
  74. static struct nand_ecclayout nand_oob_128 = {
  75. .eccbytes = 48,
  76. .eccpos = {
  77. 80, 81, 82, 83, 84, 85, 86, 87,
  78. 88, 89, 90, 91, 92, 93, 94, 95,
  79. 96, 97, 98, 99, 100, 101, 102, 103,
  80. 104, 105, 106, 107, 108, 109, 110, 111,
  81. 112, 113, 114, 115, 116, 117, 118, 119,
  82. 120, 121, 122, 123, 124, 125, 126, 127},
  83. .oobfree = {
  84. {.offset = 2,
  85. .length = 78} }
  86. };
  87. static int nand_get_device(struct mtd_info *mtd, int new_state);
  88. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  89. struct mtd_oob_ops *ops);
  90. /*
  91. * For devices which display every fart in the system on a separate LED. Is
  92. * compiled away when LED support is disabled.
  93. */
  94. DEFINE_LED_TRIGGER(nand_led_trigger);
  95. static int check_offs_len(struct mtd_info *mtd,
  96. loff_t ofs, uint64_t len)
  97. {
  98. struct nand_chip *chip = mtd_to_nand(mtd);
  99. int ret = 0;
  100. /* Start address must align on block boundary */
  101. if (ofs & ((1ULL << chip->phys_erase_shift) - 1)) {
  102. pr_debug("%s: unaligned address\n", __func__);
  103. ret = -EINVAL;
  104. }
  105. /* Length must align on block boundary */
  106. if (len & ((1ULL << chip->phys_erase_shift) - 1)) {
  107. pr_debug("%s: length not block aligned\n", __func__);
  108. ret = -EINVAL;
  109. }
  110. return ret;
  111. }
  112. /**
  113. * nand_release_device - [GENERIC] release chip
  114. * @mtd: MTD device structure
  115. *
  116. * Release chip lock and wake up anyone waiting on the device.
  117. */
  118. static void nand_release_device(struct mtd_info *mtd)
  119. {
  120. struct nand_chip *chip = mtd_to_nand(mtd);
  121. /* De-select the NAND device */
  122. chip->select_chip(mtd, -1);
  123. }
  124. /**
  125. * nand_read_byte - [DEFAULT] read one byte from the chip
  126. * @mtd: MTD device structure
  127. *
  128. * Default read function for 8bit buswidth
  129. */
  130. uint8_t nand_read_byte(struct mtd_info *mtd)
  131. {
  132. struct nand_chip *chip = mtd_to_nand(mtd);
  133. return readb(chip->IO_ADDR_R);
  134. }
  135. /**
  136. * nand_read_byte16 - [DEFAULT] read one byte endianness aware from the chip
  137. * @mtd: MTD device structure
  138. *
  139. * Default read function for 16bit buswidth with endianness conversion.
  140. *
  141. */
  142. static uint8_t nand_read_byte16(struct mtd_info *mtd)
  143. {
  144. struct nand_chip *chip = mtd_to_nand(mtd);
  145. return (uint8_t) cpu_to_le16(readw(chip->IO_ADDR_R));
  146. }
  147. /**
  148. * nand_read_word - [DEFAULT] read one word from the chip
  149. * @mtd: MTD device structure
  150. *
  151. * Default read function for 16bit buswidth without endianness conversion.
  152. */
  153. static u16 nand_read_word(struct mtd_info *mtd)
  154. {
  155. struct nand_chip *chip = mtd_to_nand(mtd);
  156. return readw(chip->IO_ADDR_R);
  157. }
  158. /**
  159. * nand_select_chip - [DEFAULT] control CE line
  160. * @mtd: MTD device structure
  161. * @chipnr: chipnumber to select, -1 for deselect
  162. *
  163. * Default select function for 1 chip devices.
  164. */
  165. static void nand_select_chip(struct mtd_info *mtd, int chipnr)
  166. {
  167. struct nand_chip *chip = mtd_to_nand(mtd);
  168. switch (chipnr) {
  169. case -1:
  170. chip->cmd_ctrl(mtd, NAND_CMD_NONE, 0 | NAND_CTRL_CHANGE);
  171. break;
  172. case 0:
  173. break;
  174. default:
  175. BUG();
  176. }
  177. }
  178. /**
  179. * nand_write_byte - [DEFAULT] write single byte to chip
  180. * @mtd: MTD device structure
  181. * @byte: value to write
  182. *
  183. * Default function to write a byte to I/O[7:0]
  184. */
  185. static void nand_write_byte(struct mtd_info *mtd, uint8_t byte)
  186. {
  187. struct nand_chip *chip = mtd_to_nand(mtd);
  188. chip->write_buf(mtd, &byte, 1);
  189. }
  190. /**
  191. * nand_write_byte16 - [DEFAULT] write single byte to a chip with width 16
  192. * @mtd: MTD device structure
  193. * @byte: value to write
  194. *
  195. * Default function to write a byte to I/O[7:0] on a 16-bit wide chip.
  196. */
  197. static void nand_write_byte16(struct mtd_info *mtd, uint8_t byte)
  198. {
  199. struct nand_chip *chip = mtd_to_nand(mtd);
  200. uint16_t word = byte;
  201. /*
  202. * It's not entirely clear what should happen to I/O[15:8] when writing
  203. * a byte. The ONFi spec (Revision 3.1; 2012-09-19, Section 2.16) reads:
  204. *
  205. * When the host supports a 16-bit bus width, only data is
  206. * transferred at the 16-bit width. All address and command line
  207. * transfers shall use only the lower 8-bits of the data bus. During
  208. * command transfers, the host may place any value on the upper
  209. * 8-bits of the data bus. During address transfers, the host shall
  210. * set the upper 8-bits of the data bus to 00h.
  211. *
  212. * One user of the write_byte callback is nand_onfi_set_features. The
  213. * four parameters are specified to be written to I/O[7:0], but this is
  214. * neither an address nor a command transfer. Let's assume a 0 on the
  215. * upper I/O lines is OK.
  216. */
  217. chip->write_buf(mtd, (uint8_t *)&word, 2);
  218. }
  219. static void iowrite8_rep(void *addr, const uint8_t *buf, int len)
  220. {
  221. int i;
  222. for (i = 0; i < len; i++)
  223. writeb(buf[i], addr);
  224. }
  225. static void ioread8_rep(void *addr, uint8_t *buf, int len)
  226. {
  227. int i;
  228. for (i = 0; i < len; i++)
  229. buf[i] = readb(addr);
  230. }
  231. static void ioread16_rep(void *addr, void *buf, int len)
  232. {
  233. int i;
  234. u16 *p = (u16 *) buf;
  235. for (i = 0; i < len; i++)
  236. p[i] = readw(addr);
  237. }
  238. static void iowrite16_rep(void *addr, void *buf, int len)
  239. {
  240. int i;
  241. u16 *p = (u16 *) buf;
  242. for (i = 0; i < len; i++)
  243. writew(p[i], addr);
  244. }
  245. /**
  246. * nand_write_buf - [DEFAULT] write buffer to chip
  247. * @mtd: MTD device structure
  248. * @buf: data buffer
  249. * @len: number of bytes to write
  250. *
  251. * Default write function for 8bit buswidth.
  252. */
  253. void nand_write_buf(struct mtd_info *mtd, const uint8_t *buf, int len)
  254. {
  255. struct nand_chip *chip = mtd_to_nand(mtd);
  256. iowrite8_rep(chip->IO_ADDR_W, buf, len);
  257. }
  258. /**
  259. * nand_read_buf - [DEFAULT] read chip data into buffer
  260. * @mtd: MTD device structure
  261. * @buf: buffer to store date
  262. * @len: number of bytes to read
  263. *
  264. * Default read function for 8bit buswidth.
  265. */
  266. void nand_read_buf(struct mtd_info *mtd, uint8_t *buf, int len)
  267. {
  268. struct nand_chip *chip = mtd_to_nand(mtd);
  269. ioread8_rep(chip->IO_ADDR_R, buf, len);
  270. }
  271. /**
  272. * nand_write_buf16 - [DEFAULT] write buffer to chip
  273. * @mtd: MTD device structure
  274. * @buf: data buffer
  275. * @len: number of bytes to write
  276. *
  277. * Default write function for 16bit buswidth.
  278. */
  279. void nand_write_buf16(struct mtd_info *mtd, const uint8_t *buf, int len)
  280. {
  281. struct nand_chip *chip = mtd_to_nand(mtd);
  282. u16 *p = (u16 *) buf;
  283. iowrite16_rep(chip->IO_ADDR_W, p, len >> 1);
  284. }
  285. /**
  286. * nand_read_buf16 - [DEFAULT] read chip data into buffer
  287. * @mtd: MTD device structure
  288. * @buf: buffer to store date
  289. * @len: number of bytes to read
  290. *
  291. * Default read function for 16bit buswidth.
  292. */
  293. void nand_read_buf16(struct mtd_info *mtd, uint8_t *buf, int len)
  294. {
  295. struct nand_chip *chip = mtd_to_nand(mtd);
  296. u16 *p = (u16 *) buf;
  297. ioread16_rep(chip->IO_ADDR_R, p, len >> 1);
  298. }
  299. /**
  300. * nand_block_bad - [DEFAULT] Read bad block marker from the chip
  301. * @mtd: MTD device structure
  302. * @ofs: offset from device start
  303. *
  304. * Check, if the block is bad.
  305. */
  306. static int nand_block_bad(struct mtd_info *mtd, loff_t ofs)
  307. {
  308. int page, res = 0, i = 0;
  309. struct nand_chip *chip = mtd_to_nand(mtd);
  310. u16 bad;
  311. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  312. ofs += mtd->erasesize - mtd->writesize;
  313. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  314. do {
  315. if (chip->options & NAND_BUSWIDTH_16) {
  316. chip->cmdfunc(mtd, NAND_CMD_READOOB,
  317. chip->badblockpos & 0xFE, page);
  318. bad = cpu_to_le16(chip->read_word(mtd));
  319. if (chip->badblockpos & 0x1)
  320. bad >>= 8;
  321. else
  322. bad &= 0xFF;
  323. } else {
  324. chip->cmdfunc(mtd, NAND_CMD_READOOB, chip->badblockpos,
  325. page);
  326. bad = chip->read_byte(mtd);
  327. }
  328. if (likely(chip->badblockbits == 8))
  329. res = bad != 0xFF;
  330. else
  331. res = hweight8(bad) < chip->badblockbits;
  332. ofs += mtd->writesize;
  333. page = (int)(ofs >> chip->page_shift) & chip->pagemask;
  334. i++;
  335. } while (!res && i < 2 && (chip->bbt_options & NAND_BBT_SCAN2NDPAGE));
  336. return res;
  337. }
  338. /**
  339. * nand_default_block_markbad - [DEFAULT] mark a block bad via bad block marker
  340. * @mtd: MTD device structure
  341. * @ofs: offset from device start
  342. *
  343. * This is the default implementation, which can be overridden by a hardware
  344. * specific driver. It provides the details for writing a bad block marker to a
  345. * block.
  346. */
  347. static int nand_default_block_markbad(struct mtd_info *mtd, loff_t ofs)
  348. {
  349. struct nand_chip *chip = mtd_to_nand(mtd);
  350. struct mtd_oob_ops ops;
  351. uint8_t buf[2] = { 0, 0 };
  352. int ret = 0, res, i = 0;
  353. memset(&ops, 0, sizeof(ops));
  354. ops.oobbuf = buf;
  355. ops.ooboffs = chip->badblockpos;
  356. if (chip->options & NAND_BUSWIDTH_16) {
  357. ops.ooboffs &= ~0x01;
  358. ops.len = ops.ooblen = 2;
  359. } else {
  360. ops.len = ops.ooblen = 1;
  361. }
  362. ops.mode = MTD_OPS_PLACE_OOB;
  363. /* Write to first/last page(s) if necessary */
  364. if (chip->bbt_options & NAND_BBT_SCANLASTPAGE)
  365. ofs += mtd->erasesize - mtd->writesize;
  366. do {
  367. res = nand_do_write_oob(mtd, ofs, &ops);
  368. if (!ret)
  369. ret = res;
  370. i++;
  371. ofs += mtd->writesize;
  372. } while ((chip->bbt_options & NAND_BBT_SCAN2NDPAGE) && i < 2);
  373. return ret;
  374. }
  375. /**
  376. * nand_block_markbad_lowlevel - mark a block bad
  377. * @mtd: MTD device structure
  378. * @ofs: offset from device start
  379. *
  380. * This function performs the generic NAND bad block marking steps (i.e., bad
  381. * block table(s) and/or marker(s)). We only allow the hardware driver to
  382. * specify how to write bad block markers to OOB (chip->block_markbad).
  383. *
  384. * We try operations in the following order:
  385. * (1) erase the affected block, to allow OOB marker to be written cleanly
  386. * (2) write bad block marker to OOB area of affected block (unless flag
  387. * NAND_BBT_NO_OOB_BBM is present)
  388. * (3) update the BBT
  389. * Note that we retain the first error encountered in (2) or (3), finish the
  390. * procedures, and dump the error in the end.
  391. */
  392. static int nand_block_markbad_lowlevel(struct mtd_info *mtd, loff_t ofs)
  393. {
  394. struct nand_chip *chip = mtd_to_nand(mtd);
  395. int res, ret = 0;
  396. if (!(chip->bbt_options & NAND_BBT_NO_OOB_BBM)) {
  397. struct erase_info einfo;
  398. /* Attempt erase before marking OOB */
  399. memset(&einfo, 0, sizeof(einfo));
  400. einfo.mtd = mtd;
  401. einfo.addr = ofs;
  402. einfo.len = 1ULL << chip->phys_erase_shift;
  403. nand_erase_nand(mtd, &einfo, 0);
  404. /* Write bad block marker to OOB */
  405. nand_get_device(mtd, FL_WRITING);
  406. ret = chip->block_markbad(mtd, ofs);
  407. nand_release_device(mtd);
  408. }
  409. /* Mark block bad in BBT */
  410. if (chip->bbt) {
  411. res = nand_markbad_bbt(mtd, ofs);
  412. if (!ret)
  413. ret = res;
  414. }
  415. if (!ret)
  416. mtd->ecc_stats.badblocks++;
  417. return ret;
  418. }
  419. /**
  420. * nand_check_wp - [GENERIC] check if the chip is write protected
  421. * @mtd: MTD device structure
  422. *
  423. * Check, if the device is write protected. The function expects, that the
  424. * device is already selected.
  425. */
  426. static int nand_check_wp(struct mtd_info *mtd)
  427. {
  428. struct nand_chip *chip = mtd_to_nand(mtd);
  429. /* Broken xD cards report WP despite being writable */
  430. if (chip->options & NAND_BROKEN_XD)
  431. return 0;
  432. /* Check the WP bit */
  433. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  434. return (chip->read_byte(mtd) & NAND_STATUS_WP) ? 0 : 1;
  435. }
  436. /**
  437. * nand_block_isreserved - [GENERIC] Check if a block is marked reserved.
  438. * @mtd: MTD device structure
  439. * @ofs: offset from device start
  440. *
  441. * Check if the block is marked as reserved.
  442. */
  443. static int nand_block_isreserved(struct mtd_info *mtd, loff_t ofs)
  444. {
  445. struct nand_chip *chip = mtd_to_nand(mtd);
  446. if (!chip->bbt)
  447. return 0;
  448. /* Return info from the table */
  449. return nand_isreserved_bbt(mtd, ofs);
  450. }
  451. /**
  452. * nand_block_checkbad - [GENERIC] Check if a block is marked bad
  453. * @mtd: MTD device structure
  454. * @ofs: offset from device start
  455. * @allowbbt: 1, if its allowed to access the bbt area
  456. *
  457. * Check, if the block is bad. Either by reading the bad block table or
  458. * calling of the scan function.
  459. */
  460. static int nand_block_checkbad(struct mtd_info *mtd, loff_t ofs, int allowbbt)
  461. {
  462. struct nand_chip *chip = mtd_to_nand(mtd);
  463. if (!(chip->options & NAND_SKIP_BBTSCAN) &&
  464. !(chip->options & NAND_BBT_SCANNED)) {
  465. chip->options |= NAND_BBT_SCANNED;
  466. chip->scan_bbt(mtd);
  467. }
  468. if (!chip->bbt)
  469. return chip->block_bad(mtd, ofs);
  470. /* Return info from the table */
  471. return nand_isbad_bbt(mtd, ofs, allowbbt);
  472. }
  473. /**
  474. * nand_wait_ready - [GENERIC] Wait for the ready pin after commands.
  475. * @mtd: MTD device structure
  476. *
  477. * Wait for the ready pin after a command, and warn if a timeout occurs.
  478. */
  479. void nand_wait_ready(struct mtd_info *mtd)
  480. {
  481. struct nand_chip *chip = mtd_to_nand(mtd);
  482. u32 timeo = (CONFIG_SYS_HZ * 400) / 1000;
  483. u32 time_start;
  484. time_start = get_timer(0);
  485. /* Wait until command is processed or timeout occurs */
  486. while (get_timer(time_start) < timeo) {
  487. if (chip->dev_ready)
  488. if (chip->dev_ready(mtd))
  489. break;
  490. }
  491. if (!chip->dev_ready(mtd))
  492. pr_warn("timeout while waiting for chip to become ready\n");
  493. }
  494. EXPORT_SYMBOL_GPL(nand_wait_ready);
  495. /**
  496. * nand_wait_status_ready - [GENERIC] Wait for the ready status after commands.
  497. * @mtd: MTD device structure
  498. * @timeo: Timeout in ms
  499. *
  500. * Wait for status ready (i.e. command done) or timeout.
  501. */
  502. static void nand_wait_status_ready(struct mtd_info *mtd, unsigned long timeo)
  503. {
  504. register struct nand_chip *chip = mtd_to_nand(mtd);
  505. u32 time_start;
  506. timeo = (CONFIG_SYS_HZ * timeo) / 1000;
  507. time_start = get_timer(0);
  508. while (get_timer(time_start) < timeo) {
  509. if ((chip->read_byte(mtd) & NAND_STATUS_READY))
  510. break;
  511. WATCHDOG_RESET();
  512. }
  513. };
  514. /**
  515. * nand_command - [DEFAULT] Send command to NAND device
  516. * @mtd: MTD device structure
  517. * @command: the command to be sent
  518. * @column: the column address for this command, -1 if none
  519. * @page_addr: the page address for this command, -1 if none
  520. *
  521. * Send command to NAND device. This function is used for small page devices
  522. * (512 Bytes per page).
  523. */
  524. static void nand_command(struct mtd_info *mtd, unsigned int command,
  525. int column, int page_addr)
  526. {
  527. register struct nand_chip *chip = mtd_to_nand(mtd);
  528. int ctrl = NAND_CTRL_CLE | NAND_CTRL_CHANGE;
  529. /* Write out the command to the device */
  530. if (command == NAND_CMD_SEQIN) {
  531. int readcmd;
  532. if (column >= mtd->writesize) {
  533. /* OOB area */
  534. column -= mtd->writesize;
  535. readcmd = NAND_CMD_READOOB;
  536. } else if (column < 256) {
  537. /* First 256 bytes --> READ0 */
  538. readcmd = NAND_CMD_READ0;
  539. } else {
  540. column -= 256;
  541. readcmd = NAND_CMD_READ1;
  542. }
  543. chip->cmd_ctrl(mtd, readcmd, ctrl);
  544. ctrl &= ~NAND_CTRL_CHANGE;
  545. }
  546. chip->cmd_ctrl(mtd, command, ctrl);
  547. /* Address cycle, when necessary */
  548. ctrl = NAND_CTRL_ALE | NAND_CTRL_CHANGE;
  549. /* Serially input address */
  550. if (column != -1) {
  551. /* Adjust columns for 16 bit buswidth */
  552. if (chip->options & NAND_BUSWIDTH_16 &&
  553. !nand_opcode_8bits(command))
  554. column >>= 1;
  555. chip->cmd_ctrl(mtd, column, ctrl);
  556. ctrl &= ~NAND_CTRL_CHANGE;
  557. }
  558. if (page_addr != -1) {
  559. chip->cmd_ctrl(mtd, page_addr, ctrl);
  560. ctrl &= ~NAND_CTRL_CHANGE;
  561. chip->cmd_ctrl(mtd, page_addr >> 8, ctrl);
  562. if (chip->options & NAND_ROW_ADDR_3)
  563. chip->cmd_ctrl(mtd, page_addr >> 16, ctrl);
  564. }
  565. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  566. /*
  567. * Program and erase have their own busy handlers status and sequential
  568. * in needs no delay
  569. */
  570. switch (command) {
  571. case NAND_CMD_PAGEPROG:
  572. case NAND_CMD_ERASE1:
  573. case NAND_CMD_ERASE2:
  574. case NAND_CMD_SEQIN:
  575. case NAND_CMD_STATUS:
  576. case NAND_CMD_READID:
  577. case NAND_CMD_SET_FEATURES:
  578. return;
  579. case NAND_CMD_RESET:
  580. if (chip->dev_ready)
  581. break;
  582. udelay(chip->chip_delay);
  583. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  584. NAND_CTRL_CLE | NAND_CTRL_CHANGE);
  585. chip->cmd_ctrl(mtd,
  586. NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  587. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  588. nand_wait_status_ready(mtd, 250);
  589. return;
  590. /* This applies to read commands */
  591. default:
  592. /*
  593. * If we don't have access to the busy pin, we apply the given
  594. * command delay
  595. */
  596. if (!chip->dev_ready) {
  597. udelay(chip->chip_delay);
  598. return;
  599. }
  600. }
  601. /*
  602. * Apply this short delay always to ensure that we do wait tWB in
  603. * any case on any machine.
  604. */
  605. ndelay(100);
  606. nand_wait_ready(mtd);
  607. }
  608. /**
  609. * nand_command_lp - [DEFAULT] Send command to NAND large page device
  610. * @mtd: MTD device structure
  611. * @command: the command to be sent
  612. * @column: the column address for this command, -1 if none
  613. * @page_addr: the page address for this command, -1 if none
  614. *
  615. * Send command to NAND device. This is the version for the new large page
  616. * devices. We don't have the separate regions as we have in the small page
  617. * devices. We must emulate NAND_CMD_READOOB to keep the code compatible.
  618. */
  619. static void nand_command_lp(struct mtd_info *mtd, unsigned int command,
  620. int column, int page_addr)
  621. {
  622. register struct nand_chip *chip = mtd_to_nand(mtd);
  623. /* Emulate NAND_CMD_READOOB */
  624. if (command == NAND_CMD_READOOB) {
  625. column += mtd->writesize;
  626. command = NAND_CMD_READ0;
  627. }
  628. /* Command latch cycle */
  629. chip->cmd_ctrl(mtd, command, NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  630. if (column != -1 || page_addr != -1) {
  631. int ctrl = NAND_CTRL_CHANGE | NAND_NCE | NAND_ALE;
  632. /* Serially input address */
  633. if (column != -1) {
  634. /* Adjust columns for 16 bit buswidth */
  635. if (chip->options & NAND_BUSWIDTH_16 &&
  636. !nand_opcode_8bits(command))
  637. column >>= 1;
  638. chip->cmd_ctrl(mtd, column, ctrl);
  639. ctrl &= ~NAND_CTRL_CHANGE;
  640. chip->cmd_ctrl(mtd, column >> 8, ctrl);
  641. }
  642. if (page_addr != -1) {
  643. chip->cmd_ctrl(mtd, page_addr, ctrl);
  644. chip->cmd_ctrl(mtd, page_addr >> 8,
  645. NAND_NCE | NAND_ALE);
  646. if (chip->options & NAND_ROW_ADDR_3)
  647. chip->cmd_ctrl(mtd, page_addr >> 16,
  648. NAND_NCE | NAND_ALE);
  649. }
  650. }
  651. chip->cmd_ctrl(mtd, NAND_CMD_NONE, NAND_NCE | NAND_CTRL_CHANGE);
  652. /*
  653. * Program and erase have their own busy handlers status, sequential
  654. * in and status need no delay.
  655. */
  656. switch (command) {
  657. case NAND_CMD_CACHEDPROG:
  658. case NAND_CMD_PAGEPROG:
  659. case NAND_CMD_ERASE1:
  660. case NAND_CMD_ERASE2:
  661. case NAND_CMD_SEQIN:
  662. case NAND_CMD_RNDIN:
  663. case NAND_CMD_STATUS:
  664. case NAND_CMD_READID:
  665. case NAND_CMD_SET_FEATURES:
  666. return;
  667. case NAND_CMD_RESET:
  668. if (chip->dev_ready)
  669. break;
  670. udelay(chip->chip_delay);
  671. chip->cmd_ctrl(mtd, NAND_CMD_STATUS,
  672. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  673. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  674. NAND_NCE | NAND_CTRL_CHANGE);
  675. /* EZ-NAND can take upto 250ms as per ONFi v4.0 */
  676. nand_wait_status_ready(mtd, 250);
  677. return;
  678. case NAND_CMD_RNDOUT:
  679. /* No ready / busy check necessary */
  680. chip->cmd_ctrl(mtd, NAND_CMD_RNDOUTSTART,
  681. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  682. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  683. NAND_NCE | NAND_CTRL_CHANGE);
  684. return;
  685. case NAND_CMD_READ0:
  686. chip->cmd_ctrl(mtd, NAND_CMD_READSTART,
  687. NAND_NCE | NAND_CLE | NAND_CTRL_CHANGE);
  688. chip->cmd_ctrl(mtd, NAND_CMD_NONE,
  689. NAND_NCE | NAND_CTRL_CHANGE);
  690. /* This applies to read commands */
  691. default:
  692. /*
  693. * If we don't have access to the busy pin, we apply the given
  694. * command delay.
  695. */
  696. if (!chip->dev_ready) {
  697. udelay(chip->chip_delay);
  698. return;
  699. }
  700. }
  701. /*
  702. * Apply this short delay always to ensure that we do wait tWB in
  703. * any case on any machine.
  704. */
  705. ndelay(100);
  706. nand_wait_ready(mtd);
  707. }
  708. /**
  709. * panic_nand_get_device - [GENERIC] Get chip for selected access
  710. * @chip: the nand chip descriptor
  711. * @mtd: MTD device structure
  712. * @new_state: the state which is requested
  713. *
  714. * Used when in panic, no locks are taken.
  715. */
  716. static void panic_nand_get_device(struct nand_chip *chip,
  717. struct mtd_info *mtd, int new_state)
  718. {
  719. /* Hardware controller shared among independent devices */
  720. chip->controller->active = chip;
  721. chip->state = new_state;
  722. }
  723. /**
  724. * nand_get_device - [GENERIC] Get chip for selected access
  725. * @mtd: MTD device structure
  726. * @new_state: the state which is requested
  727. *
  728. * Get the device and lock it for exclusive access
  729. */
  730. static int
  731. nand_get_device(struct mtd_info *mtd, int new_state)
  732. {
  733. struct nand_chip *chip = mtd_to_nand(mtd);
  734. chip->state = new_state;
  735. return 0;
  736. }
  737. /**
  738. * panic_nand_wait - [GENERIC] wait until the command is done
  739. * @mtd: MTD device structure
  740. * @chip: NAND chip structure
  741. * @timeo: timeout
  742. *
  743. * Wait for command done. This is a helper function for nand_wait used when
  744. * we are in interrupt context. May happen when in panic and trying to write
  745. * an oops through mtdoops.
  746. */
  747. static void panic_nand_wait(struct mtd_info *mtd, struct nand_chip *chip,
  748. unsigned long timeo)
  749. {
  750. int i;
  751. for (i = 0; i < timeo; i++) {
  752. if (chip->dev_ready) {
  753. if (chip->dev_ready(mtd))
  754. break;
  755. } else {
  756. if (chip->read_byte(mtd) & NAND_STATUS_READY)
  757. break;
  758. }
  759. mdelay(1);
  760. }
  761. }
  762. /**
  763. * nand_wait - [DEFAULT] wait until the command is done
  764. * @mtd: MTD device structure
  765. * @chip: NAND chip structure
  766. *
  767. * Wait for command done. This applies to erase and program only.
  768. */
  769. static int nand_wait(struct mtd_info *mtd, struct nand_chip *chip)
  770. {
  771. int status;
  772. unsigned long timeo = 400;
  773. led_trigger_event(nand_led_trigger, LED_FULL);
  774. /*
  775. * Apply this short delay always to ensure that we do wait tWB in any
  776. * case on any machine.
  777. */
  778. ndelay(100);
  779. chip->cmdfunc(mtd, NAND_CMD_STATUS, -1, -1);
  780. u32 timer = (CONFIG_SYS_HZ * timeo) / 1000;
  781. u32 time_start;
  782. time_start = get_timer(0);
  783. while (get_timer(time_start) < timer) {
  784. if (chip->dev_ready) {
  785. if (chip->dev_ready(mtd))
  786. break;
  787. } else {
  788. if (chip->read_byte(mtd) & NAND_STATUS_READY)
  789. break;
  790. }
  791. }
  792. led_trigger_event(nand_led_trigger, LED_OFF);
  793. status = (int)chip->read_byte(mtd);
  794. /* This can happen if in case of timeout or buggy dev_ready */
  795. WARN_ON(!(status & NAND_STATUS_READY));
  796. return status;
  797. }
  798. /**
  799. * nand_reset_data_interface - Reset data interface and timings
  800. * @chip: The NAND chip
  801. * @chipnr: Internal die id
  802. *
  803. * Reset the Data interface and timings to ONFI mode 0.
  804. *
  805. * Returns 0 for success or negative error code otherwise.
  806. */
  807. static int nand_reset_data_interface(struct nand_chip *chip, int chipnr)
  808. {
  809. struct mtd_info *mtd = nand_to_mtd(chip);
  810. const struct nand_data_interface *conf;
  811. int ret;
  812. if (!chip->setup_data_interface)
  813. return 0;
  814. /*
  815. * The ONFI specification says:
  816. * "
  817. * To transition from NV-DDR or NV-DDR2 to the SDR data
  818. * interface, the host shall use the Reset (FFh) command
  819. * using SDR timing mode 0. A device in any timing mode is
  820. * required to recognize Reset (FFh) command issued in SDR
  821. * timing mode 0.
  822. * "
  823. *
  824. * Configure the data interface in SDR mode and set the
  825. * timings to timing mode 0.
  826. */
  827. conf = nand_get_default_data_interface();
  828. ret = chip->setup_data_interface(mtd, chipnr, conf);
  829. if (ret)
  830. pr_err("Failed to configure data interface to SDR timing mode 0\n");
  831. return ret;
  832. }
  833. /**
  834. * nand_setup_data_interface - Setup the best data interface and timings
  835. * @chip: The NAND chip
  836. * @chipnr: Internal die id
  837. *
  838. * Find and configure the best data interface and NAND timings supported by
  839. * the chip and the driver.
  840. * First tries to retrieve supported timing modes from ONFI information,
  841. * and if the NAND chip does not support ONFI, relies on the
  842. * ->onfi_timing_mode_default specified in the nand_ids table.
  843. *
  844. * Returns 0 for success or negative error code otherwise.
  845. */
  846. static int nand_setup_data_interface(struct nand_chip *chip, int chipnr)
  847. {
  848. struct mtd_info *mtd = nand_to_mtd(chip);
  849. int ret;
  850. if (!chip->setup_data_interface || !chip->data_interface)
  851. return 0;
  852. /*
  853. * Ensure the timing mode has been changed on the chip side
  854. * before changing timings on the controller side.
  855. */
  856. if (chip->onfi_version) {
  857. u8 tmode_param[ONFI_SUBFEATURE_PARAM_LEN] = {
  858. chip->onfi_timing_mode_default,
  859. };
  860. ret = chip->onfi_set_features(mtd, chip,
  861. ONFI_FEATURE_ADDR_TIMING_MODE,
  862. tmode_param);
  863. if (ret)
  864. goto err;
  865. }
  866. ret = chip->setup_data_interface(mtd, chipnr, chip->data_interface);
  867. err:
  868. return ret;
  869. }
  870. /**
  871. * nand_init_data_interface - find the best data interface and timings
  872. * @chip: The NAND chip
  873. *
  874. * Find the best data interface and NAND timings supported by the chip
  875. * and the driver.
  876. * First tries to retrieve supported timing modes from ONFI information,
  877. * and if the NAND chip does not support ONFI, relies on the
  878. * ->onfi_timing_mode_default specified in the nand_ids table. After this
  879. * function nand_chip->data_interface is initialized with the best timing mode
  880. * available.
  881. *
  882. * Returns 0 for success or negative error code otherwise.
  883. */
  884. static int nand_init_data_interface(struct nand_chip *chip)
  885. {
  886. struct mtd_info *mtd = nand_to_mtd(chip);
  887. int modes, mode, ret;
  888. if (!chip->setup_data_interface)
  889. return 0;
  890. /*
  891. * First try to identify the best timings from ONFI parameters and
  892. * if the NAND does not support ONFI, fallback to the default ONFI
  893. * timing mode.
  894. */
  895. modes = onfi_get_async_timing_mode(chip);
  896. if (modes == ONFI_TIMING_MODE_UNKNOWN) {
  897. if (!chip->onfi_timing_mode_default)
  898. return 0;
  899. modes = GENMASK(chip->onfi_timing_mode_default, 0);
  900. }
  901. chip->data_interface = kzalloc(sizeof(*chip->data_interface),
  902. GFP_KERNEL);
  903. if (!chip->data_interface)
  904. return -ENOMEM;
  905. for (mode = fls(modes) - 1; mode >= 0; mode--) {
  906. ret = onfi_init_data_interface(chip, chip->data_interface,
  907. NAND_SDR_IFACE, mode);
  908. if (ret)
  909. continue;
  910. /* Pass -1 to only */
  911. ret = chip->setup_data_interface(mtd,
  912. NAND_DATA_IFACE_CHECK_ONLY,
  913. chip->data_interface);
  914. if (!ret) {
  915. chip->onfi_timing_mode_default = mode;
  916. break;
  917. }
  918. }
  919. return 0;
  920. }
  921. static void __maybe_unused nand_release_data_interface(struct nand_chip *chip)
  922. {
  923. kfree(chip->data_interface);
  924. }
  925. /**
  926. * nand_reset - Reset and initialize a NAND device
  927. * @chip: The NAND chip
  928. * @chipnr: Internal die id
  929. *
  930. * Returns 0 for success or negative error code otherwise
  931. */
  932. int nand_reset(struct nand_chip *chip, int chipnr)
  933. {
  934. struct mtd_info *mtd = nand_to_mtd(chip);
  935. int ret;
  936. ret = nand_reset_data_interface(chip, chipnr);
  937. if (ret)
  938. return ret;
  939. /*
  940. * The CS line has to be released before we can apply the new NAND
  941. * interface settings, hence this weird ->select_chip() dance.
  942. */
  943. chip->select_chip(mtd, chipnr);
  944. chip->cmdfunc(mtd, NAND_CMD_RESET, -1, -1);
  945. chip->select_chip(mtd, -1);
  946. chip->select_chip(mtd, chipnr);
  947. ret = nand_setup_data_interface(chip, chipnr);
  948. chip->select_chip(mtd, -1);
  949. if (ret)
  950. return ret;
  951. return 0;
  952. }
  953. /**
  954. * nand_check_erased_buf - check if a buffer contains (almost) only 0xff data
  955. * @buf: buffer to test
  956. * @len: buffer length
  957. * @bitflips_threshold: maximum number of bitflips
  958. *
  959. * Check if a buffer contains only 0xff, which means the underlying region
  960. * has been erased and is ready to be programmed.
  961. * The bitflips_threshold specify the maximum number of bitflips before
  962. * considering the region is not erased.
  963. * Note: The logic of this function has been extracted from the memweight
  964. * implementation, except that nand_check_erased_buf function exit before
  965. * testing the whole buffer if the number of bitflips exceed the
  966. * bitflips_threshold value.
  967. *
  968. * Returns a positive number of bitflips less than or equal to
  969. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  970. * threshold.
  971. */
  972. static int nand_check_erased_buf(void *buf, int len, int bitflips_threshold)
  973. {
  974. const unsigned char *bitmap = buf;
  975. int bitflips = 0;
  976. int weight;
  977. for (; len && ((uintptr_t)bitmap) % sizeof(long);
  978. len--, bitmap++) {
  979. weight = hweight8(*bitmap);
  980. bitflips += BITS_PER_BYTE - weight;
  981. if (unlikely(bitflips > bitflips_threshold))
  982. return -EBADMSG;
  983. }
  984. for (; len >= 4; len -= 4, bitmap += 4) {
  985. weight = hweight32(*((u32 *)bitmap));
  986. bitflips += 32 - weight;
  987. if (unlikely(bitflips > bitflips_threshold))
  988. return -EBADMSG;
  989. }
  990. for (; len > 0; len--, bitmap++) {
  991. weight = hweight8(*bitmap);
  992. bitflips += BITS_PER_BYTE - weight;
  993. if (unlikely(bitflips > bitflips_threshold))
  994. return -EBADMSG;
  995. }
  996. return bitflips;
  997. }
  998. /**
  999. * nand_check_erased_ecc_chunk - check if an ECC chunk contains (almost) only
  1000. * 0xff data
  1001. * @data: data buffer to test
  1002. * @datalen: data length
  1003. * @ecc: ECC buffer
  1004. * @ecclen: ECC length
  1005. * @extraoob: extra OOB buffer
  1006. * @extraooblen: extra OOB length
  1007. * @bitflips_threshold: maximum number of bitflips
  1008. *
  1009. * Check if a data buffer and its associated ECC and OOB data contains only
  1010. * 0xff pattern, which means the underlying region has been erased and is
  1011. * ready to be programmed.
  1012. * The bitflips_threshold specify the maximum number of bitflips before
  1013. * considering the region as not erased.
  1014. *
  1015. * Note:
  1016. * 1/ ECC algorithms are working on pre-defined block sizes which are usually
  1017. * different from the NAND page size. When fixing bitflips, ECC engines will
  1018. * report the number of errors per chunk, and the NAND core infrastructure
  1019. * expect you to return the maximum number of bitflips for the whole page.
  1020. * This is why you should always use this function on a single chunk and
  1021. * not on the whole page. After checking each chunk you should update your
  1022. * max_bitflips value accordingly.
  1023. * 2/ When checking for bitflips in erased pages you should not only check
  1024. * the payload data but also their associated ECC data, because a user might
  1025. * have programmed almost all bits to 1 but a few. In this case, we
  1026. * shouldn't consider the chunk as erased, and checking ECC bytes prevent
  1027. * this case.
  1028. * 3/ The extraoob argument is optional, and should be used if some of your OOB
  1029. * data are protected by the ECC engine.
  1030. * It could also be used if you support subpages and want to attach some
  1031. * extra OOB data to an ECC chunk.
  1032. *
  1033. * Returns a positive number of bitflips less than or equal to
  1034. * bitflips_threshold, or -ERROR_CODE for bitflips in excess of the
  1035. * threshold. In case of success, the passed buffers are filled with 0xff.
  1036. */
  1037. int nand_check_erased_ecc_chunk(void *data, int datalen,
  1038. void *ecc, int ecclen,
  1039. void *extraoob, int extraooblen,
  1040. int bitflips_threshold)
  1041. {
  1042. int data_bitflips = 0, ecc_bitflips = 0, extraoob_bitflips = 0;
  1043. data_bitflips = nand_check_erased_buf(data, datalen,
  1044. bitflips_threshold);
  1045. if (data_bitflips < 0)
  1046. return data_bitflips;
  1047. bitflips_threshold -= data_bitflips;
  1048. ecc_bitflips = nand_check_erased_buf(ecc, ecclen, bitflips_threshold);
  1049. if (ecc_bitflips < 0)
  1050. return ecc_bitflips;
  1051. bitflips_threshold -= ecc_bitflips;
  1052. extraoob_bitflips = nand_check_erased_buf(extraoob, extraooblen,
  1053. bitflips_threshold);
  1054. if (extraoob_bitflips < 0)
  1055. return extraoob_bitflips;
  1056. if (data_bitflips)
  1057. memset(data, 0xff, datalen);
  1058. if (ecc_bitflips)
  1059. memset(ecc, 0xff, ecclen);
  1060. if (extraoob_bitflips)
  1061. memset(extraoob, 0xff, extraooblen);
  1062. return data_bitflips + ecc_bitflips + extraoob_bitflips;
  1063. }
  1064. EXPORT_SYMBOL(nand_check_erased_ecc_chunk);
  1065. /**
  1066. * nand_read_page_raw - [INTERN] read raw page data without ecc
  1067. * @mtd: mtd info structure
  1068. * @chip: nand chip info structure
  1069. * @buf: buffer to store read data
  1070. * @oob_required: caller requires OOB data read to chip->oob_poi
  1071. * @page: page number to read
  1072. *
  1073. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  1074. */
  1075. static int nand_read_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1076. uint8_t *buf, int oob_required, int page)
  1077. {
  1078. chip->read_buf(mtd, buf, mtd->writesize);
  1079. if (oob_required)
  1080. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1081. return 0;
  1082. }
  1083. /**
  1084. * nand_read_page_raw_syndrome - [INTERN] read raw page data without ecc
  1085. * @mtd: mtd info structure
  1086. * @chip: nand chip info structure
  1087. * @buf: buffer to store read data
  1088. * @oob_required: caller requires OOB data read to chip->oob_poi
  1089. * @page: page number to read
  1090. *
  1091. * We need a special oob layout and handling even when OOB isn't used.
  1092. */
  1093. static int nand_read_page_raw_syndrome(struct mtd_info *mtd,
  1094. struct nand_chip *chip, uint8_t *buf,
  1095. int oob_required, int page)
  1096. {
  1097. int eccsize = chip->ecc.size;
  1098. int eccbytes = chip->ecc.bytes;
  1099. uint8_t *oob = chip->oob_poi;
  1100. int steps, size;
  1101. for (steps = chip->ecc.steps; steps > 0; steps--) {
  1102. chip->read_buf(mtd, buf, eccsize);
  1103. buf += eccsize;
  1104. if (chip->ecc.prepad) {
  1105. chip->read_buf(mtd, oob, chip->ecc.prepad);
  1106. oob += chip->ecc.prepad;
  1107. }
  1108. chip->read_buf(mtd, oob, eccbytes);
  1109. oob += eccbytes;
  1110. if (chip->ecc.postpad) {
  1111. chip->read_buf(mtd, oob, chip->ecc.postpad);
  1112. oob += chip->ecc.postpad;
  1113. }
  1114. }
  1115. size = mtd->oobsize - (oob - chip->oob_poi);
  1116. if (size)
  1117. chip->read_buf(mtd, oob, size);
  1118. return 0;
  1119. }
  1120. /**
  1121. * nand_read_page_swecc - [REPLACEABLE] software ECC based page read function
  1122. * @mtd: mtd info structure
  1123. * @chip: nand chip info structure
  1124. * @buf: buffer to store read data
  1125. * @oob_required: caller requires OOB data read to chip->oob_poi
  1126. * @page: page number to read
  1127. */
  1128. static int nand_read_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  1129. uint8_t *buf, int oob_required, int page)
  1130. {
  1131. int i, eccsize = chip->ecc.size;
  1132. int eccbytes = chip->ecc.bytes;
  1133. int eccsteps = chip->ecc.steps;
  1134. uint8_t *p = buf;
  1135. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1136. uint8_t *ecc_code = chip->buffers->ecccode;
  1137. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1138. unsigned int max_bitflips = 0;
  1139. chip->ecc.read_page_raw(mtd, chip, buf, 1, page);
  1140. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1141. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1142. for (i = 0; i < chip->ecc.total; i++)
  1143. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1144. eccsteps = chip->ecc.steps;
  1145. p = buf;
  1146. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1147. int stat;
  1148. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1149. if (stat < 0) {
  1150. mtd->ecc_stats.failed++;
  1151. } else {
  1152. mtd->ecc_stats.corrected += stat;
  1153. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1154. }
  1155. }
  1156. return max_bitflips;
  1157. }
  1158. /**
  1159. * nand_read_subpage - [REPLACEABLE] ECC based sub-page read function
  1160. * @mtd: mtd info structure
  1161. * @chip: nand chip info structure
  1162. * @data_offs: offset of requested data within the page
  1163. * @readlen: data length
  1164. * @bufpoi: buffer to store read data
  1165. * @page: page number to read
  1166. */
  1167. static int nand_read_subpage(struct mtd_info *mtd, struct nand_chip *chip,
  1168. uint32_t data_offs, uint32_t readlen, uint8_t *bufpoi,
  1169. int page)
  1170. {
  1171. int start_step, end_step, num_steps;
  1172. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1173. uint8_t *p;
  1174. int data_col_addr, i, gaps = 0;
  1175. int datafrag_len, eccfrag_len, aligned_len, aligned_pos;
  1176. int busw = (chip->options & NAND_BUSWIDTH_16) ? 2 : 1;
  1177. int index;
  1178. unsigned int max_bitflips = 0;
  1179. /* Column address within the page aligned to ECC size (256bytes) */
  1180. start_step = data_offs / chip->ecc.size;
  1181. end_step = (data_offs + readlen - 1) / chip->ecc.size;
  1182. num_steps = end_step - start_step + 1;
  1183. index = start_step * chip->ecc.bytes;
  1184. /* Data size aligned to ECC ecc.size */
  1185. datafrag_len = num_steps * chip->ecc.size;
  1186. eccfrag_len = num_steps * chip->ecc.bytes;
  1187. data_col_addr = start_step * chip->ecc.size;
  1188. /* If we read not a page aligned data */
  1189. if (data_col_addr != 0)
  1190. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, data_col_addr, -1);
  1191. p = bufpoi + data_col_addr;
  1192. chip->read_buf(mtd, p, datafrag_len);
  1193. /* Calculate ECC */
  1194. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size)
  1195. chip->ecc.calculate(mtd, p, &chip->buffers->ecccalc[i]);
  1196. /*
  1197. * The performance is faster if we position offsets according to
  1198. * ecc.pos. Let's make sure that there are no gaps in ECC positions.
  1199. */
  1200. for (i = 0; i < eccfrag_len - 1; i++) {
  1201. if (eccpos[i + index] + 1 != eccpos[i + index + 1]) {
  1202. gaps = 1;
  1203. break;
  1204. }
  1205. }
  1206. if (gaps) {
  1207. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, mtd->writesize, -1);
  1208. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1209. } else {
  1210. /*
  1211. * Send the command to read the particular ECC bytes take care
  1212. * about buswidth alignment in read_buf.
  1213. */
  1214. aligned_pos = eccpos[index] & ~(busw - 1);
  1215. aligned_len = eccfrag_len;
  1216. if (eccpos[index] & (busw - 1))
  1217. aligned_len++;
  1218. if (eccpos[index + (num_steps * chip->ecc.bytes)] & (busw - 1))
  1219. aligned_len++;
  1220. chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
  1221. mtd->writesize + aligned_pos, -1);
  1222. chip->read_buf(mtd, &chip->oob_poi[aligned_pos], aligned_len);
  1223. }
  1224. for (i = 0; i < eccfrag_len; i++)
  1225. chip->buffers->ecccode[i] = chip->oob_poi[eccpos[i + index]];
  1226. p = bufpoi + data_col_addr;
  1227. for (i = 0; i < eccfrag_len ; i += chip->ecc.bytes, p += chip->ecc.size) {
  1228. int stat;
  1229. stat = chip->ecc.correct(mtd, p,
  1230. &chip->buffers->ecccode[i], &chip->buffers->ecccalc[i]);
  1231. if (stat == -EBADMSG &&
  1232. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1233. /* check for empty pages with bitflips */
  1234. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  1235. &chip->buffers->ecccode[i],
  1236. chip->ecc.bytes,
  1237. NULL, 0,
  1238. chip->ecc.strength);
  1239. }
  1240. if (stat < 0) {
  1241. mtd->ecc_stats.failed++;
  1242. } else {
  1243. mtd->ecc_stats.corrected += stat;
  1244. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1245. }
  1246. }
  1247. return max_bitflips;
  1248. }
  1249. /**
  1250. * nand_read_page_hwecc - [REPLACEABLE] hardware ECC based page read function
  1251. * @mtd: mtd info structure
  1252. * @chip: nand chip info structure
  1253. * @buf: buffer to store read data
  1254. * @oob_required: caller requires OOB data read to chip->oob_poi
  1255. * @page: page number to read
  1256. *
  1257. * Not for syndrome calculating ECC controllers which need a special oob layout.
  1258. */
  1259. static int nand_read_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  1260. uint8_t *buf, int oob_required, int page)
  1261. {
  1262. int i, eccsize = chip->ecc.size;
  1263. int eccbytes = chip->ecc.bytes;
  1264. int eccsteps = chip->ecc.steps;
  1265. uint8_t *p = buf;
  1266. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1267. uint8_t *ecc_code = chip->buffers->ecccode;
  1268. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1269. unsigned int max_bitflips = 0;
  1270. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1271. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1272. chip->read_buf(mtd, p, eccsize);
  1273. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1274. }
  1275. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1276. for (i = 0; i < chip->ecc.total; i++)
  1277. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1278. eccsteps = chip->ecc.steps;
  1279. p = buf;
  1280. for (i = 0 ; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1281. int stat;
  1282. stat = chip->ecc.correct(mtd, p, &ecc_code[i], &ecc_calc[i]);
  1283. if (stat == -EBADMSG &&
  1284. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1285. /* check for empty pages with bitflips */
  1286. stat = nand_check_erased_ecc_chunk(p, eccsize,
  1287. &ecc_code[i], eccbytes,
  1288. NULL, 0,
  1289. chip->ecc.strength);
  1290. }
  1291. if (stat < 0) {
  1292. mtd->ecc_stats.failed++;
  1293. } else {
  1294. mtd->ecc_stats.corrected += stat;
  1295. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1296. }
  1297. }
  1298. return max_bitflips;
  1299. }
  1300. /**
  1301. * nand_read_page_hwecc_oob_first - [REPLACEABLE] hw ecc, read oob first
  1302. * @mtd: mtd info structure
  1303. * @chip: nand chip info structure
  1304. * @buf: buffer to store read data
  1305. * @oob_required: caller requires OOB data read to chip->oob_poi
  1306. * @page: page number to read
  1307. *
  1308. * Hardware ECC for large page chips, require OOB to be read first. For this
  1309. * ECC mode, the write_page method is re-used from ECC_HW. These methods
  1310. * read/write ECC from the OOB area, unlike the ECC_HW_SYNDROME support with
  1311. * multiple ECC steps, follows the "infix ECC" scheme and reads/writes ECC from
  1312. * the data area, by overwriting the NAND manufacturer bad block markings.
  1313. */
  1314. static int nand_read_page_hwecc_oob_first(struct mtd_info *mtd,
  1315. struct nand_chip *chip, uint8_t *buf, int oob_required, int page)
  1316. {
  1317. int i, eccsize = chip->ecc.size;
  1318. int eccbytes = chip->ecc.bytes;
  1319. int eccsteps = chip->ecc.steps;
  1320. uint8_t *p = buf;
  1321. uint8_t *ecc_code = chip->buffers->ecccode;
  1322. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1323. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1324. unsigned int max_bitflips = 0;
  1325. /* Read the OOB area first */
  1326. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  1327. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1328. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  1329. for (i = 0; i < chip->ecc.total; i++)
  1330. ecc_code[i] = chip->oob_poi[eccpos[i]];
  1331. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1332. int stat;
  1333. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1334. chip->read_buf(mtd, p, eccsize);
  1335. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1336. stat = chip->ecc.correct(mtd, p, &ecc_code[i], NULL);
  1337. if (stat == -EBADMSG &&
  1338. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1339. /* check for empty pages with bitflips */
  1340. stat = nand_check_erased_ecc_chunk(p, eccsize,
  1341. &ecc_code[i], eccbytes,
  1342. NULL, 0,
  1343. chip->ecc.strength);
  1344. }
  1345. if (stat < 0) {
  1346. mtd->ecc_stats.failed++;
  1347. } else {
  1348. mtd->ecc_stats.corrected += stat;
  1349. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1350. }
  1351. }
  1352. return max_bitflips;
  1353. }
  1354. /**
  1355. * nand_read_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page read
  1356. * @mtd: mtd info structure
  1357. * @chip: nand chip info structure
  1358. * @buf: buffer to store read data
  1359. * @oob_required: caller requires OOB data read to chip->oob_poi
  1360. * @page: page number to read
  1361. *
  1362. * The hw generator calculates the error syndrome automatically. Therefore we
  1363. * need a special oob layout and handling.
  1364. */
  1365. static int nand_read_page_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  1366. uint8_t *buf, int oob_required, int page)
  1367. {
  1368. int i, eccsize = chip->ecc.size;
  1369. int eccbytes = chip->ecc.bytes;
  1370. int eccsteps = chip->ecc.steps;
  1371. int eccpadbytes = eccbytes + chip->ecc.prepad + chip->ecc.postpad;
  1372. uint8_t *p = buf;
  1373. uint8_t *oob = chip->oob_poi;
  1374. unsigned int max_bitflips = 0;
  1375. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1376. int stat;
  1377. chip->ecc.hwctl(mtd, NAND_ECC_READ);
  1378. chip->read_buf(mtd, p, eccsize);
  1379. if (chip->ecc.prepad) {
  1380. chip->read_buf(mtd, oob, chip->ecc.prepad);
  1381. oob += chip->ecc.prepad;
  1382. }
  1383. chip->ecc.hwctl(mtd, NAND_ECC_READSYN);
  1384. chip->read_buf(mtd, oob, eccbytes);
  1385. stat = chip->ecc.correct(mtd, p, oob, NULL);
  1386. oob += eccbytes;
  1387. if (chip->ecc.postpad) {
  1388. chip->read_buf(mtd, oob, chip->ecc.postpad);
  1389. oob += chip->ecc.postpad;
  1390. }
  1391. if (stat == -EBADMSG &&
  1392. (chip->ecc.options & NAND_ECC_GENERIC_ERASED_CHECK)) {
  1393. /* check for empty pages with bitflips */
  1394. stat = nand_check_erased_ecc_chunk(p, chip->ecc.size,
  1395. oob - eccpadbytes,
  1396. eccpadbytes,
  1397. NULL, 0,
  1398. chip->ecc.strength);
  1399. }
  1400. if (stat < 0) {
  1401. mtd->ecc_stats.failed++;
  1402. } else {
  1403. mtd->ecc_stats.corrected += stat;
  1404. max_bitflips = max_t(unsigned int, max_bitflips, stat);
  1405. }
  1406. }
  1407. /* Calculate remaining oob bytes */
  1408. i = mtd->oobsize - (oob - chip->oob_poi);
  1409. if (i)
  1410. chip->read_buf(mtd, oob, i);
  1411. return max_bitflips;
  1412. }
  1413. /**
  1414. * nand_transfer_oob - [INTERN] Transfer oob to client buffer
  1415. * @chip: nand chip structure
  1416. * @oob: oob destination address
  1417. * @ops: oob ops structure
  1418. * @len: size of oob to transfer
  1419. */
  1420. static uint8_t *nand_transfer_oob(struct nand_chip *chip, uint8_t *oob,
  1421. struct mtd_oob_ops *ops, size_t len)
  1422. {
  1423. switch (ops->mode) {
  1424. case MTD_OPS_PLACE_OOB:
  1425. case MTD_OPS_RAW:
  1426. memcpy(oob, chip->oob_poi + ops->ooboffs, len);
  1427. return oob + len;
  1428. case MTD_OPS_AUTO_OOB: {
  1429. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  1430. uint32_t boffs = 0, roffs = ops->ooboffs;
  1431. size_t bytes = 0;
  1432. for (; free->length && len; free++, len -= bytes) {
  1433. /* Read request not from offset 0? */
  1434. if (unlikely(roffs)) {
  1435. if (roffs >= free->length) {
  1436. roffs -= free->length;
  1437. continue;
  1438. }
  1439. boffs = free->offset + roffs;
  1440. bytes = min_t(size_t, len,
  1441. (free->length - roffs));
  1442. roffs = 0;
  1443. } else {
  1444. bytes = min_t(size_t, len, free->length);
  1445. boffs = free->offset;
  1446. }
  1447. memcpy(oob, chip->oob_poi + boffs, bytes);
  1448. oob += bytes;
  1449. }
  1450. return oob;
  1451. }
  1452. default:
  1453. BUG();
  1454. }
  1455. return NULL;
  1456. }
  1457. /**
  1458. * nand_setup_read_retry - [INTERN] Set the READ RETRY mode
  1459. * @mtd: MTD device structure
  1460. * @retry_mode: the retry mode to use
  1461. *
  1462. * Some vendors supply a special command to shift the Vt threshold, to be used
  1463. * when there are too many bitflips in a page (i.e., ECC error). After setting
  1464. * a new threshold, the host should retry reading the page.
  1465. */
  1466. static int nand_setup_read_retry(struct mtd_info *mtd, int retry_mode)
  1467. {
  1468. struct nand_chip *chip = mtd_to_nand(mtd);
  1469. pr_debug("setting READ RETRY mode %d\n", retry_mode);
  1470. if (retry_mode >= chip->read_retries)
  1471. return -EINVAL;
  1472. if (!chip->setup_read_retry)
  1473. return -EOPNOTSUPP;
  1474. return chip->setup_read_retry(mtd, retry_mode);
  1475. }
  1476. /**
  1477. * nand_do_read_ops - [INTERN] Read data with ECC
  1478. * @mtd: MTD device structure
  1479. * @from: offset to read from
  1480. * @ops: oob ops structure
  1481. *
  1482. * Internal function. Called with chip held.
  1483. */
  1484. static int nand_do_read_ops(struct mtd_info *mtd, loff_t from,
  1485. struct mtd_oob_ops *ops)
  1486. {
  1487. int chipnr, page, realpage, col, bytes, aligned, oob_required;
  1488. struct nand_chip *chip = mtd_to_nand(mtd);
  1489. int ret = 0;
  1490. uint32_t readlen = ops->len;
  1491. uint32_t oobreadlen = ops->ooblen;
  1492. uint32_t max_oobsize = mtd_oobavail(mtd, ops);
  1493. uint8_t *bufpoi, *oob, *buf;
  1494. int use_bufpoi;
  1495. unsigned int max_bitflips = 0;
  1496. int retry_mode = 0;
  1497. bool ecc_fail = false;
  1498. chipnr = (int)(from >> chip->chip_shift);
  1499. chip->select_chip(mtd, chipnr);
  1500. realpage = (int)(from >> chip->page_shift);
  1501. page = realpage & chip->pagemask;
  1502. col = (int)(from & (mtd->writesize - 1));
  1503. buf = ops->datbuf;
  1504. oob = ops->oobbuf;
  1505. oob_required = oob ? 1 : 0;
  1506. while (1) {
  1507. unsigned int ecc_failures = mtd->ecc_stats.failed;
  1508. WATCHDOG_RESET();
  1509. bytes = min(mtd->writesize - col, readlen);
  1510. aligned = (bytes == mtd->writesize);
  1511. if (!aligned)
  1512. use_bufpoi = 1;
  1513. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  1514. use_bufpoi = !IS_ALIGNED((unsigned long)buf,
  1515. chip->buf_align);
  1516. else
  1517. use_bufpoi = 0;
  1518. /* Is the current page in the buffer? */
  1519. if (realpage != chip->pagebuf || oob) {
  1520. bufpoi = use_bufpoi ? chip->buffers->databuf : buf;
  1521. if (use_bufpoi && aligned)
  1522. pr_debug("%s: using read bounce buffer for buf@%p\n",
  1523. __func__, buf);
  1524. read_retry:
  1525. if (nand_standard_page_accessors(&chip->ecc))
  1526. chip->cmdfunc(mtd, NAND_CMD_READ0, 0x00, page);
  1527. /*
  1528. * Now read the page into the buffer. Absent an error,
  1529. * the read methods return max bitflips per ecc step.
  1530. */
  1531. if (unlikely(ops->mode == MTD_OPS_RAW))
  1532. ret = chip->ecc.read_page_raw(mtd, chip, bufpoi,
  1533. oob_required,
  1534. page);
  1535. else if (!aligned && NAND_HAS_SUBPAGE_READ(chip) &&
  1536. !oob)
  1537. ret = chip->ecc.read_subpage(mtd, chip,
  1538. col, bytes, bufpoi,
  1539. page);
  1540. else
  1541. ret = chip->ecc.read_page(mtd, chip, bufpoi,
  1542. oob_required, page);
  1543. if (ret < 0) {
  1544. if (use_bufpoi)
  1545. /* Invalidate page cache */
  1546. chip->pagebuf = -1;
  1547. break;
  1548. }
  1549. max_bitflips = max_t(unsigned int, max_bitflips, ret);
  1550. /* Transfer not aligned data */
  1551. if (use_bufpoi) {
  1552. if (!NAND_HAS_SUBPAGE_READ(chip) && !oob &&
  1553. !(mtd->ecc_stats.failed - ecc_failures) &&
  1554. (ops->mode != MTD_OPS_RAW)) {
  1555. chip->pagebuf = realpage;
  1556. chip->pagebuf_bitflips = ret;
  1557. } else {
  1558. /* Invalidate page cache */
  1559. chip->pagebuf = -1;
  1560. }
  1561. memcpy(buf, chip->buffers->databuf + col, bytes);
  1562. }
  1563. if (unlikely(oob)) {
  1564. int toread = min(oobreadlen, max_oobsize);
  1565. if (toread) {
  1566. oob = nand_transfer_oob(chip,
  1567. oob, ops, toread);
  1568. oobreadlen -= toread;
  1569. }
  1570. }
  1571. if (chip->options & NAND_NEED_READRDY) {
  1572. /* Apply delay or wait for ready/busy pin */
  1573. if (!chip->dev_ready)
  1574. udelay(chip->chip_delay);
  1575. else
  1576. nand_wait_ready(mtd);
  1577. }
  1578. if (mtd->ecc_stats.failed - ecc_failures) {
  1579. if (retry_mode + 1 < chip->read_retries) {
  1580. retry_mode++;
  1581. ret = nand_setup_read_retry(mtd,
  1582. retry_mode);
  1583. if (ret < 0)
  1584. break;
  1585. /* Reset failures; retry */
  1586. mtd->ecc_stats.failed = ecc_failures;
  1587. goto read_retry;
  1588. } else {
  1589. /* No more retry modes; real failure */
  1590. ecc_fail = true;
  1591. }
  1592. }
  1593. buf += bytes;
  1594. } else {
  1595. memcpy(buf, chip->buffers->databuf + col, bytes);
  1596. buf += bytes;
  1597. max_bitflips = max_t(unsigned int, max_bitflips,
  1598. chip->pagebuf_bitflips);
  1599. }
  1600. readlen -= bytes;
  1601. /* Reset to retry mode 0 */
  1602. if (retry_mode) {
  1603. ret = nand_setup_read_retry(mtd, 0);
  1604. if (ret < 0)
  1605. break;
  1606. retry_mode = 0;
  1607. }
  1608. if (!readlen)
  1609. break;
  1610. /* For subsequent reads align to page boundary */
  1611. col = 0;
  1612. /* Increment page address */
  1613. realpage++;
  1614. page = realpage & chip->pagemask;
  1615. /* Check, if we cross a chip boundary */
  1616. if (!page) {
  1617. chipnr++;
  1618. chip->select_chip(mtd, -1);
  1619. chip->select_chip(mtd, chipnr);
  1620. }
  1621. }
  1622. chip->select_chip(mtd, -1);
  1623. ops->retlen = ops->len - (size_t) readlen;
  1624. if (oob)
  1625. ops->oobretlen = ops->ooblen - oobreadlen;
  1626. if (ret < 0)
  1627. return ret;
  1628. if (ecc_fail)
  1629. return -EBADMSG;
  1630. return max_bitflips;
  1631. }
  1632. /**
  1633. * nand_read_oob_std - [REPLACEABLE] the most common OOB data read function
  1634. * @mtd: mtd info structure
  1635. * @chip: nand chip info structure
  1636. * @page: page number to read
  1637. */
  1638. static int nand_read_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  1639. int page)
  1640. {
  1641. chip->cmdfunc(mtd, NAND_CMD_READOOB, 0, page);
  1642. chip->read_buf(mtd, chip->oob_poi, mtd->oobsize);
  1643. return 0;
  1644. }
  1645. /**
  1646. * nand_read_oob_syndrome - [REPLACEABLE] OOB data read function for HW ECC
  1647. * with syndromes
  1648. * @mtd: mtd info structure
  1649. * @chip: nand chip info structure
  1650. * @page: page number to read
  1651. */
  1652. static int nand_read_oob_syndrome(struct mtd_info *mtd, struct nand_chip *chip,
  1653. int page)
  1654. {
  1655. int length = mtd->oobsize;
  1656. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  1657. int eccsize = chip->ecc.size;
  1658. uint8_t *bufpoi = chip->oob_poi;
  1659. int i, toread, sndrnd = 0, pos;
  1660. chip->cmdfunc(mtd, NAND_CMD_READ0, chip->ecc.size, page);
  1661. for (i = 0; i < chip->ecc.steps; i++) {
  1662. if (sndrnd) {
  1663. pos = eccsize + i * (eccsize + chunk);
  1664. if (mtd->writesize > 512)
  1665. chip->cmdfunc(mtd, NAND_CMD_RNDOUT, pos, -1);
  1666. else
  1667. chip->cmdfunc(mtd, NAND_CMD_READ0, pos, page);
  1668. } else
  1669. sndrnd = 1;
  1670. toread = min_t(int, length, chunk);
  1671. chip->read_buf(mtd, bufpoi, toread);
  1672. bufpoi += toread;
  1673. length -= toread;
  1674. }
  1675. if (length > 0)
  1676. chip->read_buf(mtd, bufpoi, length);
  1677. return 0;
  1678. }
  1679. /**
  1680. * nand_write_oob_std - [REPLACEABLE] the most common OOB data write function
  1681. * @mtd: mtd info structure
  1682. * @chip: nand chip info structure
  1683. * @page: page number to write
  1684. */
  1685. static int nand_write_oob_std(struct mtd_info *mtd, struct nand_chip *chip,
  1686. int page)
  1687. {
  1688. int status = 0;
  1689. const uint8_t *buf = chip->oob_poi;
  1690. int length = mtd->oobsize;
  1691. chip->cmdfunc(mtd, NAND_CMD_SEQIN, mtd->writesize, page);
  1692. chip->write_buf(mtd, buf, length);
  1693. /* Send command to program the OOB data */
  1694. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1695. status = chip->waitfunc(mtd, chip);
  1696. return status & NAND_STATUS_FAIL ? -EIO : 0;
  1697. }
  1698. /**
  1699. * nand_write_oob_syndrome - [REPLACEABLE] OOB data write function for HW ECC
  1700. * with syndrome - only for large page flash
  1701. * @mtd: mtd info structure
  1702. * @chip: nand chip info structure
  1703. * @page: page number to write
  1704. */
  1705. static int nand_write_oob_syndrome(struct mtd_info *mtd,
  1706. struct nand_chip *chip, int page)
  1707. {
  1708. int chunk = chip->ecc.bytes + chip->ecc.prepad + chip->ecc.postpad;
  1709. int eccsize = chip->ecc.size, length = mtd->oobsize;
  1710. int i, len, pos, status = 0, sndcmd = 0, steps = chip->ecc.steps;
  1711. const uint8_t *bufpoi = chip->oob_poi;
  1712. /*
  1713. * data-ecc-data-ecc ... ecc-oob
  1714. * or
  1715. * data-pad-ecc-pad-data-pad .... ecc-pad-oob
  1716. */
  1717. if (!chip->ecc.prepad && !chip->ecc.postpad) {
  1718. pos = steps * (eccsize + chunk);
  1719. steps = 0;
  1720. } else
  1721. pos = eccsize;
  1722. chip->cmdfunc(mtd, NAND_CMD_SEQIN, pos, page);
  1723. for (i = 0; i < steps; i++) {
  1724. if (sndcmd) {
  1725. if (mtd->writesize <= 512) {
  1726. uint32_t fill = 0xFFFFFFFF;
  1727. len = eccsize;
  1728. while (len > 0) {
  1729. int num = min_t(int, len, 4);
  1730. chip->write_buf(mtd, (uint8_t *)&fill,
  1731. num);
  1732. len -= num;
  1733. }
  1734. } else {
  1735. pos = eccsize + i * (eccsize + chunk);
  1736. chip->cmdfunc(mtd, NAND_CMD_RNDIN, pos, -1);
  1737. }
  1738. } else
  1739. sndcmd = 1;
  1740. len = min_t(int, length, chunk);
  1741. chip->write_buf(mtd, bufpoi, len);
  1742. bufpoi += len;
  1743. length -= len;
  1744. }
  1745. if (length > 0)
  1746. chip->write_buf(mtd, bufpoi, length);
  1747. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  1748. status = chip->waitfunc(mtd, chip);
  1749. return status & NAND_STATUS_FAIL ? -EIO : 0;
  1750. }
  1751. /**
  1752. * nand_do_read_oob - [INTERN] NAND read out-of-band
  1753. * @mtd: MTD device structure
  1754. * @from: offset to read from
  1755. * @ops: oob operations description structure
  1756. *
  1757. * NAND read out-of-band data from the spare area.
  1758. */
  1759. static int nand_do_read_oob(struct mtd_info *mtd, loff_t from,
  1760. struct mtd_oob_ops *ops)
  1761. {
  1762. int page, realpage, chipnr;
  1763. struct nand_chip *chip = mtd_to_nand(mtd);
  1764. struct mtd_ecc_stats stats;
  1765. int readlen = ops->ooblen;
  1766. int len;
  1767. uint8_t *buf = ops->oobbuf;
  1768. int ret = 0;
  1769. pr_debug("%s: from = 0x%08Lx, len = %i\n",
  1770. __func__, (unsigned long long)from, readlen);
  1771. stats = mtd->ecc_stats;
  1772. len = mtd_oobavail(mtd, ops);
  1773. if (unlikely(ops->ooboffs >= len)) {
  1774. pr_debug("%s: attempt to start read outside oob\n",
  1775. __func__);
  1776. return -EINVAL;
  1777. }
  1778. /* Do not allow reads past end of device */
  1779. if (unlikely(from >= mtd->size ||
  1780. ops->ooboffs + readlen > ((mtd->size >> chip->page_shift) -
  1781. (from >> chip->page_shift)) * len)) {
  1782. pr_debug("%s: attempt to read beyond end of device\n",
  1783. __func__);
  1784. return -EINVAL;
  1785. }
  1786. chipnr = (int)(from >> chip->chip_shift);
  1787. chip->select_chip(mtd, chipnr);
  1788. /* Shift to get page */
  1789. realpage = (int)(from >> chip->page_shift);
  1790. page = realpage & chip->pagemask;
  1791. while (1) {
  1792. WATCHDOG_RESET();
  1793. if (ops->mode == MTD_OPS_RAW)
  1794. ret = chip->ecc.read_oob_raw(mtd, chip, page);
  1795. else
  1796. ret = chip->ecc.read_oob(mtd, chip, page);
  1797. if (ret < 0)
  1798. break;
  1799. len = min(len, readlen);
  1800. buf = nand_transfer_oob(chip, buf, ops, len);
  1801. if (chip->options & NAND_NEED_READRDY) {
  1802. /* Apply delay or wait for ready/busy pin */
  1803. if (!chip->dev_ready)
  1804. udelay(chip->chip_delay);
  1805. else
  1806. nand_wait_ready(mtd);
  1807. }
  1808. readlen -= len;
  1809. if (!readlen)
  1810. break;
  1811. /* Increment page address */
  1812. realpage++;
  1813. page = realpage & chip->pagemask;
  1814. /* Check, if we cross a chip boundary */
  1815. if (!page) {
  1816. chipnr++;
  1817. chip->select_chip(mtd, -1);
  1818. chip->select_chip(mtd, chipnr);
  1819. }
  1820. }
  1821. chip->select_chip(mtd, -1);
  1822. ops->oobretlen = ops->ooblen - readlen;
  1823. if (ret < 0)
  1824. return ret;
  1825. if (mtd->ecc_stats.failed - stats.failed)
  1826. return -EBADMSG;
  1827. return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0;
  1828. }
  1829. /**
  1830. * nand_read_oob - [MTD Interface] NAND read data and/or out-of-band
  1831. * @mtd: MTD device structure
  1832. * @from: offset to read from
  1833. * @ops: oob operation description structure
  1834. *
  1835. * NAND read data and/or out-of-band data.
  1836. */
  1837. static int nand_read_oob(struct mtd_info *mtd, loff_t from,
  1838. struct mtd_oob_ops *ops)
  1839. {
  1840. int ret = -ENOTSUPP;
  1841. ops->retlen = 0;
  1842. /* Do not allow reads past end of device */
  1843. if (ops->datbuf && (from + ops->len) > mtd->size) {
  1844. pr_debug("%s: attempt to read beyond end of device\n",
  1845. __func__);
  1846. return -EINVAL;
  1847. }
  1848. nand_get_device(mtd, FL_READING);
  1849. switch (ops->mode) {
  1850. case MTD_OPS_PLACE_OOB:
  1851. case MTD_OPS_AUTO_OOB:
  1852. case MTD_OPS_RAW:
  1853. break;
  1854. default:
  1855. goto out;
  1856. }
  1857. if (!ops->datbuf)
  1858. ret = nand_do_read_oob(mtd, from, ops);
  1859. else
  1860. ret = nand_do_read_ops(mtd, from, ops);
  1861. out:
  1862. nand_release_device(mtd);
  1863. return ret;
  1864. }
  1865. /**
  1866. * nand_write_page_raw - [INTERN] raw page write function
  1867. * @mtd: mtd info structure
  1868. * @chip: nand chip info structure
  1869. * @buf: data buffer
  1870. * @oob_required: must write chip->oob_poi to OOB
  1871. * @page: page number to write
  1872. *
  1873. * Not for syndrome calculating ECC controllers, which use a special oob layout.
  1874. */
  1875. static int nand_write_page_raw(struct mtd_info *mtd, struct nand_chip *chip,
  1876. const uint8_t *buf, int oob_required, int page)
  1877. {
  1878. chip->write_buf(mtd, buf, mtd->writesize);
  1879. if (oob_required)
  1880. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1881. return 0;
  1882. }
  1883. /**
  1884. * nand_write_page_raw_syndrome - [INTERN] raw page write function
  1885. * @mtd: mtd info structure
  1886. * @chip: nand chip info structure
  1887. * @buf: data buffer
  1888. * @oob_required: must write chip->oob_poi to OOB
  1889. * @page: page number to write
  1890. *
  1891. * We need a special oob layout and handling even when ECC isn't checked.
  1892. */
  1893. static int nand_write_page_raw_syndrome(struct mtd_info *mtd,
  1894. struct nand_chip *chip,
  1895. const uint8_t *buf, int oob_required,
  1896. int page)
  1897. {
  1898. int eccsize = chip->ecc.size;
  1899. int eccbytes = chip->ecc.bytes;
  1900. uint8_t *oob = chip->oob_poi;
  1901. int steps, size;
  1902. for (steps = chip->ecc.steps; steps > 0; steps--) {
  1903. chip->write_buf(mtd, buf, eccsize);
  1904. buf += eccsize;
  1905. if (chip->ecc.prepad) {
  1906. chip->write_buf(mtd, oob, chip->ecc.prepad);
  1907. oob += chip->ecc.prepad;
  1908. }
  1909. chip->write_buf(mtd, oob, eccbytes);
  1910. oob += eccbytes;
  1911. if (chip->ecc.postpad) {
  1912. chip->write_buf(mtd, oob, chip->ecc.postpad);
  1913. oob += chip->ecc.postpad;
  1914. }
  1915. }
  1916. size = mtd->oobsize - (oob - chip->oob_poi);
  1917. if (size)
  1918. chip->write_buf(mtd, oob, size);
  1919. return 0;
  1920. }
  1921. /**
  1922. * nand_write_page_swecc - [REPLACEABLE] software ECC based page write function
  1923. * @mtd: mtd info structure
  1924. * @chip: nand chip info structure
  1925. * @buf: data buffer
  1926. * @oob_required: must write chip->oob_poi to OOB
  1927. * @page: page number to write
  1928. */
  1929. static int nand_write_page_swecc(struct mtd_info *mtd, struct nand_chip *chip,
  1930. const uint8_t *buf, int oob_required,
  1931. int page)
  1932. {
  1933. int i, eccsize = chip->ecc.size;
  1934. int eccbytes = chip->ecc.bytes;
  1935. int eccsteps = chip->ecc.steps;
  1936. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1937. const uint8_t *p = buf;
  1938. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1939. /* Software ECC calculation */
  1940. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize)
  1941. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1942. for (i = 0; i < chip->ecc.total; i++)
  1943. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  1944. return chip->ecc.write_page_raw(mtd, chip, buf, 1, page);
  1945. }
  1946. /**
  1947. * nand_write_page_hwecc - [REPLACEABLE] hardware ECC based page write function
  1948. * @mtd: mtd info structure
  1949. * @chip: nand chip info structure
  1950. * @buf: data buffer
  1951. * @oob_required: must write chip->oob_poi to OOB
  1952. * @page: page number to write
  1953. */
  1954. static int nand_write_page_hwecc(struct mtd_info *mtd, struct nand_chip *chip,
  1955. const uint8_t *buf, int oob_required,
  1956. int page)
  1957. {
  1958. int i, eccsize = chip->ecc.size;
  1959. int eccbytes = chip->ecc.bytes;
  1960. int eccsteps = chip->ecc.steps;
  1961. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1962. const uint8_t *p = buf;
  1963. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1964. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  1965. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  1966. chip->write_buf(mtd, p, eccsize);
  1967. chip->ecc.calculate(mtd, p, &ecc_calc[i]);
  1968. }
  1969. for (i = 0; i < chip->ecc.total; i++)
  1970. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  1971. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  1972. return 0;
  1973. }
  1974. /**
  1975. * nand_write_subpage_hwecc - [REPLACEABLE] hardware ECC based subpage write
  1976. * @mtd: mtd info structure
  1977. * @chip: nand chip info structure
  1978. * @offset: column address of subpage within the page
  1979. * @data_len: data length
  1980. * @buf: data buffer
  1981. * @oob_required: must write chip->oob_poi to OOB
  1982. * @page: page number to write
  1983. */
  1984. static int nand_write_subpage_hwecc(struct mtd_info *mtd,
  1985. struct nand_chip *chip, uint32_t offset,
  1986. uint32_t data_len, const uint8_t *buf,
  1987. int oob_required, int page)
  1988. {
  1989. uint8_t *oob_buf = chip->oob_poi;
  1990. uint8_t *ecc_calc = chip->buffers->ecccalc;
  1991. int ecc_size = chip->ecc.size;
  1992. int ecc_bytes = chip->ecc.bytes;
  1993. int ecc_steps = chip->ecc.steps;
  1994. uint32_t *eccpos = chip->ecc.layout->eccpos;
  1995. uint32_t start_step = offset / ecc_size;
  1996. uint32_t end_step = (offset + data_len - 1) / ecc_size;
  1997. int oob_bytes = mtd->oobsize / ecc_steps;
  1998. int step, i;
  1999. for (step = 0; step < ecc_steps; step++) {
  2000. /* configure controller for WRITE access */
  2001. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2002. /* write data (untouched subpages already masked by 0xFF) */
  2003. chip->write_buf(mtd, buf, ecc_size);
  2004. /* mask ECC of un-touched subpages by padding 0xFF */
  2005. if ((step < start_step) || (step > end_step))
  2006. memset(ecc_calc, 0xff, ecc_bytes);
  2007. else
  2008. chip->ecc.calculate(mtd, buf, ecc_calc);
  2009. /* mask OOB of un-touched subpages by padding 0xFF */
  2010. /* if oob_required, preserve OOB metadata of written subpage */
  2011. if (!oob_required || (step < start_step) || (step > end_step))
  2012. memset(oob_buf, 0xff, oob_bytes);
  2013. buf += ecc_size;
  2014. ecc_calc += ecc_bytes;
  2015. oob_buf += oob_bytes;
  2016. }
  2017. /* copy calculated ECC for whole page to chip->buffer->oob */
  2018. /* this include masked-value(0xFF) for unwritten subpages */
  2019. ecc_calc = chip->buffers->ecccalc;
  2020. for (i = 0; i < chip->ecc.total; i++)
  2021. chip->oob_poi[eccpos[i]] = ecc_calc[i];
  2022. /* write OOB buffer to NAND device */
  2023. chip->write_buf(mtd, chip->oob_poi, mtd->oobsize);
  2024. return 0;
  2025. }
  2026. /**
  2027. * nand_write_page_syndrome - [REPLACEABLE] hardware ECC syndrome based page write
  2028. * @mtd: mtd info structure
  2029. * @chip: nand chip info structure
  2030. * @buf: data buffer
  2031. * @oob_required: must write chip->oob_poi to OOB
  2032. * @page: page number to write
  2033. *
  2034. * The hw generator calculates the error syndrome automatically. Therefore we
  2035. * need a special oob layout and handling.
  2036. */
  2037. static int nand_write_page_syndrome(struct mtd_info *mtd,
  2038. struct nand_chip *chip,
  2039. const uint8_t *buf, int oob_required,
  2040. int page)
  2041. {
  2042. int i, eccsize = chip->ecc.size;
  2043. int eccbytes = chip->ecc.bytes;
  2044. int eccsteps = chip->ecc.steps;
  2045. const uint8_t *p = buf;
  2046. uint8_t *oob = chip->oob_poi;
  2047. for (i = 0; eccsteps; eccsteps--, i += eccbytes, p += eccsize) {
  2048. chip->ecc.hwctl(mtd, NAND_ECC_WRITE);
  2049. chip->write_buf(mtd, p, eccsize);
  2050. if (chip->ecc.prepad) {
  2051. chip->write_buf(mtd, oob, chip->ecc.prepad);
  2052. oob += chip->ecc.prepad;
  2053. }
  2054. chip->ecc.calculate(mtd, p, oob);
  2055. chip->write_buf(mtd, oob, eccbytes);
  2056. oob += eccbytes;
  2057. if (chip->ecc.postpad) {
  2058. chip->write_buf(mtd, oob, chip->ecc.postpad);
  2059. oob += chip->ecc.postpad;
  2060. }
  2061. }
  2062. /* Calculate remaining oob bytes */
  2063. i = mtd->oobsize - (oob - chip->oob_poi);
  2064. if (i)
  2065. chip->write_buf(mtd, oob, i);
  2066. return 0;
  2067. }
  2068. /**
  2069. * nand_write_page - [REPLACEABLE] write one page
  2070. * @mtd: MTD device structure
  2071. * @chip: NAND chip descriptor
  2072. * @offset: address offset within the page
  2073. * @data_len: length of actual data to be written
  2074. * @buf: the data to write
  2075. * @oob_required: must write chip->oob_poi to OOB
  2076. * @page: page number to write
  2077. * @raw: use _raw version of write_page
  2078. */
  2079. static int nand_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  2080. uint32_t offset, int data_len, const uint8_t *buf,
  2081. int oob_required, int page, int raw)
  2082. {
  2083. int status, subpage;
  2084. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) &&
  2085. chip->ecc.write_subpage)
  2086. subpage = offset || (data_len < mtd->writesize);
  2087. else
  2088. subpage = 0;
  2089. if (nand_standard_page_accessors(&chip->ecc))
  2090. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x00, page);
  2091. if (unlikely(raw))
  2092. status = chip->ecc.write_page_raw(mtd, chip, buf,
  2093. oob_required, page);
  2094. else if (subpage)
  2095. status = chip->ecc.write_subpage(mtd, chip, offset, data_len,
  2096. buf, oob_required, page);
  2097. else
  2098. status = chip->ecc.write_page(mtd, chip, buf, oob_required,
  2099. page);
  2100. if (status < 0)
  2101. return status;
  2102. if (nand_standard_page_accessors(&chip->ecc)) {
  2103. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  2104. status = chip->waitfunc(mtd, chip);
  2105. if (status & NAND_STATUS_FAIL)
  2106. return -EIO;
  2107. }
  2108. return 0;
  2109. }
  2110. /**
  2111. * nand_fill_oob - [INTERN] Transfer client buffer to oob
  2112. * @mtd: MTD device structure
  2113. * @oob: oob data buffer
  2114. * @len: oob data write length
  2115. * @ops: oob ops structure
  2116. */
  2117. static uint8_t *nand_fill_oob(struct mtd_info *mtd, uint8_t *oob, size_t len,
  2118. struct mtd_oob_ops *ops)
  2119. {
  2120. struct nand_chip *chip = mtd_to_nand(mtd);
  2121. /*
  2122. * Initialise to all 0xFF, to avoid the possibility of left over OOB
  2123. * data from a previous OOB read.
  2124. */
  2125. memset(chip->oob_poi, 0xff, mtd->oobsize);
  2126. switch (ops->mode) {
  2127. case MTD_OPS_PLACE_OOB:
  2128. case MTD_OPS_RAW:
  2129. memcpy(chip->oob_poi + ops->ooboffs, oob, len);
  2130. return oob + len;
  2131. case MTD_OPS_AUTO_OOB: {
  2132. struct nand_oobfree *free = chip->ecc.layout->oobfree;
  2133. uint32_t boffs = 0, woffs = ops->ooboffs;
  2134. size_t bytes = 0;
  2135. for (; free->length && len; free++, len -= bytes) {
  2136. /* Write request not from offset 0? */
  2137. if (unlikely(woffs)) {
  2138. if (woffs >= free->length) {
  2139. woffs -= free->length;
  2140. continue;
  2141. }
  2142. boffs = free->offset + woffs;
  2143. bytes = min_t(size_t, len,
  2144. (free->length - woffs));
  2145. woffs = 0;
  2146. } else {
  2147. bytes = min_t(size_t, len, free->length);
  2148. boffs = free->offset;
  2149. }
  2150. memcpy(chip->oob_poi + boffs, oob, bytes);
  2151. oob += bytes;
  2152. }
  2153. return oob;
  2154. }
  2155. default:
  2156. BUG();
  2157. }
  2158. return NULL;
  2159. }
  2160. #define NOTALIGNED(x) ((x & (chip->subpagesize - 1)) != 0)
  2161. /**
  2162. * nand_do_write_ops - [INTERN] NAND write with ECC
  2163. * @mtd: MTD device structure
  2164. * @to: offset to write to
  2165. * @ops: oob operations description structure
  2166. *
  2167. * NAND write with ECC.
  2168. */
  2169. static int nand_do_write_ops(struct mtd_info *mtd, loff_t to,
  2170. struct mtd_oob_ops *ops)
  2171. {
  2172. int chipnr, realpage, page, column;
  2173. struct nand_chip *chip = mtd_to_nand(mtd);
  2174. uint32_t writelen = ops->len;
  2175. uint32_t oobwritelen = ops->ooblen;
  2176. uint32_t oobmaxlen = mtd_oobavail(mtd, ops);
  2177. uint8_t *oob = ops->oobbuf;
  2178. uint8_t *buf = ops->datbuf;
  2179. int ret;
  2180. int oob_required = oob ? 1 : 0;
  2181. ops->retlen = 0;
  2182. if (!writelen)
  2183. return 0;
  2184. /* Reject writes, which are not page aligned */
  2185. if (NOTALIGNED(to)) {
  2186. pr_notice("%s: attempt to write non page aligned data\n",
  2187. __func__);
  2188. return -EINVAL;
  2189. }
  2190. column = to & (mtd->writesize - 1);
  2191. chipnr = (int)(to >> chip->chip_shift);
  2192. chip->select_chip(mtd, chipnr);
  2193. /* Check, if it is write protected */
  2194. if (nand_check_wp(mtd)) {
  2195. ret = -EIO;
  2196. goto err_out;
  2197. }
  2198. realpage = (int)(to >> chip->page_shift);
  2199. page = realpage & chip->pagemask;
  2200. /* Invalidate the page cache, when we write to the cached page */
  2201. if (to <= ((loff_t)chip->pagebuf << chip->page_shift) &&
  2202. ((loff_t)chip->pagebuf << chip->page_shift) < (to + ops->len))
  2203. chip->pagebuf = -1;
  2204. /* Don't allow multipage oob writes with offset */
  2205. if (oob && ops->ooboffs && (ops->ooboffs + ops->ooblen > oobmaxlen)) {
  2206. ret = -EINVAL;
  2207. goto err_out;
  2208. }
  2209. while (1) {
  2210. int bytes = mtd->writesize;
  2211. uint8_t *wbuf = buf;
  2212. int use_bufpoi;
  2213. int part_pagewr = (column || writelen < mtd->writesize);
  2214. if (part_pagewr)
  2215. use_bufpoi = 1;
  2216. else if (chip->options & NAND_USE_BOUNCE_BUFFER)
  2217. use_bufpoi = !IS_ALIGNED((unsigned long)buf,
  2218. chip->buf_align);
  2219. else
  2220. use_bufpoi = 0;
  2221. WATCHDOG_RESET();
  2222. /* Partial page write?, or need to use bounce buffer */
  2223. if (use_bufpoi) {
  2224. pr_debug("%s: using write bounce buffer for buf@%p\n",
  2225. __func__, buf);
  2226. if (part_pagewr)
  2227. bytes = min_t(int, bytes - column, writelen);
  2228. chip->pagebuf = -1;
  2229. memset(chip->buffers->databuf, 0xff, mtd->writesize);
  2230. memcpy(&chip->buffers->databuf[column], buf, bytes);
  2231. wbuf = chip->buffers->databuf;
  2232. }
  2233. if (unlikely(oob)) {
  2234. size_t len = min(oobwritelen, oobmaxlen);
  2235. oob = nand_fill_oob(mtd, oob, len, ops);
  2236. oobwritelen -= len;
  2237. } else {
  2238. /* We still need to erase leftover OOB data */
  2239. memset(chip->oob_poi, 0xff, mtd->oobsize);
  2240. }
  2241. ret = chip->write_page(mtd, chip, column, bytes, wbuf,
  2242. oob_required, page,
  2243. (ops->mode == MTD_OPS_RAW));
  2244. if (ret)
  2245. break;
  2246. writelen -= bytes;
  2247. if (!writelen)
  2248. break;
  2249. column = 0;
  2250. buf += bytes;
  2251. realpage++;
  2252. page = realpage & chip->pagemask;
  2253. /* Check, if we cross a chip boundary */
  2254. if (!page) {
  2255. chipnr++;
  2256. chip->select_chip(mtd, -1);
  2257. chip->select_chip(mtd, chipnr);
  2258. }
  2259. }
  2260. ops->retlen = ops->len - writelen;
  2261. if (unlikely(oob))
  2262. ops->oobretlen = ops->ooblen;
  2263. err_out:
  2264. chip->select_chip(mtd, -1);
  2265. return ret;
  2266. }
  2267. /**
  2268. * panic_nand_write - [MTD Interface] NAND write with ECC
  2269. * @mtd: MTD device structure
  2270. * @to: offset to write to
  2271. * @len: number of bytes to write
  2272. * @retlen: pointer to variable to store the number of written bytes
  2273. * @buf: the data to write
  2274. *
  2275. * NAND write with ECC. Used when performing writes in interrupt context, this
  2276. * may for example be called by mtdoops when writing an oops while in panic.
  2277. */
  2278. static int panic_nand_write(struct mtd_info *mtd, loff_t to, size_t len,
  2279. size_t *retlen, const uint8_t *buf)
  2280. {
  2281. struct nand_chip *chip = mtd_to_nand(mtd);
  2282. struct mtd_oob_ops ops;
  2283. int ret;
  2284. /* Wait for the device to get ready */
  2285. panic_nand_wait(mtd, chip, 400);
  2286. /* Grab the device */
  2287. panic_nand_get_device(chip, mtd, FL_WRITING);
  2288. memset(&ops, 0, sizeof(ops));
  2289. ops.len = len;
  2290. ops.datbuf = (uint8_t *)buf;
  2291. ops.mode = MTD_OPS_PLACE_OOB;
  2292. ret = nand_do_write_ops(mtd, to, &ops);
  2293. *retlen = ops.retlen;
  2294. return ret;
  2295. }
  2296. /**
  2297. * nand_do_write_oob - [MTD Interface] NAND write out-of-band
  2298. * @mtd: MTD device structure
  2299. * @to: offset to write to
  2300. * @ops: oob operation description structure
  2301. *
  2302. * NAND write out-of-band.
  2303. */
  2304. static int nand_do_write_oob(struct mtd_info *mtd, loff_t to,
  2305. struct mtd_oob_ops *ops)
  2306. {
  2307. int chipnr, page, status, len;
  2308. struct nand_chip *chip = mtd_to_nand(mtd);
  2309. pr_debug("%s: to = 0x%08x, len = %i\n",
  2310. __func__, (unsigned int)to, (int)ops->ooblen);
  2311. len = mtd_oobavail(mtd, ops);
  2312. /* Do not allow write past end of page */
  2313. if ((ops->ooboffs + ops->ooblen) > len) {
  2314. pr_debug("%s: attempt to write past end of page\n",
  2315. __func__);
  2316. return -EINVAL;
  2317. }
  2318. if (unlikely(ops->ooboffs >= len)) {
  2319. pr_debug("%s: attempt to start write outside oob\n",
  2320. __func__);
  2321. return -EINVAL;
  2322. }
  2323. /* Do not allow write past end of device */
  2324. if (unlikely(to >= mtd->size ||
  2325. ops->ooboffs + ops->ooblen >
  2326. ((mtd->size >> chip->page_shift) -
  2327. (to >> chip->page_shift)) * len)) {
  2328. pr_debug("%s: attempt to write beyond end of device\n",
  2329. __func__);
  2330. return -EINVAL;
  2331. }
  2332. chipnr = (int)(to >> chip->chip_shift);
  2333. /*
  2334. * Reset the chip. Some chips (like the Toshiba TC5832DC found in one
  2335. * of my DiskOnChip 2000 test units) will clear the whole data page too
  2336. * if we don't do this. I have no clue why, but I seem to have 'fixed'
  2337. * it in the doc2000 driver in August 1999. dwmw2.
  2338. */
  2339. nand_reset(chip, chipnr);
  2340. chip->select_chip(mtd, chipnr);
  2341. /* Shift to get page */
  2342. page = (int)(to >> chip->page_shift);
  2343. /* Check, if it is write protected */
  2344. if (nand_check_wp(mtd)) {
  2345. chip->select_chip(mtd, -1);
  2346. return -EROFS;
  2347. }
  2348. /* Invalidate the page cache, if we write to the cached page */
  2349. if (page == chip->pagebuf)
  2350. chip->pagebuf = -1;
  2351. nand_fill_oob(mtd, ops->oobbuf, ops->ooblen, ops);
  2352. if (ops->mode == MTD_OPS_RAW)
  2353. status = chip->ecc.write_oob_raw(mtd, chip, page & chip->pagemask);
  2354. else
  2355. status = chip->ecc.write_oob(mtd, chip, page & chip->pagemask);
  2356. chip->select_chip(mtd, -1);
  2357. if (status)
  2358. return status;
  2359. ops->oobretlen = ops->ooblen;
  2360. return 0;
  2361. }
  2362. /**
  2363. * nand_write_oob - [MTD Interface] NAND write data and/or out-of-band
  2364. * @mtd: MTD device structure
  2365. * @to: offset to write to
  2366. * @ops: oob operation description structure
  2367. */
  2368. static int nand_write_oob(struct mtd_info *mtd, loff_t to,
  2369. struct mtd_oob_ops *ops)
  2370. {
  2371. int ret = -ENOTSUPP;
  2372. ops->retlen = 0;
  2373. /* Do not allow writes past end of device */
  2374. if (ops->datbuf && (to + ops->len) > mtd->size) {
  2375. pr_debug("%s: attempt to write beyond end of device\n",
  2376. __func__);
  2377. return -EINVAL;
  2378. }
  2379. nand_get_device(mtd, FL_WRITING);
  2380. switch (ops->mode) {
  2381. case MTD_OPS_PLACE_OOB:
  2382. case MTD_OPS_AUTO_OOB:
  2383. case MTD_OPS_RAW:
  2384. break;
  2385. default:
  2386. goto out;
  2387. }
  2388. if (!ops->datbuf)
  2389. ret = nand_do_write_oob(mtd, to, ops);
  2390. else
  2391. ret = nand_do_write_ops(mtd, to, ops);
  2392. out:
  2393. nand_release_device(mtd);
  2394. return ret;
  2395. }
  2396. /**
  2397. * single_erase - [GENERIC] NAND standard block erase command function
  2398. * @mtd: MTD device structure
  2399. * @page: the page address of the block which will be erased
  2400. *
  2401. * Standard erase command for NAND chips. Returns NAND status.
  2402. */
  2403. static int single_erase(struct mtd_info *mtd, int page)
  2404. {
  2405. struct nand_chip *chip = mtd_to_nand(mtd);
  2406. /* Send commands to erase a block */
  2407. chip->cmdfunc(mtd, NAND_CMD_ERASE1, -1, page);
  2408. chip->cmdfunc(mtd, NAND_CMD_ERASE2, -1, -1);
  2409. return chip->waitfunc(mtd, chip);
  2410. }
  2411. /**
  2412. * nand_erase - [MTD Interface] erase block(s)
  2413. * @mtd: MTD device structure
  2414. * @instr: erase instruction
  2415. *
  2416. * Erase one ore more blocks.
  2417. */
  2418. static int nand_erase(struct mtd_info *mtd, struct erase_info *instr)
  2419. {
  2420. return nand_erase_nand(mtd, instr, 0);
  2421. }
  2422. /**
  2423. * nand_erase_nand - [INTERN] erase block(s)
  2424. * @mtd: MTD device structure
  2425. * @instr: erase instruction
  2426. * @allowbbt: allow erasing the bbt area
  2427. *
  2428. * Erase one ore more blocks.
  2429. */
  2430. int nand_erase_nand(struct mtd_info *mtd, struct erase_info *instr,
  2431. int allowbbt)
  2432. {
  2433. int page, status, pages_per_block, ret, chipnr;
  2434. struct nand_chip *chip = mtd_to_nand(mtd);
  2435. loff_t len;
  2436. pr_debug("%s: start = 0x%012llx, len = %llu\n",
  2437. __func__, (unsigned long long)instr->addr,
  2438. (unsigned long long)instr->len);
  2439. if (check_offs_len(mtd, instr->addr, instr->len))
  2440. return -EINVAL;
  2441. /* Grab the lock and see if the device is available */
  2442. nand_get_device(mtd, FL_ERASING);
  2443. /* Shift to get first page */
  2444. page = (int)(instr->addr >> chip->page_shift);
  2445. chipnr = (int)(instr->addr >> chip->chip_shift);
  2446. /* Calculate pages in each block */
  2447. pages_per_block = 1 << (chip->phys_erase_shift - chip->page_shift);
  2448. /* Select the NAND device */
  2449. chip->select_chip(mtd, chipnr);
  2450. /* Check, if it is write protected */
  2451. if (nand_check_wp(mtd)) {
  2452. pr_debug("%s: device is write protected!\n",
  2453. __func__);
  2454. instr->state = MTD_ERASE_FAILED;
  2455. goto erase_exit;
  2456. }
  2457. /* Loop through the pages */
  2458. len = instr->len;
  2459. instr->state = MTD_ERASING;
  2460. while (len) {
  2461. WATCHDOG_RESET();
  2462. /* Check if we have a bad block, we do not erase bad blocks! */
  2463. if (!instr->scrub && nand_block_checkbad(mtd, ((loff_t) page) <<
  2464. chip->page_shift, allowbbt)) {
  2465. pr_warn("%s: attempt to erase a bad block at page 0x%08x\n",
  2466. __func__, page);
  2467. instr->state = MTD_ERASE_FAILED;
  2468. goto erase_exit;
  2469. }
  2470. /*
  2471. * Invalidate the page cache, if we erase the block which
  2472. * contains the current cached page.
  2473. */
  2474. if (page <= chip->pagebuf && chip->pagebuf <
  2475. (page + pages_per_block))
  2476. chip->pagebuf = -1;
  2477. status = chip->erase(mtd, page & chip->pagemask);
  2478. /* See if block erase succeeded */
  2479. if (status & NAND_STATUS_FAIL) {
  2480. pr_debug("%s: failed erase, page 0x%08x\n",
  2481. __func__, page);
  2482. instr->state = MTD_ERASE_FAILED;
  2483. instr->fail_addr =
  2484. ((loff_t)page << chip->page_shift);
  2485. goto erase_exit;
  2486. }
  2487. /* Increment page address and decrement length */
  2488. len -= (1ULL << chip->phys_erase_shift);
  2489. page += pages_per_block;
  2490. /* Check, if we cross a chip boundary */
  2491. if (len && !(page & chip->pagemask)) {
  2492. chipnr++;
  2493. chip->select_chip(mtd, -1);
  2494. chip->select_chip(mtd, chipnr);
  2495. }
  2496. }
  2497. instr->state = MTD_ERASE_DONE;
  2498. erase_exit:
  2499. ret = instr->state == MTD_ERASE_DONE ? 0 : -EIO;
  2500. /* Deselect and wake up anyone waiting on the device */
  2501. chip->select_chip(mtd, -1);
  2502. nand_release_device(mtd);
  2503. /* Do call back function */
  2504. if (!ret)
  2505. mtd_erase_callback(instr);
  2506. /* Return more or less happy */
  2507. return ret;
  2508. }
  2509. /**
  2510. * nand_sync - [MTD Interface] sync
  2511. * @mtd: MTD device structure
  2512. *
  2513. * Sync is actually a wait for chip ready function.
  2514. */
  2515. static void nand_sync(struct mtd_info *mtd)
  2516. {
  2517. pr_debug("%s: called\n", __func__);
  2518. /* Grab the lock and see if the device is available */
  2519. nand_get_device(mtd, FL_SYNCING);
  2520. /* Release it and go back */
  2521. nand_release_device(mtd);
  2522. }
  2523. /**
  2524. * nand_block_isbad - [MTD Interface] Check if block at offset is bad
  2525. * @mtd: MTD device structure
  2526. * @offs: offset relative to mtd start
  2527. */
  2528. static int nand_block_isbad(struct mtd_info *mtd, loff_t offs)
  2529. {
  2530. struct nand_chip *chip = mtd_to_nand(mtd);
  2531. int chipnr = (int)(offs >> chip->chip_shift);
  2532. int ret;
  2533. /* Select the NAND device */
  2534. nand_get_device(mtd, FL_READING);
  2535. chip->select_chip(mtd, chipnr);
  2536. ret = nand_block_checkbad(mtd, offs, 0);
  2537. chip->select_chip(mtd, -1);
  2538. nand_release_device(mtd);
  2539. return ret;
  2540. }
  2541. /**
  2542. * nand_block_markbad - [MTD Interface] Mark block at the given offset as bad
  2543. * @mtd: MTD device structure
  2544. * @ofs: offset relative to mtd start
  2545. */
  2546. static int nand_block_markbad(struct mtd_info *mtd, loff_t ofs)
  2547. {
  2548. int ret;
  2549. ret = nand_block_isbad(mtd, ofs);
  2550. if (ret) {
  2551. /* If it was bad already, return success and do nothing */
  2552. if (ret > 0)
  2553. return 0;
  2554. return ret;
  2555. }
  2556. return nand_block_markbad_lowlevel(mtd, ofs);
  2557. }
  2558. /**
  2559. * nand_onfi_set_features- [REPLACEABLE] set features for ONFI nand
  2560. * @mtd: MTD device structure
  2561. * @chip: nand chip info structure
  2562. * @addr: feature address.
  2563. * @subfeature_param: the subfeature parameters, a four bytes array.
  2564. */
  2565. static int nand_onfi_set_features(struct mtd_info *mtd, struct nand_chip *chip,
  2566. int addr, uint8_t *subfeature_param)
  2567. {
  2568. int status;
  2569. int i;
  2570. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  2571. if (!chip->onfi_version ||
  2572. !(le16_to_cpu(chip->onfi_params.opt_cmd)
  2573. & ONFI_OPT_CMD_SET_GET_FEATURES))
  2574. return -ENOTSUPP;
  2575. #endif
  2576. chip->cmdfunc(mtd, NAND_CMD_SET_FEATURES, addr, -1);
  2577. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  2578. chip->write_byte(mtd, subfeature_param[i]);
  2579. status = chip->waitfunc(mtd, chip);
  2580. if (status & NAND_STATUS_FAIL)
  2581. return -EIO;
  2582. return 0;
  2583. }
  2584. /**
  2585. * nand_onfi_get_features- [REPLACEABLE] get features for ONFI nand
  2586. * @mtd: MTD device structure
  2587. * @chip: nand chip info structure
  2588. * @addr: feature address.
  2589. * @subfeature_param: the subfeature parameters, a four bytes array.
  2590. */
  2591. static int nand_onfi_get_features(struct mtd_info *mtd, struct nand_chip *chip,
  2592. int addr, uint8_t *subfeature_param)
  2593. {
  2594. int i;
  2595. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  2596. if (!chip->onfi_version ||
  2597. !(le16_to_cpu(chip->onfi_params.opt_cmd)
  2598. & ONFI_OPT_CMD_SET_GET_FEATURES))
  2599. return -ENOTSUPP;
  2600. #endif
  2601. chip->cmdfunc(mtd, NAND_CMD_GET_FEATURES, addr, -1);
  2602. for (i = 0; i < ONFI_SUBFEATURE_PARAM_LEN; ++i)
  2603. *subfeature_param++ = chip->read_byte(mtd);
  2604. return 0;
  2605. }
  2606. /* Set default functions */
  2607. static void nand_set_defaults(struct nand_chip *chip, int busw)
  2608. {
  2609. /* check for proper chip_delay setup, set 20us if not */
  2610. if (!chip->chip_delay)
  2611. chip->chip_delay = 20;
  2612. /* check, if a user supplied command function given */
  2613. if (chip->cmdfunc == NULL)
  2614. chip->cmdfunc = nand_command;
  2615. /* check, if a user supplied wait function given */
  2616. if (chip->waitfunc == NULL)
  2617. chip->waitfunc = nand_wait;
  2618. if (!chip->select_chip)
  2619. chip->select_chip = nand_select_chip;
  2620. /* set for ONFI nand */
  2621. if (!chip->onfi_set_features)
  2622. chip->onfi_set_features = nand_onfi_set_features;
  2623. if (!chip->onfi_get_features)
  2624. chip->onfi_get_features = nand_onfi_get_features;
  2625. /* If called twice, pointers that depend on busw may need to be reset */
  2626. if (!chip->read_byte || chip->read_byte == nand_read_byte)
  2627. chip->read_byte = busw ? nand_read_byte16 : nand_read_byte;
  2628. if (!chip->read_word)
  2629. chip->read_word = nand_read_word;
  2630. if (!chip->block_bad)
  2631. chip->block_bad = nand_block_bad;
  2632. if (!chip->block_markbad)
  2633. chip->block_markbad = nand_default_block_markbad;
  2634. if (!chip->write_buf || chip->write_buf == nand_write_buf)
  2635. chip->write_buf = busw ? nand_write_buf16 : nand_write_buf;
  2636. if (!chip->write_byte || chip->write_byte == nand_write_byte)
  2637. chip->write_byte = busw ? nand_write_byte16 : nand_write_byte;
  2638. if (!chip->read_buf || chip->read_buf == nand_read_buf)
  2639. chip->read_buf = busw ? nand_read_buf16 : nand_read_buf;
  2640. if (!chip->scan_bbt)
  2641. chip->scan_bbt = nand_default_bbt;
  2642. if (!chip->controller) {
  2643. chip->controller = &chip->hwcontrol;
  2644. spin_lock_init(&chip->controller->lock);
  2645. init_waitqueue_head(&chip->controller->wq);
  2646. }
  2647. if (!chip->buf_align)
  2648. chip->buf_align = 1;
  2649. }
  2650. /* Sanitize ONFI strings so we can safely print them */
  2651. static void sanitize_string(char *s, size_t len)
  2652. {
  2653. ssize_t i;
  2654. /* Null terminate */
  2655. s[len - 1] = 0;
  2656. /* Remove non printable chars */
  2657. for (i = 0; i < len - 1; i++) {
  2658. if (s[i] < ' ' || s[i] > 127)
  2659. s[i] = '?';
  2660. }
  2661. /* Remove trailing spaces */
  2662. strim(s);
  2663. }
  2664. static u16 onfi_crc16(u16 crc, u8 const *p, size_t len)
  2665. {
  2666. int i;
  2667. while (len--) {
  2668. crc ^= *p++ << 8;
  2669. for (i = 0; i < 8; i++)
  2670. crc = (crc << 1) ^ ((crc & 0x8000) ? 0x8005 : 0);
  2671. }
  2672. return crc;
  2673. }
  2674. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  2675. /* Parse the Extended Parameter Page. */
  2676. static int nand_flash_detect_ext_param_page(struct mtd_info *mtd,
  2677. struct nand_chip *chip, struct nand_onfi_params *p)
  2678. {
  2679. struct onfi_ext_param_page *ep;
  2680. struct onfi_ext_section *s;
  2681. struct onfi_ext_ecc_info *ecc;
  2682. uint8_t *cursor;
  2683. int ret = -EINVAL;
  2684. int len;
  2685. int i;
  2686. len = le16_to_cpu(p->ext_param_page_length) * 16;
  2687. ep = kmalloc(len, GFP_KERNEL);
  2688. if (!ep)
  2689. return -ENOMEM;
  2690. /* Send our own NAND_CMD_PARAM. */
  2691. chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
  2692. /* Use the Change Read Column command to skip the ONFI param pages. */
  2693. chip->cmdfunc(mtd, NAND_CMD_RNDOUT,
  2694. sizeof(*p) * p->num_of_param_pages , -1);
  2695. /* Read out the Extended Parameter Page. */
  2696. chip->read_buf(mtd, (uint8_t *)ep, len);
  2697. if ((onfi_crc16(ONFI_CRC_BASE, ((uint8_t *)ep) + 2, len - 2)
  2698. != le16_to_cpu(ep->crc))) {
  2699. pr_debug("fail in the CRC.\n");
  2700. goto ext_out;
  2701. }
  2702. /*
  2703. * Check the signature.
  2704. * Do not strictly follow the ONFI spec, maybe changed in future.
  2705. */
  2706. if (strncmp((char *)ep->sig, "EPPS", 4)) {
  2707. pr_debug("The signature is invalid.\n");
  2708. goto ext_out;
  2709. }
  2710. /* find the ECC section. */
  2711. cursor = (uint8_t *)(ep + 1);
  2712. for (i = 0; i < ONFI_EXT_SECTION_MAX; i++) {
  2713. s = ep->sections + i;
  2714. if (s->type == ONFI_SECTION_TYPE_2)
  2715. break;
  2716. cursor += s->length * 16;
  2717. }
  2718. if (i == ONFI_EXT_SECTION_MAX) {
  2719. pr_debug("We can not find the ECC section.\n");
  2720. goto ext_out;
  2721. }
  2722. /* get the info we want. */
  2723. ecc = (struct onfi_ext_ecc_info *)cursor;
  2724. if (!ecc->codeword_size) {
  2725. pr_debug("Invalid codeword size\n");
  2726. goto ext_out;
  2727. }
  2728. chip->ecc_strength_ds = ecc->ecc_bits;
  2729. chip->ecc_step_ds = 1 << ecc->codeword_size;
  2730. ret = 0;
  2731. ext_out:
  2732. kfree(ep);
  2733. return ret;
  2734. }
  2735. static int nand_setup_read_retry_micron(struct mtd_info *mtd, int retry_mode)
  2736. {
  2737. struct nand_chip *chip = mtd_to_nand(mtd);
  2738. uint8_t feature[ONFI_SUBFEATURE_PARAM_LEN] = {retry_mode};
  2739. return chip->onfi_set_features(mtd, chip, ONFI_FEATURE_ADDR_READ_RETRY,
  2740. feature);
  2741. }
  2742. /*
  2743. * Configure chip properties from Micron vendor-specific ONFI table
  2744. */
  2745. static void nand_onfi_detect_micron(struct nand_chip *chip,
  2746. struct nand_onfi_params *p)
  2747. {
  2748. struct nand_onfi_vendor_micron *micron = (void *)p->vendor;
  2749. if (le16_to_cpu(p->vendor_revision) < 1)
  2750. return;
  2751. chip->read_retries = micron->read_retry_options;
  2752. chip->setup_read_retry = nand_setup_read_retry_micron;
  2753. }
  2754. /*
  2755. * Check if the NAND chip is ONFI compliant, returns 1 if it is, 0 otherwise.
  2756. */
  2757. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  2758. int *busw)
  2759. {
  2760. struct nand_onfi_params *p = &chip->onfi_params;
  2761. int i, j;
  2762. int val;
  2763. /* Try ONFI for unknown chip or LP */
  2764. chip->cmdfunc(mtd, NAND_CMD_READID, 0x20, -1);
  2765. if (chip->read_byte(mtd) != 'O' || chip->read_byte(mtd) != 'N' ||
  2766. chip->read_byte(mtd) != 'F' || chip->read_byte(mtd) != 'I')
  2767. return 0;
  2768. chip->cmdfunc(mtd, NAND_CMD_PARAM, 0, -1);
  2769. for (i = 0; i < 3; i++) {
  2770. for (j = 0; j < sizeof(*p); j++)
  2771. ((uint8_t *)p)[j] = chip->read_byte(mtd);
  2772. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 254) ==
  2773. le16_to_cpu(p->crc)) {
  2774. break;
  2775. }
  2776. }
  2777. if (i == 3) {
  2778. pr_err("Could not find valid ONFI parameter page; aborting\n");
  2779. return 0;
  2780. }
  2781. /* Check version */
  2782. val = le16_to_cpu(p->revision);
  2783. if (val & (1 << 5))
  2784. chip->onfi_version = 23;
  2785. else if (val & (1 << 4))
  2786. chip->onfi_version = 22;
  2787. else if (val & (1 << 3))
  2788. chip->onfi_version = 21;
  2789. else if (val & (1 << 2))
  2790. chip->onfi_version = 20;
  2791. else if (val & (1 << 1))
  2792. chip->onfi_version = 10;
  2793. if (!chip->onfi_version) {
  2794. pr_info("unsupported ONFI version: %d\n", val);
  2795. return 0;
  2796. }
  2797. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  2798. sanitize_string(p->model, sizeof(p->model));
  2799. if (!mtd->name)
  2800. mtd->name = p->model;
  2801. mtd->writesize = le32_to_cpu(p->byte_per_page);
  2802. /*
  2803. * pages_per_block and blocks_per_lun may not be a power-of-2 size
  2804. * (don't ask me who thought of this...). MTD assumes that these
  2805. * dimensions will be power-of-2, so just truncate the remaining area.
  2806. */
  2807. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  2808. mtd->erasesize *= mtd->writesize;
  2809. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  2810. /* See erasesize comment */
  2811. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  2812. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  2813. chip->bits_per_cell = p->bits_per_cell;
  2814. if (onfi_feature(chip) & ONFI_FEATURE_16_BIT_BUS)
  2815. *busw = NAND_BUSWIDTH_16;
  2816. else
  2817. *busw = 0;
  2818. if (p->ecc_bits != 0xff) {
  2819. chip->ecc_strength_ds = p->ecc_bits;
  2820. chip->ecc_step_ds = 512;
  2821. } else if (chip->onfi_version >= 21 &&
  2822. (onfi_feature(chip) & ONFI_FEATURE_EXT_PARAM_PAGE)) {
  2823. /*
  2824. * The nand_flash_detect_ext_param_page() uses the
  2825. * Change Read Column command which maybe not supported
  2826. * by the chip->cmdfunc. So try to update the chip->cmdfunc
  2827. * now. We do not replace user supplied command function.
  2828. */
  2829. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  2830. chip->cmdfunc = nand_command_lp;
  2831. /* The Extended Parameter Page is supported since ONFI 2.1. */
  2832. if (nand_flash_detect_ext_param_page(mtd, chip, p))
  2833. pr_warn("Failed to detect ONFI extended param page\n");
  2834. } else {
  2835. pr_warn("Could not retrieve ONFI ECC requirements\n");
  2836. }
  2837. if (p->jedec_id == NAND_MFR_MICRON)
  2838. nand_onfi_detect_micron(chip, p);
  2839. return 1;
  2840. }
  2841. #else
  2842. static int nand_flash_detect_onfi(struct mtd_info *mtd, struct nand_chip *chip,
  2843. int *busw)
  2844. {
  2845. return 0;
  2846. }
  2847. #endif
  2848. /*
  2849. * Check if the NAND chip is JEDEC compliant, returns 1 if it is, 0 otherwise.
  2850. */
  2851. static int nand_flash_detect_jedec(struct mtd_info *mtd, struct nand_chip *chip,
  2852. int *busw)
  2853. {
  2854. struct nand_jedec_params *p = &chip->jedec_params;
  2855. struct jedec_ecc_info *ecc;
  2856. int val;
  2857. int i, j;
  2858. /* Try JEDEC for unknown chip or LP */
  2859. chip->cmdfunc(mtd, NAND_CMD_READID, 0x40, -1);
  2860. if (chip->read_byte(mtd) != 'J' || chip->read_byte(mtd) != 'E' ||
  2861. chip->read_byte(mtd) != 'D' || chip->read_byte(mtd) != 'E' ||
  2862. chip->read_byte(mtd) != 'C')
  2863. return 0;
  2864. chip->cmdfunc(mtd, NAND_CMD_PARAM, 0x40, -1);
  2865. for (i = 0; i < 3; i++) {
  2866. for (j = 0; j < sizeof(*p); j++)
  2867. ((uint8_t *)p)[j] = chip->read_byte(mtd);
  2868. if (onfi_crc16(ONFI_CRC_BASE, (uint8_t *)p, 510) ==
  2869. le16_to_cpu(p->crc))
  2870. break;
  2871. }
  2872. if (i == 3) {
  2873. pr_err("Could not find valid JEDEC parameter page; aborting\n");
  2874. return 0;
  2875. }
  2876. /* Check version */
  2877. val = le16_to_cpu(p->revision);
  2878. if (val & (1 << 2))
  2879. chip->jedec_version = 10;
  2880. else if (val & (1 << 1))
  2881. chip->jedec_version = 1; /* vendor specific version */
  2882. if (!chip->jedec_version) {
  2883. pr_info("unsupported JEDEC version: %d\n", val);
  2884. return 0;
  2885. }
  2886. sanitize_string(p->manufacturer, sizeof(p->manufacturer));
  2887. sanitize_string(p->model, sizeof(p->model));
  2888. if (!mtd->name)
  2889. mtd->name = p->model;
  2890. mtd->writesize = le32_to_cpu(p->byte_per_page);
  2891. /* Please reference to the comment for nand_flash_detect_onfi. */
  2892. mtd->erasesize = 1 << (fls(le32_to_cpu(p->pages_per_block)) - 1);
  2893. mtd->erasesize *= mtd->writesize;
  2894. mtd->oobsize = le16_to_cpu(p->spare_bytes_per_page);
  2895. /* Please reference to the comment for nand_flash_detect_onfi. */
  2896. chip->chipsize = 1 << (fls(le32_to_cpu(p->blocks_per_lun)) - 1);
  2897. chip->chipsize *= (uint64_t)mtd->erasesize * p->lun_count;
  2898. chip->bits_per_cell = p->bits_per_cell;
  2899. if (jedec_feature(chip) & JEDEC_FEATURE_16_BIT_BUS)
  2900. *busw = NAND_BUSWIDTH_16;
  2901. else
  2902. *busw = 0;
  2903. /* ECC info */
  2904. ecc = &p->ecc_info[0];
  2905. if (ecc->codeword_size >= 9) {
  2906. chip->ecc_strength_ds = ecc->ecc_bits;
  2907. chip->ecc_step_ds = 1 << ecc->codeword_size;
  2908. } else {
  2909. pr_warn("Invalid codeword size\n");
  2910. }
  2911. return 1;
  2912. }
  2913. /*
  2914. * nand_id_has_period - Check if an ID string has a given wraparound period
  2915. * @id_data: the ID string
  2916. * @arrlen: the length of the @id_data array
  2917. * @period: the period of repitition
  2918. *
  2919. * Check if an ID string is repeated within a given sequence of bytes at
  2920. * specific repetition interval period (e.g., {0x20,0x01,0x7F,0x20} has a
  2921. * period of 3). This is a helper function for nand_id_len(). Returns non-zero
  2922. * if the repetition has a period of @period; otherwise, returns zero.
  2923. */
  2924. static int nand_id_has_period(u8 *id_data, int arrlen, int period)
  2925. {
  2926. int i, j;
  2927. for (i = 0; i < period; i++)
  2928. for (j = i + period; j < arrlen; j += period)
  2929. if (id_data[i] != id_data[j])
  2930. return 0;
  2931. return 1;
  2932. }
  2933. /*
  2934. * nand_id_len - Get the length of an ID string returned by CMD_READID
  2935. * @id_data: the ID string
  2936. * @arrlen: the length of the @id_data array
  2937. * Returns the length of the ID string, according to known wraparound/trailing
  2938. * zero patterns. If no pattern exists, returns the length of the array.
  2939. */
  2940. static int nand_id_len(u8 *id_data, int arrlen)
  2941. {
  2942. int last_nonzero, period;
  2943. /* Find last non-zero byte */
  2944. for (last_nonzero = arrlen - 1; last_nonzero >= 0; last_nonzero--)
  2945. if (id_data[last_nonzero])
  2946. break;
  2947. /* All zeros */
  2948. if (last_nonzero < 0)
  2949. return 0;
  2950. /* Calculate wraparound period */
  2951. for (period = 1; period < arrlen; period++)
  2952. if (nand_id_has_period(id_data, arrlen, period))
  2953. break;
  2954. /* There's a repeated pattern */
  2955. if (period < arrlen)
  2956. return period;
  2957. /* There are trailing zeros */
  2958. if (last_nonzero < arrlen - 1)
  2959. return last_nonzero + 1;
  2960. /* No pattern detected */
  2961. return arrlen;
  2962. }
  2963. /* Extract the bits of per cell from the 3rd byte of the extended ID */
  2964. static int nand_get_bits_per_cell(u8 cellinfo)
  2965. {
  2966. int bits;
  2967. bits = cellinfo & NAND_CI_CELLTYPE_MSK;
  2968. bits >>= NAND_CI_CELLTYPE_SHIFT;
  2969. return bits + 1;
  2970. }
  2971. /*
  2972. * Many new NAND share similar device ID codes, which represent the size of the
  2973. * chip. The rest of the parameters must be decoded according to generic or
  2974. * manufacturer-specific "extended ID" decoding patterns.
  2975. */
  2976. static void nand_decode_ext_id(struct mtd_info *mtd, struct nand_chip *chip,
  2977. u8 id_data[8], int *busw)
  2978. {
  2979. int extid, id_len;
  2980. /* The 3rd id byte holds MLC / multichip data */
  2981. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  2982. /* The 4th id byte is the important one */
  2983. extid = id_data[3];
  2984. id_len = nand_id_len(id_data, 8);
  2985. /*
  2986. * Field definitions are in the following datasheets:
  2987. * Old style (4,5 byte ID): Samsung K9GAG08U0M (p.32)
  2988. * New Samsung (6 byte ID): Samsung K9GAG08U0F (p.44)
  2989. * Hynix MLC (6 byte ID): Hynix H27UBG8T2B (p.22)
  2990. *
  2991. * Check for ID length, non-zero 6th byte, cell type, and Hynix/Samsung
  2992. * ID to decide what to do.
  2993. */
  2994. if (id_len == 6 && id_data[0] == NAND_MFR_SAMSUNG &&
  2995. !nand_is_slc(chip) && id_data[5] != 0x00) {
  2996. /* Calc pagesize */
  2997. mtd->writesize = 2048 << (extid & 0x03);
  2998. extid >>= 2;
  2999. /* Calc oobsize */
  3000. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  3001. case 1:
  3002. mtd->oobsize = 128;
  3003. break;
  3004. case 2:
  3005. mtd->oobsize = 218;
  3006. break;
  3007. case 3:
  3008. mtd->oobsize = 400;
  3009. break;
  3010. case 4:
  3011. mtd->oobsize = 436;
  3012. break;
  3013. case 5:
  3014. mtd->oobsize = 512;
  3015. break;
  3016. case 6:
  3017. mtd->oobsize = 640;
  3018. break;
  3019. case 7:
  3020. default: /* Other cases are "reserved" (unknown) */
  3021. mtd->oobsize = 1024;
  3022. break;
  3023. }
  3024. extid >>= 2;
  3025. /* Calc blocksize */
  3026. mtd->erasesize = (128 * 1024) <<
  3027. (((extid >> 1) & 0x04) | (extid & 0x03));
  3028. *busw = 0;
  3029. } else if (id_len == 6 && id_data[0] == NAND_MFR_HYNIX &&
  3030. !nand_is_slc(chip)) {
  3031. unsigned int tmp;
  3032. /* Calc pagesize */
  3033. mtd->writesize = 2048 << (extid & 0x03);
  3034. extid >>= 2;
  3035. /* Calc oobsize */
  3036. switch (((extid >> 2) & 0x04) | (extid & 0x03)) {
  3037. case 0:
  3038. mtd->oobsize = 128;
  3039. break;
  3040. case 1:
  3041. mtd->oobsize = 224;
  3042. break;
  3043. case 2:
  3044. mtd->oobsize = 448;
  3045. break;
  3046. case 3:
  3047. mtd->oobsize = 64;
  3048. break;
  3049. case 4:
  3050. mtd->oobsize = 32;
  3051. break;
  3052. case 5:
  3053. mtd->oobsize = 16;
  3054. break;
  3055. default:
  3056. mtd->oobsize = 640;
  3057. break;
  3058. }
  3059. extid >>= 2;
  3060. /* Calc blocksize */
  3061. tmp = ((extid >> 1) & 0x04) | (extid & 0x03);
  3062. if (tmp < 0x03)
  3063. mtd->erasesize = (128 * 1024) << tmp;
  3064. else if (tmp == 0x03)
  3065. mtd->erasesize = 768 * 1024;
  3066. else
  3067. mtd->erasesize = (64 * 1024) << tmp;
  3068. *busw = 0;
  3069. } else {
  3070. /* Calc pagesize */
  3071. mtd->writesize = 1024 << (extid & 0x03);
  3072. extid >>= 2;
  3073. /* Calc oobsize */
  3074. mtd->oobsize = (8 << (extid & 0x01)) *
  3075. (mtd->writesize >> 9);
  3076. extid >>= 2;
  3077. /* Calc blocksize. Blocksize is multiples of 64KiB */
  3078. mtd->erasesize = (64 * 1024) << (extid & 0x03);
  3079. extid >>= 2;
  3080. /* Get buswidth information */
  3081. *busw = (extid & 0x01) ? NAND_BUSWIDTH_16 : 0;
  3082. /*
  3083. * Toshiba 24nm raw SLC (i.e., not BENAND) have 32B OOB per
  3084. * 512B page. For Toshiba SLC, we decode the 5th/6th byte as
  3085. * follows:
  3086. * - ID byte 6, bits[2:0]: 100b -> 43nm, 101b -> 32nm,
  3087. * 110b -> 24nm
  3088. * - ID byte 5, bit[7]: 1 -> BENAND, 0 -> raw SLC
  3089. */
  3090. if (id_len >= 6 && id_data[0] == NAND_MFR_TOSHIBA &&
  3091. nand_is_slc(chip) &&
  3092. (id_data[5] & 0x7) == 0x6 /* 24nm */ &&
  3093. !(id_data[4] & 0x80) /* !BENAND */) {
  3094. mtd->oobsize = 32 * mtd->writesize >> 9;
  3095. }
  3096. }
  3097. }
  3098. /*
  3099. * Old devices have chip data hardcoded in the device ID table. nand_decode_id
  3100. * decodes a matching ID table entry and assigns the MTD size parameters for
  3101. * the chip.
  3102. */
  3103. static void nand_decode_id(struct mtd_info *mtd, struct nand_chip *chip,
  3104. struct nand_flash_dev *type, u8 id_data[8],
  3105. int *busw)
  3106. {
  3107. int maf_id = id_data[0];
  3108. mtd->erasesize = type->erasesize;
  3109. mtd->writesize = type->pagesize;
  3110. mtd->oobsize = mtd->writesize / 32;
  3111. *busw = type->options & NAND_BUSWIDTH_16;
  3112. /* All legacy ID NAND are small-page, SLC */
  3113. chip->bits_per_cell = 1;
  3114. /*
  3115. * Check for Spansion/AMD ID + repeating 5th, 6th byte since
  3116. * some Spansion chips have erasesize that conflicts with size
  3117. * listed in nand_ids table.
  3118. * Data sheet (5 byte ID): Spansion S30ML-P ORNAND (p.39)
  3119. */
  3120. if (maf_id == NAND_MFR_AMD && id_data[4] != 0x00 && id_data[5] == 0x00
  3121. && id_data[6] == 0x00 && id_data[7] == 0x00
  3122. && mtd->writesize == 512) {
  3123. mtd->erasesize = 128 * 1024;
  3124. mtd->erasesize <<= ((id_data[3] & 0x03) << 1);
  3125. }
  3126. }
  3127. /*
  3128. * Set the bad block marker/indicator (BBM/BBI) patterns according to some
  3129. * heuristic patterns using various detected parameters (e.g., manufacturer,
  3130. * page size, cell-type information).
  3131. */
  3132. static void nand_decode_bbm_options(struct mtd_info *mtd,
  3133. struct nand_chip *chip, u8 id_data[8])
  3134. {
  3135. int maf_id = id_data[0];
  3136. /* Set the bad block position */
  3137. if (mtd->writesize > 512 || (chip->options & NAND_BUSWIDTH_16))
  3138. chip->badblockpos = NAND_LARGE_BADBLOCK_POS;
  3139. else
  3140. chip->badblockpos = NAND_SMALL_BADBLOCK_POS;
  3141. /*
  3142. * Bad block marker is stored in the last page of each block on Samsung
  3143. * and Hynix MLC devices; stored in first two pages of each block on
  3144. * Micron devices with 2KiB pages and on SLC Samsung, Hynix, Toshiba,
  3145. * AMD/Spansion, and Macronix. All others scan only the first page.
  3146. */
  3147. if (!nand_is_slc(chip) &&
  3148. (maf_id == NAND_MFR_SAMSUNG ||
  3149. maf_id == NAND_MFR_HYNIX))
  3150. chip->bbt_options |= NAND_BBT_SCANLASTPAGE;
  3151. else if ((nand_is_slc(chip) &&
  3152. (maf_id == NAND_MFR_SAMSUNG ||
  3153. maf_id == NAND_MFR_HYNIX ||
  3154. maf_id == NAND_MFR_TOSHIBA ||
  3155. maf_id == NAND_MFR_AMD ||
  3156. maf_id == NAND_MFR_MACRONIX)) ||
  3157. (mtd->writesize == 2048 &&
  3158. maf_id == NAND_MFR_MICRON))
  3159. chip->bbt_options |= NAND_BBT_SCAN2NDPAGE;
  3160. }
  3161. static inline bool is_full_id_nand(struct nand_flash_dev *type)
  3162. {
  3163. return type->id_len;
  3164. }
  3165. static bool find_full_id_nand(struct mtd_info *mtd, struct nand_chip *chip,
  3166. struct nand_flash_dev *type, u8 *id_data, int *busw)
  3167. {
  3168. if (!strncmp((char *)type->id, (char *)id_data, type->id_len)) {
  3169. mtd->writesize = type->pagesize;
  3170. mtd->erasesize = type->erasesize;
  3171. mtd->oobsize = type->oobsize;
  3172. chip->bits_per_cell = nand_get_bits_per_cell(id_data[2]);
  3173. chip->chipsize = (uint64_t)type->chipsize << 20;
  3174. chip->options |= type->options;
  3175. chip->ecc_strength_ds = NAND_ECC_STRENGTH(type);
  3176. chip->ecc_step_ds = NAND_ECC_STEP(type);
  3177. chip->onfi_timing_mode_default =
  3178. type->onfi_timing_mode_default;
  3179. *busw = type->options & NAND_BUSWIDTH_16;
  3180. if (!mtd->name)
  3181. mtd->name = type->name;
  3182. return true;
  3183. }
  3184. return false;
  3185. }
  3186. /*
  3187. * Get the flash and manufacturer id and lookup if the type is supported.
  3188. */
  3189. struct nand_flash_dev *nand_get_flash_type(struct mtd_info *mtd,
  3190. struct nand_chip *chip,
  3191. int *maf_id, int *dev_id,
  3192. struct nand_flash_dev *type)
  3193. {
  3194. int busw;
  3195. int i, maf_idx;
  3196. u8 id_data[8];
  3197. /*
  3198. * Reset the chip, required by some chips (e.g. Micron MT29FxGxxxxx)
  3199. * after power-up.
  3200. */
  3201. nand_reset(chip, 0);
  3202. /* Select the device */
  3203. chip->select_chip(mtd, 0);
  3204. /* Send the command for reading device ID */
  3205. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  3206. /* Read manufacturer and device IDs */
  3207. *maf_id = chip->read_byte(mtd);
  3208. *dev_id = chip->read_byte(mtd);
  3209. /*
  3210. * Try again to make sure, as some systems the bus-hold or other
  3211. * interface concerns can cause random data which looks like a
  3212. * possibly credible NAND flash to appear. If the two results do
  3213. * not match, ignore the device completely.
  3214. */
  3215. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  3216. /* Read entire ID string */
  3217. for (i = 0; i < 8; i++)
  3218. id_data[i] = chip->read_byte(mtd);
  3219. if (id_data[0] != *maf_id || id_data[1] != *dev_id) {
  3220. pr_info("second ID read did not match %02x,%02x against %02x,%02x\n",
  3221. *maf_id, *dev_id, id_data[0], id_data[1]);
  3222. return ERR_PTR(-ENODEV);
  3223. }
  3224. if (!type)
  3225. type = nand_flash_ids;
  3226. for (; type->name != NULL; type++) {
  3227. if (is_full_id_nand(type)) {
  3228. if (find_full_id_nand(mtd, chip, type, id_data, &busw))
  3229. goto ident_done;
  3230. } else if (*dev_id == type->dev_id) {
  3231. break;
  3232. }
  3233. }
  3234. chip->onfi_version = 0;
  3235. if (!type->name || !type->pagesize) {
  3236. /* Check if the chip is ONFI compliant */
  3237. if (nand_flash_detect_onfi(mtd, chip, &busw))
  3238. goto ident_done;
  3239. /* Check if the chip is JEDEC compliant */
  3240. if (nand_flash_detect_jedec(mtd, chip, &busw))
  3241. goto ident_done;
  3242. }
  3243. if (!type->name)
  3244. return ERR_PTR(-ENODEV);
  3245. if (!mtd->name)
  3246. mtd->name = type->name;
  3247. chip->chipsize = (uint64_t)type->chipsize << 20;
  3248. if (!type->pagesize) {
  3249. /* Decode parameters from extended ID */
  3250. nand_decode_ext_id(mtd, chip, id_data, &busw);
  3251. } else {
  3252. nand_decode_id(mtd, chip, type, id_data, &busw);
  3253. }
  3254. /* Get chip options */
  3255. chip->options |= type->options;
  3256. /*
  3257. * Check if chip is not a Samsung device. Do not clear the
  3258. * options for chips which do not have an extended id.
  3259. */
  3260. if (*maf_id != NAND_MFR_SAMSUNG && !type->pagesize)
  3261. chip->options &= ~NAND_SAMSUNG_LP_OPTIONS;
  3262. ident_done:
  3263. /* Try to identify manufacturer */
  3264. for (maf_idx = 0; nand_manuf_ids[maf_idx].id != 0x0; maf_idx++) {
  3265. if (nand_manuf_ids[maf_idx].id == *maf_id)
  3266. break;
  3267. }
  3268. if (chip->options & NAND_BUSWIDTH_AUTO) {
  3269. WARN_ON(chip->options & NAND_BUSWIDTH_16);
  3270. chip->options |= busw;
  3271. nand_set_defaults(chip, busw);
  3272. } else if (busw != (chip->options & NAND_BUSWIDTH_16)) {
  3273. /*
  3274. * Check, if buswidth is correct. Hardware drivers should set
  3275. * chip correct!
  3276. */
  3277. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  3278. *maf_id, *dev_id);
  3279. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name, mtd->name);
  3280. pr_warn("bus width %d instead %d bit\n",
  3281. (chip->options & NAND_BUSWIDTH_16) ? 16 : 8,
  3282. busw ? 16 : 8);
  3283. return ERR_PTR(-EINVAL);
  3284. }
  3285. nand_decode_bbm_options(mtd, chip, id_data);
  3286. /* Calculate the address shift from the page size */
  3287. chip->page_shift = ffs(mtd->writesize) - 1;
  3288. /* Convert chipsize to number of pages per chip -1 */
  3289. chip->pagemask = (chip->chipsize >> chip->page_shift) - 1;
  3290. chip->bbt_erase_shift = chip->phys_erase_shift =
  3291. ffs(mtd->erasesize) - 1;
  3292. if (chip->chipsize & 0xffffffff)
  3293. chip->chip_shift = ffs((unsigned)chip->chipsize) - 1;
  3294. else {
  3295. chip->chip_shift = ffs((unsigned)(chip->chipsize >> 32));
  3296. chip->chip_shift += 32 - 1;
  3297. }
  3298. if (chip->chip_shift - chip->page_shift > 16)
  3299. chip->options |= NAND_ROW_ADDR_3;
  3300. chip->badblockbits = 8;
  3301. chip->erase = single_erase;
  3302. /* Do not replace user supplied command function! */
  3303. if (mtd->writesize > 512 && chip->cmdfunc == nand_command)
  3304. chip->cmdfunc = nand_command_lp;
  3305. pr_info("device found, Manufacturer ID: 0x%02x, Chip ID: 0x%02x\n",
  3306. *maf_id, *dev_id);
  3307. #ifdef CONFIG_SYS_NAND_ONFI_DETECTION
  3308. if (chip->onfi_version)
  3309. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3310. chip->onfi_params.model);
  3311. else if (chip->jedec_version)
  3312. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3313. chip->jedec_params.model);
  3314. else
  3315. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3316. type->name);
  3317. #else
  3318. if (chip->jedec_version)
  3319. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3320. chip->jedec_params.model);
  3321. else
  3322. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3323. type->name);
  3324. pr_info("%s %s\n", nand_manuf_ids[maf_idx].name,
  3325. type->name);
  3326. #endif
  3327. pr_info("%d MiB, %s, erase size: %d KiB, page size: %d, OOB size: %d\n",
  3328. (int)(chip->chipsize >> 20), nand_is_slc(chip) ? "SLC" : "MLC",
  3329. mtd->erasesize >> 10, mtd->writesize, mtd->oobsize);
  3330. return type;
  3331. }
  3332. EXPORT_SYMBOL(nand_get_flash_type);
  3333. #if CONFIG_IS_ENABLED(OF_CONTROL)
  3334. DECLARE_GLOBAL_DATA_PTR;
  3335. static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
  3336. {
  3337. int ret, ecc_mode = -1, ecc_strength, ecc_step;
  3338. const void *blob = gd->fdt_blob;
  3339. const char *str;
  3340. ret = fdtdec_get_int(blob, node, "nand-bus-width", -1);
  3341. if (ret == 16)
  3342. chip->options |= NAND_BUSWIDTH_16;
  3343. if (fdtdec_get_bool(blob, node, "nand-on-flash-bbt"))
  3344. chip->bbt_options |= NAND_BBT_USE_FLASH;
  3345. str = fdt_getprop(blob, node, "nand-ecc-mode", NULL);
  3346. if (str) {
  3347. if (!strcmp(str, "none"))
  3348. ecc_mode = NAND_ECC_NONE;
  3349. else if (!strcmp(str, "soft"))
  3350. ecc_mode = NAND_ECC_SOFT;
  3351. else if (!strcmp(str, "hw"))
  3352. ecc_mode = NAND_ECC_HW;
  3353. else if (!strcmp(str, "hw_syndrome"))
  3354. ecc_mode = NAND_ECC_HW_SYNDROME;
  3355. else if (!strcmp(str, "hw_oob_first"))
  3356. ecc_mode = NAND_ECC_HW_OOB_FIRST;
  3357. else if (!strcmp(str, "soft_bch"))
  3358. ecc_mode = NAND_ECC_SOFT_BCH;
  3359. }
  3360. ecc_strength = fdtdec_get_int(blob, node, "nand-ecc-strength", -1);
  3361. ecc_step = fdtdec_get_int(blob, node, "nand-ecc-step-size", -1);
  3362. if ((ecc_step >= 0 && !(ecc_strength >= 0)) ||
  3363. (!(ecc_step >= 0) && ecc_strength >= 0)) {
  3364. pr_err("must set both strength and step size in DT\n");
  3365. return -EINVAL;
  3366. }
  3367. if (ecc_mode >= 0)
  3368. chip->ecc.mode = ecc_mode;
  3369. if (ecc_strength >= 0)
  3370. chip->ecc.strength = ecc_strength;
  3371. if (ecc_step > 0)
  3372. chip->ecc.size = ecc_step;
  3373. if (fdt_getprop(blob, node, "nand-ecc-maximize", NULL))
  3374. chip->ecc.options |= NAND_ECC_MAXIMIZE;
  3375. return 0;
  3376. }
  3377. #else
  3378. static int nand_dt_init(struct mtd_info *mtd, struct nand_chip *chip, int node)
  3379. {
  3380. return 0;
  3381. }
  3382. #endif /* CONFIG_IS_ENABLED(OF_CONTROL) */
  3383. /**
  3384. * nand_scan_ident - [NAND Interface] Scan for the NAND device
  3385. * @mtd: MTD device structure
  3386. * @maxchips: number of chips to scan for
  3387. * @table: alternative NAND ID table
  3388. *
  3389. * This is the first phase of the normal nand_scan() function. It reads the
  3390. * flash ID and sets up MTD fields accordingly.
  3391. *
  3392. */
  3393. int nand_scan_ident(struct mtd_info *mtd, int maxchips,
  3394. struct nand_flash_dev *table)
  3395. {
  3396. int i, nand_maf_id, nand_dev_id;
  3397. struct nand_chip *chip = mtd_to_nand(mtd);
  3398. struct nand_flash_dev *type;
  3399. int ret;
  3400. if (chip->flash_node) {
  3401. ret = nand_dt_init(mtd, chip, chip->flash_node);
  3402. if (ret)
  3403. return ret;
  3404. }
  3405. /* Set the default functions */
  3406. nand_set_defaults(chip, chip->options & NAND_BUSWIDTH_16);
  3407. /* Read the flash type */
  3408. type = nand_get_flash_type(mtd, chip, &nand_maf_id,
  3409. &nand_dev_id, table);
  3410. if (IS_ERR(type)) {
  3411. if (!(chip->options & NAND_SCAN_SILENT_NODEV))
  3412. pr_warn("No NAND device found\n");
  3413. chip->select_chip(mtd, -1);
  3414. return PTR_ERR(type);
  3415. }
  3416. /* Initialize the ->data_interface field. */
  3417. ret = nand_init_data_interface(chip);
  3418. if (ret)
  3419. return ret;
  3420. /*
  3421. * Setup the data interface correctly on the chip and controller side.
  3422. * This explicit call to nand_setup_data_interface() is only required
  3423. * for the first die, because nand_reset() has been called before
  3424. * ->data_interface and ->default_onfi_timing_mode were set.
  3425. * For the other dies, nand_reset() will automatically switch to the
  3426. * best mode for us.
  3427. */
  3428. ret = nand_setup_data_interface(chip, 0);
  3429. if (ret)
  3430. return ret;
  3431. chip->select_chip(mtd, -1);
  3432. /* Check for a chip array */
  3433. for (i = 1; i < maxchips; i++) {
  3434. /* See comment in nand_get_flash_type for reset */
  3435. nand_reset(chip, i);
  3436. chip->select_chip(mtd, i);
  3437. /* Send the command for reading device ID */
  3438. chip->cmdfunc(mtd, NAND_CMD_READID, 0x00, -1);
  3439. /* Read manufacturer and device IDs */
  3440. if (nand_maf_id != chip->read_byte(mtd) ||
  3441. nand_dev_id != chip->read_byte(mtd)) {
  3442. chip->select_chip(mtd, -1);
  3443. break;
  3444. }
  3445. chip->select_chip(mtd, -1);
  3446. }
  3447. #ifdef DEBUG
  3448. if (i > 1)
  3449. pr_info("%d chips detected\n", i);
  3450. #endif
  3451. /* Store the number of chips and calc total size for mtd */
  3452. chip->numchips = i;
  3453. mtd->size = i * chip->chipsize;
  3454. return 0;
  3455. }
  3456. EXPORT_SYMBOL(nand_scan_ident);
  3457. /**
  3458. * nand_check_ecc_caps - check the sanity of preset ECC settings
  3459. * @chip: nand chip info structure
  3460. * @caps: ECC caps info structure
  3461. * @oobavail: OOB size that the ECC engine can use
  3462. *
  3463. * When ECC step size and strength are already set, check if they are supported
  3464. * by the controller and the calculated ECC bytes fit within the chip's OOB.
  3465. * On success, the calculated ECC bytes is set.
  3466. */
  3467. int nand_check_ecc_caps(struct nand_chip *chip,
  3468. const struct nand_ecc_caps *caps, int oobavail)
  3469. {
  3470. struct mtd_info *mtd = nand_to_mtd(chip);
  3471. const struct nand_ecc_step_info *stepinfo;
  3472. int preset_step = chip->ecc.size;
  3473. int preset_strength = chip->ecc.strength;
  3474. int nsteps, ecc_bytes;
  3475. int i, j;
  3476. if (WARN_ON(oobavail < 0))
  3477. return -EINVAL;
  3478. if (!preset_step || !preset_strength)
  3479. return -ENODATA;
  3480. nsteps = mtd->writesize / preset_step;
  3481. for (i = 0; i < caps->nstepinfos; i++) {
  3482. stepinfo = &caps->stepinfos[i];
  3483. if (stepinfo->stepsize != preset_step)
  3484. continue;
  3485. for (j = 0; j < stepinfo->nstrengths; j++) {
  3486. if (stepinfo->strengths[j] != preset_strength)
  3487. continue;
  3488. ecc_bytes = caps->calc_ecc_bytes(preset_step,
  3489. preset_strength);
  3490. if (WARN_ON_ONCE(ecc_bytes < 0))
  3491. return ecc_bytes;
  3492. if (ecc_bytes * nsteps > oobavail) {
  3493. pr_err("ECC (step, strength) = (%d, %d) does not fit in OOB",
  3494. preset_step, preset_strength);
  3495. return -ENOSPC;
  3496. }
  3497. chip->ecc.bytes = ecc_bytes;
  3498. return 0;
  3499. }
  3500. }
  3501. pr_err("ECC (step, strength) = (%d, %d) not supported on this controller",
  3502. preset_step, preset_strength);
  3503. return -ENOTSUPP;
  3504. }
  3505. EXPORT_SYMBOL_GPL(nand_check_ecc_caps);
  3506. /**
  3507. * nand_match_ecc_req - meet the chip's requirement with least ECC bytes
  3508. * @chip: nand chip info structure
  3509. * @caps: ECC engine caps info structure
  3510. * @oobavail: OOB size that the ECC engine can use
  3511. *
  3512. * If a chip's ECC requirement is provided, try to meet it with the least
  3513. * number of ECC bytes (i.e. with the largest number of OOB-free bytes).
  3514. * On success, the chosen ECC settings are set.
  3515. */
  3516. int nand_match_ecc_req(struct nand_chip *chip,
  3517. const struct nand_ecc_caps *caps, int oobavail)
  3518. {
  3519. struct mtd_info *mtd = nand_to_mtd(chip);
  3520. const struct nand_ecc_step_info *stepinfo;
  3521. int req_step = chip->ecc_step_ds;
  3522. int req_strength = chip->ecc_strength_ds;
  3523. int req_corr, step_size, strength, nsteps, ecc_bytes, ecc_bytes_total;
  3524. int best_step, best_strength, best_ecc_bytes;
  3525. int best_ecc_bytes_total = INT_MAX;
  3526. int i, j;
  3527. if (WARN_ON(oobavail < 0))
  3528. return -EINVAL;
  3529. /* No information provided by the NAND chip */
  3530. if (!req_step || !req_strength)
  3531. return -ENOTSUPP;
  3532. /* number of correctable bits the chip requires in a page */
  3533. req_corr = mtd->writesize / req_step * req_strength;
  3534. for (i = 0; i < caps->nstepinfos; i++) {
  3535. stepinfo = &caps->stepinfos[i];
  3536. step_size = stepinfo->stepsize;
  3537. for (j = 0; j < stepinfo->nstrengths; j++) {
  3538. strength = stepinfo->strengths[j];
  3539. /*
  3540. * If both step size and strength are smaller than the
  3541. * chip's requirement, it is not easy to compare the
  3542. * resulted reliability.
  3543. */
  3544. if (step_size < req_step && strength < req_strength)
  3545. continue;
  3546. if (mtd->writesize % step_size)
  3547. continue;
  3548. nsteps = mtd->writesize / step_size;
  3549. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  3550. if (WARN_ON_ONCE(ecc_bytes < 0))
  3551. continue;
  3552. ecc_bytes_total = ecc_bytes * nsteps;
  3553. if (ecc_bytes_total > oobavail ||
  3554. strength * nsteps < req_corr)
  3555. continue;
  3556. /*
  3557. * We assume the best is to meet the chip's requrement
  3558. * with the least number of ECC bytes.
  3559. */
  3560. if (ecc_bytes_total < best_ecc_bytes_total) {
  3561. best_ecc_bytes_total = ecc_bytes_total;
  3562. best_step = step_size;
  3563. best_strength = strength;
  3564. best_ecc_bytes = ecc_bytes;
  3565. }
  3566. }
  3567. }
  3568. if (best_ecc_bytes_total == INT_MAX)
  3569. return -ENOTSUPP;
  3570. chip->ecc.size = best_step;
  3571. chip->ecc.strength = best_strength;
  3572. chip->ecc.bytes = best_ecc_bytes;
  3573. return 0;
  3574. }
  3575. EXPORT_SYMBOL_GPL(nand_match_ecc_req);
  3576. /**
  3577. * nand_maximize_ecc - choose the max ECC strength available
  3578. * @chip: nand chip info structure
  3579. * @caps: ECC engine caps info structure
  3580. * @oobavail: OOB size that the ECC engine can use
  3581. *
  3582. * Choose the max ECC strength that is supported on the controller, and can fit
  3583. * within the chip's OOB. On success, the chosen ECC settings are set.
  3584. */
  3585. int nand_maximize_ecc(struct nand_chip *chip,
  3586. const struct nand_ecc_caps *caps, int oobavail)
  3587. {
  3588. struct mtd_info *mtd = nand_to_mtd(chip);
  3589. const struct nand_ecc_step_info *stepinfo;
  3590. int step_size, strength, nsteps, ecc_bytes, corr;
  3591. int best_corr = 0;
  3592. int best_step = 0;
  3593. int best_strength, best_ecc_bytes;
  3594. int i, j;
  3595. if (WARN_ON(oobavail < 0))
  3596. return -EINVAL;
  3597. for (i = 0; i < caps->nstepinfos; i++) {
  3598. stepinfo = &caps->stepinfos[i];
  3599. step_size = stepinfo->stepsize;
  3600. /* If chip->ecc.size is already set, respect it */
  3601. if (chip->ecc.size && step_size != chip->ecc.size)
  3602. continue;
  3603. for (j = 0; j < stepinfo->nstrengths; j++) {
  3604. strength = stepinfo->strengths[j];
  3605. if (mtd->writesize % step_size)
  3606. continue;
  3607. nsteps = mtd->writesize / step_size;
  3608. ecc_bytes = caps->calc_ecc_bytes(step_size, strength);
  3609. if (WARN_ON_ONCE(ecc_bytes < 0))
  3610. continue;
  3611. if (ecc_bytes * nsteps > oobavail)
  3612. continue;
  3613. corr = strength * nsteps;
  3614. /*
  3615. * If the number of correctable bits is the same,
  3616. * bigger step_size has more reliability.
  3617. */
  3618. if (corr > best_corr ||
  3619. (corr == best_corr && step_size > best_step)) {
  3620. best_corr = corr;
  3621. best_step = step_size;
  3622. best_strength = strength;
  3623. best_ecc_bytes = ecc_bytes;
  3624. }
  3625. }
  3626. }
  3627. if (!best_corr)
  3628. return -ENOTSUPP;
  3629. chip->ecc.size = best_step;
  3630. chip->ecc.strength = best_strength;
  3631. chip->ecc.bytes = best_ecc_bytes;
  3632. return 0;
  3633. }
  3634. EXPORT_SYMBOL_GPL(nand_maximize_ecc);
  3635. /*
  3636. * Check if the chip configuration meet the datasheet requirements.
  3637. * If our configuration corrects A bits per B bytes and the minimum
  3638. * required correction level is X bits per Y bytes, then we must ensure
  3639. * both of the following are true:
  3640. *
  3641. * (1) A / B >= X / Y
  3642. * (2) A >= X
  3643. *
  3644. * Requirement (1) ensures we can correct for the required bitflip density.
  3645. * Requirement (2) ensures we can correct even when all bitflips are clumped
  3646. * in the same sector.
  3647. */
  3648. static bool nand_ecc_strength_good(struct mtd_info *mtd)
  3649. {
  3650. struct nand_chip *chip = mtd_to_nand(mtd);
  3651. struct nand_ecc_ctrl *ecc = &chip->ecc;
  3652. int corr, ds_corr;
  3653. if (ecc->size == 0 || chip->ecc_step_ds == 0)
  3654. /* Not enough information */
  3655. return true;
  3656. /*
  3657. * We get the number of corrected bits per page to compare
  3658. * the correction density.
  3659. */
  3660. corr = (mtd->writesize * ecc->strength) / ecc->size;
  3661. ds_corr = (mtd->writesize * chip->ecc_strength_ds) / chip->ecc_step_ds;
  3662. return corr >= ds_corr && ecc->strength >= chip->ecc_strength_ds;
  3663. }
  3664. static bool invalid_ecc_page_accessors(struct nand_chip *chip)
  3665. {
  3666. struct nand_ecc_ctrl *ecc = &chip->ecc;
  3667. if (nand_standard_page_accessors(ecc))
  3668. return false;
  3669. /*
  3670. * NAND_ECC_CUSTOM_PAGE_ACCESS flag is set, make sure the NAND
  3671. * controller driver implements all the page accessors because
  3672. * default helpers are not suitable when the core does not
  3673. * send the READ0/PAGEPROG commands.
  3674. */
  3675. return (!ecc->read_page || !ecc->write_page ||
  3676. !ecc->read_page_raw || !ecc->write_page_raw ||
  3677. (NAND_HAS_SUBPAGE_READ(chip) && !ecc->read_subpage) ||
  3678. (NAND_HAS_SUBPAGE_WRITE(chip) && !ecc->write_subpage &&
  3679. ecc->hwctl && ecc->calculate));
  3680. }
  3681. /**
  3682. * nand_scan_tail - [NAND Interface] Scan for the NAND device
  3683. * @mtd: MTD device structure
  3684. *
  3685. * This is the second phase of the normal nand_scan() function. It fills out
  3686. * all the uninitialized function pointers with the defaults and scans for a
  3687. * bad block table if appropriate.
  3688. */
  3689. int nand_scan_tail(struct mtd_info *mtd)
  3690. {
  3691. int i;
  3692. struct nand_chip *chip = mtd_to_nand(mtd);
  3693. struct nand_ecc_ctrl *ecc = &chip->ecc;
  3694. struct nand_buffers *nbuf;
  3695. /* New bad blocks should be marked in OOB, flash-based BBT, or both */
  3696. BUG_ON((chip->bbt_options & NAND_BBT_NO_OOB_BBM) &&
  3697. !(chip->bbt_options & NAND_BBT_USE_FLASH));
  3698. if (invalid_ecc_page_accessors(chip)) {
  3699. pr_err("Invalid ECC page accessors setup\n");
  3700. return -EINVAL;
  3701. }
  3702. if (!(chip->options & NAND_OWN_BUFFERS)) {
  3703. nbuf = kzalloc(sizeof(struct nand_buffers), GFP_KERNEL);
  3704. chip->buffers = nbuf;
  3705. } else {
  3706. if (!chip->buffers)
  3707. return -ENOMEM;
  3708. }
  3709. /* Set the internal oob buffer location, just after the page data */
  3710. chip->oob_poi = chip->buffers->databuf + mtd->writesize;
  3711. /*
  3712. * If no default placement scheme is given, select an appropriate one.
  3713. */
  3714. if (!ecc->layout && (ecc->mode != NAND_ECC_SOFT_BCH)) {
  3715. switch (mtd->oobsize) {
  3716. case 8:
  3717. ecc->layout = &nand_oob_8;
  3718. break;
  3719. case 16:
  3720. ecc->layout = &nand_oob_16;
  3721. break;
  3722. case 64:
  3723. ecc->layout = &nand_oob_64;
  3724. break;
  3725. case 128:
  3726. ecc->layout = &nand_oob_128;
  3727. break;
  3728. default:
  3729. pr_warn("No oob scheme defined for oobsize %d\n",
  3730. mtd->oobsize);
  3731. BUG();
  3732. }
  3733. }
  3734. if (!chip->write_page)
  3735. chip->write_page = nand_write_page;
  3736. /*
  3737. * Check ECC mode, default to software if 3byte/512byte hardware ECC is
  3738. * selected and we have 256 byte pagesize fallback to software ECC
  3739. */
  3740. switch (ecc->mode) {
  3741. case NAND_ECC_HW_OOB_FIRST:
  3742. /* Similar to NAND_ECC_HW, but a separate read_page handle */
  3743. if (!ecc->calculate || !ecc->correct || !ecc->hwctl) {
  3744. pr_warn("No ECC functions supplied; hardware ECC not possible\n");
  3745. BUG();
  3746. }
  3747. if (!ecc->read_page)
  3748. ecc->read_page = nand_read_page_hwecc_oob_first;
  3749. case NAND_ECC_HW:
  3750. /* Use standard hwecc read page function? */
  3751. if (!ecc->read_page)
  3752. ecc->read_page = nand_read_page_hwecc;
  3753. if (!ecc->write_page)
  3754. ecc->write_page = nand_write_page_hwecc;
  3755. if (!ecc->read_page_raw)
  3756. ecc->read_page_raw = nand_read_page_raw;
  3757. if (!ecc->write_page_raw)
  3758. ecc->write_page_raw = nand_write_page_raw;
  3759. if (!ecc->read_oob)
  3760. ecc->read_oob = nand_read_oob_std;
  3761. if (!ecc->write_oob)
  3762. ecc->write_oob = nand_write_oob_std;
  3763. if (!ecc->read_subpage)
  3764. ecc->read_subpage = nand_read_subpage;
  3765. if (!ecc->write_subpage && ecc->hwctl && ecc->calculate)
  3766. ecc->write_subpage = nand_write_subpage_hwecc;
  3767. case NAND_ECC_HW_SYNDROME:
  3768. if ((!ecc->calculate || !ecc->correct || !ecc->hwctl) &&
  3769. (!ecc->read_page ||
  3770. ecc->read_page == nand_read_page_hwecc ||
  3771. !ecc->write_page ||
  3772. ecc->write_page == nand_write_page_hwecc)) {
  3773. pr_warn("No ECC functions supplied; hardware ECC not possible\n");
  3774. BUG();
  3775. }
  3776. /* Use standard syndrome read/write page function? */
  3777. if (!ecc->read_page)
  3778. ecc->read_page = nand_read_page_syndrome;
  3779. if (!ecc->write_page)
  3780. ecc->write_page = nand_write_page_syndrome;
  3781. if (!ecc->read_page_raw)
  3782. ecc->read_page_raw = nand_read_page_raw_syndrome;
  3783. if (!ecc->write_page_raw)
  3784. ecc->write_page_raw = nand_write_page_raw_syndrome;
  3785. if (!ecc->read_oob)
  3786. ecc->read_oob = nand_read_oob_syndrome;
  3787. if (!ecc->write_oob)
  3788. ecc->write_oob = nand_write_oob_syndrome;
  3789. if (mtd->writesize >= ecc->size) {
  3790. if (!ecc->strength) {
  3791. pr_warn("Driver must set ecc.strength when using hardware ECC\n");
  3792. BUG();
  3793. }
  3794. break;
  3795. }
  3796. pr_warn("%d byte HW ECC not possible on %d byte page size, fallback to SW ECC\n",
  3797. ecc->size, mtd->writesize);
  3798. ecc->mode = NAND_ECC_SOFT;
  3799. case NAND_ECC_SOFT:
  3800. ecc->calculate = nand_calculate_ecc;
  3801. ecc->correct = nand_correct_data;
  3802. ecc->read_page = nand_read_page_swecc;
  3803. ecc->read_subpage = nand_read_subpage;
  3804. ecc->write_page = nand_write_page_swecc;
  3805. ecc->read_page_raw = nand_read_page_raw;
  3806. ecc->write_page_raw = nand_write_page_raw;
  3807. ecc->read_oob = nand_read_oob_std;
  3808. ecc->write_oob = nand_write_oob_std;
  3809. if (!ecc->size)
  3810. ecc->size = 256;
  3811. ecc->bytes = 3;
  3812. ecc->strength = 1;
  3813. break;
  3814. case NAND_ECC_SOFT_BCH:
  3815. if (!mtd_nand_has_bch()) {
  3816. pr_warn("CONFIG_MTD_NAND_ECC_BCH not enabled\n");
  3817. BUG();
  3818. }
  3819. ecc->calculate = nand_bch_calculate_ecc;
  3820. ecc->correct = nand_bch_correct_data;
  3821. ecc->read_page = nand_read_page_swecc;
  3822. ecc->read_subpage = nand_read_subpage;
  3823. ecc->write_page = nand_write_page_swecc;
  3824. ecc->read_page_raw = nand_read_page_raw;
  3825. ecc->write_page_raw = nand_write_page_raw;
  3826. ecc->read_oob = nand_read_oob_std;
  3827. ecc->write_oob = nand_write_oob_std;
  3828. /*
  3829. * Board driver should supply ecc.size and ecc.strength values
  3830. * to select how many bits are correctable. Otherwise, default
  3831. * to 4 bits for large page devices.
  3832. */
  3833. if (!ecc->size && (mtd->oobsize >= 64)) {
  3834. ecc->size = 512;
  3835. ecc->strength = 4;
  3836. }
  3837. /* See nand_bch_init() for details. */
  3838. ecc->bytes = 0;
  3839. ecc->priv = nand_bch_init(mtd);
  3840. if (!ecc->priv) {
  3841. pr_warn("BCH ECC initialization failed!\n");
  3842. BUG();
  3843. }
  3844. break;
  3845. case NAND_ECC_NONE:
  3846. pr_warn("NAND_ECC_NONE selected by board driver. This is not recommended!\n");
  3847. ecc->read_page = nand_read_page_raw;
  3848. ecc->write_page = nand_write_page_raw;
  3849. ecc->read_oob = nand_read_oob_std;
  3850. ecc->read_page_raw = nand_read_page_raw;
  3851. ecc->write_page_raw = nand_write_page_raw;
  3852. ecc->write_oob = nand_write_oob_std;
  3853. ecc->size = mtd->writesize;
  3854. ecc->bytes = 0;
  3855. ecc->strength = 0;
  3856. break;
  3857. default:
  3858. pr_warn("Invalid NAND_ECC_MODE %d\n", ecc->mode);
  3859. BUG();
  3860. }
  3861. /* For many systems, the standard OOB write also works for raw */
  3862. if (!ecc->read_oob_raw)
  3863. ecc->read_oob_raw = ecc->read_oob;
  3864. if (!ecc->write_oob_raw)
  3865. ecc->write_oob_raw = ecc->write_oob;
  3866. /*
  3867. * The number of bytes available for a client to place data into
  3868. * the out of band area.
  3869. */
  3870. mtd->oobavail = 0;
  3871. if (ecc->layout) {
  3872. for (i = 0; ecc->layout->oobfree[i].length; i++)
  3873. mtd->oobavail += ecc->layout->oobfree[i].length;
  3874. }
  3875. /* ECC sanity check: warn if it's too weak */
  3876. if (!nand_ecc_strength_good(mtd))
  3877. pr_warn("WARNING: %s: the ECC used on your system is too weak compared to the one required by the NAND chip\n",
  3878. mtd->name);
  3879. /*
  3880. * Set the number of read / write steps for one page depending on ECC
  3881. * mode.
  3882. */
  3883. ecc->steps = mtd->writesize / ecc->size;
  3884. if (ecc->steps * ecc->size != mtd->writesize) {
  3885. pr_warn("Invalid ECC parameters\n");
  3886. BUG();
  3887. }
  3888. ecc->total = ecc->steps * ecc->bytes;
  3889. /* Allow subpage writes up to ecc.steps. Not possible for MLC flash */
  3890. if (!(chip->options & NAND_NO_SUBPAGE_WRITE) && nand_is_slc(chip)) {
  3891. switch (ecc->steps) {
  3892. case 2:
  3893. mtd->subpage_sft = 1;
  3894. break;
  3895. case 4:
  3896. case 8:
  3897. case 16:
  3898. mtd->subpage_sft = 2;
  3899. break;
  3900. }
  3901. }
  3902. chip->subpagesize = mtd->writesize >> mtd->subpage_sft;
  3903. /* Initialize state */
  3904. chip->state = FL_READY;
  3905. /* Invalidate the pagebuffer reference */
  3906. chip->pagebuf = -1;
  3907. /* Large page NAND with SOFT_ECC should support subpage reads */
  3908. switch (ecc->mode) {
  3909. case NAND_ECC_SOFT:
  3910. case NAND_ECC_SOFT_BCH:
  3911. if (chip->page_shift > 9)
  3912. chip->options |= NAND_SUBPAGE_READ;
  3913. break;
  3914. default:
  3915. break;
  3916. }
  3917. /* Fill in remaining MTD driver data */
  3918. mtd->type = nand_is_slc(chip) ? MTD_NANDFLASH : MTD_MLCNANDFLASH;
  3919. mtd->flags = (chip->options & NAND_ROM) ? MTD_CAP_ROM :
  3920. MTD_CAP_NANDFLASH;
  3921. mtd->_erase = nand_erase;
  3922. mtd->_panic_write = panic_nand_write;
  3923. mtd->_read_oob = nand_read_oob;
  3924. mtd->_write_oob = nand_write_oob;
  3925. mtd->_sync = nand_sync;
  3926. mtd->_lock = NULL;
  3927. mtd->_unlock = NULL;
  3928. mtd->_block_isreserved = nand_block_isreserved;
  3929. mtd->_block_isbad = nand_block_isbad;
  3930. mtd->_block_markbad = nand_block_markbad;
  3931. mtd->writebufsize = mtd->writesize;
  3932. /* propagate ecc info to mtd_info */
  3933. mtd->ecclayout = ecc->layout;
  3934. mtd->ecc_strength = ecc->strength;
  3935. mtd->ecc_step_size = ecc->size;
  3936. /*
  3937. * Initialize bitflip_threshold to its default prior scan_bbt() call.
  3938. * scan_bbt() might invoke mtd_read(), thus bitflip_threshold must be
  3939. * properly set.
  3940. */
  3941. if (!mtd->bitflip_threshold)
  3942. mtd->bitflip_threshold = DIV_ROUND_UP(mtd->ecc_strength * 3, 4);
  3943. return 0;
  3944. }
  3945. EXPORT_SYMBOL(nand_scan_tail);
  3946. /**
  3947. * nand_scan - [NAND Interface] Scan for the NAND device
  3948. * @mtd: MTD device structure
  3949. * @maxchips: number of chips to scan for
  3950. *
  3951. * This fills out all the uninitialized function pointers with the defaults.
  3952. * The flash ID is read and the mtd/chip structures are filled with the
  3953. * appropriate values.
  3954. */
  3955. int nand_scan(struct mtd_info *mtd, int maxchips)
  3956. {
  3957. int ret;
  3958. ret = nand_scan_ident(mtd, maxchips, NULL);
  3959. if (!ret)
  3960. ret = nand_scan_tail(mtd);
  3961. return ret;
  3962. }
  3963. EXPORT_SYMBOL(nand_scan);
  3964. MODULE_LICENSE("GPL");
  3965. MODULE_AUTHOR("Steven J. Hill <sjhill@realitydiluted.com>");
  3966. MODULE_AUTHOR("Thomas Gleixner <tglx@linutronix.de>");
  3967. MODULE_DESCRIPTION("Generic NAND flash driver code");