lpc32xx_nand_mlc.c 23 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /*
  3. * LPC32xx MLC NAND flash controller driver
  4. *
  5. * (C) Copyright 2014 3ADEV <http://3adev.com>
  6. * Written by Albert ARIBAUD <albert.aribaud@3adev.fr>
  7. *
  8. * NOTE:
  9. *
  10. * The MLC NAND flash controller provides hardware Reed-Solomon ECC
  11. * covering in- and out-of-band data together. Therefore, in- and out-
  12. * of-band data must be written together in order to have a valid ECC.
  13. *
  14. * Consequently, pages with meaningful in-band data are written with
  15. * blank (all-ones) out-of-band data and a valid ECC, and any later
  16. * out-of-band data write will void the ECC.
  17. *
  18. * Therefore, code which reads such late-written out-of-band data
  19. * should not rely on the ECC validity.
  20. */
  21. #include <common.h>
  22. #include <nand.h>
  23. #include <linux/errno.h>
  24. #include <asm/io.h>
  25. #include <nand.h>
  26. #include <asm/arch/clk.h>
  27. #include <asm/arch/sys_proto.h>
  28. /*
  29. * MLC NAND controller registers.
  30. */
  31. struct lpc32xx_nand_mlc_registers {
  32. u8 buff[32768]; /* controller's serial data buffer */
  33. u8 data[32768]; /* NAND's raw data buffer */
  34. u32 cmd;
  35. u32 addr;
  36. u32 ecc_enc_reg;
  37. u32 ecc_dec_reg;
  38. u32 ecc_auto_enc_reg;
  39. u32 ecc_auto_dec_reg;
  40. u32 rpr;
  41. u32 wpr;
  42. u32 rubp;
  43. u32 robp;
  44. u32 sw_wp_add_low;
  45. u32 sw_wp_add_hig;
  46. u32 icr;
  47. u32 time_reg;
  48. u32 irq_mr;
  49. u32 irq_sr;
  50. u32 lock_pr;
  51. u32 isr;
  52. u32 ceh;
  53. };
  54. /* LOCK_PR register defines */
  55. #define LOCK_PR_UNLOCK_KEY 0x0000A25E /* Magic unlock value */
  56. /* ICR defines */
  57. #define ICR_LARGE_BLOCKS 0x00000004 /* configure for 2KB blocks */
  58. #define ICR_ADDR4 0x00000002 /* configure for 4-word addrs */
  59. /* CEH defines */
  60. #define CEH_NORMAL_CE 0x00000001 /* do not force CE ON */
  61. /* ISR register defines */
  62. #define ISR_NAND_READY 0x00000001
  63. #define ISR_CONTROLLER_READY 0x00000002
  64. #define ISR_ECC_READY 0x00000004
  65. #define ISR_DECODER_ERRORS(s) ((((s) >> 4) & 3)+1)
  66. #define ISR_DECODER_FAILURE 0x00000040
  67. #define ISR_DECODER_ERROR 0x00000008
  68. /* time-out for NAND chip / controller loops, in us */
  69. #define LPC32X_NAND_TIMEOUT 5000
  70. /*
  71. * There is a single instance of the NAND MLC controller
  72. */
  73. static struct lpc32xx_nand_mlc_registers __iomem *lpc32xx_nand_mlc_registers
  74. = (struct lpc32xx_nand_mlc_registers __iomem *)MLC_NAND_BASE;
  75. #define clkdiv(v, w, o) (((1+(clk/v)) & w) << o)
  76. /**
  77. * OOB data in each small page are 6 'free' then 10 ECC bytes.
  78. * To make things easier, when reading large pages, the four pages'
  79. * 'free' OOB bytes are grouped in the first 24 bytes of the OOB buffer,
  80. * while the the four ECC bytes are groupe in its last 40 bytes.
  81. *
  82. * The struct below represents how free vs ecc oob bytes are stored
  83. * in the buffer.
  84. *
  85. * Note: the OOB bytes contain the bad block marker at offsets 0 and 1.
  86. */
  87. struct lpc32xx_oob {
  88. struct {
  89. uint8_t free_oob_bytes[6];
  90. } free[4];
  91. struct {
  92. uint8_t ecc_oob_bytes[10];
  93. } ecc[4];
  94. };
  95. /*
  96. * Initialize the controller
  97. */
  98. static void lpc32xx_nand_init(void)
  99. {
  100. unsigned int clk;
  101. /* Configure controller for no software write protection, x8 bus
  102. width, large block device, and 4 address words */
  103. /* unlock controller registers with magic key */
  104. writel(LOCK_PR_UNLOCK_KEY,
  105. &lpc32xx_nand_mlc_registers->lock_pr);
  106. /* enable large blocks and large NANDs */
  107. writel(ICR_LARGE_BLOCKS | ICR_ADDR4,
  108. &lpc32xx_nand_mlc_registers->icr);
  109. /* Make sure MLC interrupts are disabled */
  110. writel(0, &lpc32xx_nand_mlc_registers->irq_mr);
  111. /* Normal chip enable operation */
  112. writel(CEH_NORMAL_CE,
  113. &lpc32xx_nand_mlc_registers->ceh);
  114. /* Setup NAND timing */
  115. clk = get_hclk_clk_rate();
  116. writel(
  117. clkdiv(CONFIG_LPC32XX_NAND_MLC_TCEA_DELAY, 0x03, 24) |
  118. clkdiv(CONFIG_LPC32XX_NAND_MLC_BUSY_DELAY, 0x1F, 19) |
  119. clkdiv(CONFIG_LPC32XX_NAND_MLC_NAND_TA, 0x07, 16) |
  120. clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_HIGH, 0x0F, 12) |
  121. clkdiv(CONFIG_LPC32XX_NAND_MLC_RD_LOW, 0x0F, 8) |
  122. clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_HIGH, 0x0F, 4) |
  123. clkdiv(CONFIG_LPC32XX_NAND_MLC_WR_LOW, 0x0F, 0),
  124. &lpc32xx_nand_mlc_registers->time_reg);
  125. }
  126. #if !defined(CONFIG_SPL_BUILD)
  127. /**
  128. * lpc32xx_cmd_ctrl - write command to either cmd or data register
  129. */
  130. static void lpc32xx_cmd_ctrl(struct mtd_info *mtd, int cmd,
  131. unsigned int ctrl)
  132. {
  133. if (cmd == NAND_CMD_NONE)
  134. return;
  135. if (ctrl & NAND_CLE)
  136. writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->cmd);
  137. else if (ctrl & NAND_ALE)
  138. writeb(cmd & 0Xff, &lpc32xx_nand_mlc_registers->addr);
  139. }
  140. /**
  141. * lpc32xx_read_byte - read a byte from the NAND
  142. * @mtd: MTD device structure
  143. */
  144. static uint8_t lpc32xx_read_byte(struct mtd_info *mtd)
  145. {
  146. return readb(&lpc32xx_nand_mlc_registers->data);
  147. }
  148. /**
  149. * lpc32xx_dev_ready - test if NAND device (actually controller) is ready
  150. * @mtd: MTD device structure
  151. * @mode: mode to set the ECC HW to.
  152. */
  153. static int lpc32xx_dev_ready(struct mtd_info *mtd)
  154. {
  155. /* means *controller* ready for us */
  156. int status = readl(&lpc32xx_nand_mlc_registers->isr);
  157. return status & ISR_CONTROLLER_READY;
  158. }
  159. /**
  160. * ECC layout -- this is needed whatever ECC mode we are using.
  161. * In a 2KB (4*512B) page, R/S codes occupy 40 (4*10) bytes.
  162. * To make U-Boot's life easier, we pack 'useable' OOB at the
  163. * front and R/S ECC at the back.
  164. */
  165. static struct nand_ecclayout lpc32xx_largepage_ecclayout = {
  166. .eccbytes = 40,
  167. .eccpos = {24, 25, 26, 27, 28, 29, 30, 31, 32, 33,
  168. 34, 35, 36, 37, 38, 39, 40, 41, 42, 43,
  169. 44, 45, 46, 47, 48, 48, 50, 51, 52, 53,
  170. 54, 55, 56, 57, 58, 59, 60, 61, 62, 63,
  171. },
  172. .oobfree = {
  173. /* bytes 0 and 1 are used for the bad block marker */
  174. {
  175. .offset = 2,
  176. .length = 22
  177. },
  178. }
  179. };
  180. /**
  181. * lpc32xx_read_page_hwecc - read in- and out-of-band data with ECC
  182. * @mtd: mtd info structure
  183. * @chip: nand chip info structure
  184. * @buf: buffer to store read data
  185. * @oob_required: caller requires OOB data read to chip->oob_poi
  186. * @page: page number to read
  187. *
  188. * Use large block Auto Decode Read Mode(1) as described in User Manual
  189. * section 8.6.2.1.
  190. *
  191. * The initial Read Mode and Read Start commands are sent by the caller.
  192. *
  193. * ECC will be false if out-of-band data has been updated since in-band
  194. * data was initially written.
  195. */
  196. static int lpc32xx_read_page_hwecc(struct mtd_info *mtd,
  197. struct nand_chip *chip, uint8_t *buf, int oob_required,
  198. int page)
  199. {
  200. unsigned int i, status, timeout, err, max_bitflips = 0;
  201. struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
  202. /* go through all four small pages */
  203. for (i = 0; i < 4; i++) {
  204. /* start auto decode (reads 528 NAND bytes) */
  205. writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
  206. /* wait for controller to return to ready state */
  207. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  208. status = readl(&lpc32xx_nand_mlc_registers->isr);
  209. if (status & ISR_CONTROLLER_READY)
  210. break;
  211. udelay(1);
  212. }
  213. /* if decoder failed, return failure */
  214. if (status & ISR_DECODER_FAILURE)
  215. return -1;
  216. /* keep count of maximum bitflips performed */
  217. if (status & ISR_DECODER_ERROR) {
  218. err = ISR_DECODER_ERRORS(status);
  219. if (err > max_bitflips)
  220. max_bitflips = err;
  221. }
  222. /* copy first 512 bytes into buffer */
  223. memcpy(buf+512*i, lpc32xx_nand_mlc_registers->buff, 512);
  224. /* copy next 6 bytes at front of OOB buffer */
  225. memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
  226. /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
  227. memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
  228. }
  229. return max_bitflips;
  230. }
  231. /**
  232. * lpc32xx_read_page_raw - read raw (in-band, out-of-band and ECC) data
  233. * @mtd: mtd info structure
  234. * @chip: nand chip info structure
  235. * @buf: buffer to store read data
  236. * @oob_required: caller requires OOB data read to chip->oob_poi
  237. * @page: page number to read
  238. *
  239. * Read NAND directly; can read pages with invalid ECC.
  240. */
  241. static int lpc32xx_read_page_raw(struct mtd_info *mtd,
  242. struct nand_chip *chip, uint8_t *buf, int oob_required,
  243. int page)
  244. {
  245. unsigned int i, status, timeout;
  246. struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
  247. /* when we get here we've already had the Read Mode(1) */
  248. /* go through all four small pages */
  249. for (i = 0; i < 4; i++) {
  250. /* wait for NAND to return to ready state */
  251. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  252. status = readl(&lpc32xx_nand_mlc_registers->isr);
  253. if (status & ISR_NAND_READY)
  254. break;
  255. udelay(1);
  256. }
  257. /* if NAND stalled, return failure */
  258. if (!(status & ISR_NAND_READY))
  259. return -1;
  260. /* copy first 512 bytes into buffer */
  261. memcpy(buf+512*i, lpc32xx_nand_mlc_registers->data, 512);
  262. /* copy next 6 bytes at front of OOB buffer */
  263. memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->data, 6);
  264. /* copy last 10 bytes (R/S ECC) at back of OOB buffer */
  265. memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->data, 10);
  266. }
  267. return 0;
  268. }
  269. /**
  270. * lpc32xx_read_oob - read out-of-band data
  271. * @mtd: mtd info structure
  272. * @chip: nand chip info structure
  273. * @page: page number to read
  274. *
  275. * Read out-of-band data. User Manual section 8.6.4 suggests using Read
  276. * Mode(3) which the controller will turn into a Read Mode(1) internally
  277. * but nand_base.c will turn Mode(3) into Mode(0), so let's use Mode(0)
  278. * directly.
  279. *
  280. * ECC covers in- and out-of-band data and was written when out-of-band
  281. * data was blank. Therefore, if the out-of-band being read here is not
  282. * blank, then the ECC will be false and the read will return bitflips,
  283. * even in case of ECC failure where we will return 5 bitflips. The
  284. * caller should be prepared to handle this.
  285. */
  286. static int lpc32xx_read_oob(struct mtd_info *mtd, struct nand_chip *chip,
  287. int page)
  288. {
  289. unsigned int i, status, timeout, err, max_bitflips = 0;
  290. struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
  291. /* No command was sent before calling read_oob() so send one */
  292. chip->cmdfunc(mtd, NAND_CMD_READ0, 0, page);
  293. /* go through all four small pages */
  294. for (i = 0; i < 4; i++) {
  295. /* start auto decode (reads 528 NAND bytes) */
  296. writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
  297. /* wait for controller to return to ready state */
  298. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  299. status = readl(&lpc32xx_nand_mlc_registers->isr);
  300. if (status & ISR_CONTROLLER_READY)
  301. break;
  302. udelay(1);
  303. }
  304. /* if decoder failure, count 'one too many' bitflips */
  305. if (status & ISR_DECODER_FAILURE)
  306. max_bitflips = 5;
  307. /* keep count of maximum bitflips performed */
  308. if (status & ISR_DECODER_ERROR) {
  309. err = ISR_DECODER_ERRORS(status);
  310. if (err > max_bitflips)
  311. max_bitflips = err;
  312. }
  313. /* set read pointer to OOB area */
  314. writel(0, &lpc32xx_nand_mlc_registers->robp);
  315. /* copy next 6 bytes at front of OOB buffer */
  316. memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
  317. /* copy next 10 bytes (R/S ECC) at back of OOB buffer */
  318. memcpy(&oob->ecc[i], lpc32xx_nand_mlc_registers->buff, 10);
  319. }
  320. return max_bitflips;
  321. }
  322. /**
  323. * lpc32xx_write_page_hwecc - write in- and out-of-band data with ECC
  324. * @mtd: mtd info structure
  325. * @chip: nand chip info structure
  326. * @buf: data buffer
  327. * @oob_required: must write chip->oob_poi to OOB
  328. *
  329. * Use large block Auto Encode as per User Manual section 8.6.4.
  330. *
  331. * The initial Write Serial Input and final Auto Program commands are
  332. * sent by the caller.
  333. */
  334. static int lpc32xx_write_page_hwecc(struct mtd_info *mtd,
  335. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  336. int page)
  337. {
  338. unsigned int i, status, timeout;
  339. struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
  340. /* when we get here we've already had the SEQIN */
  341. for (i = 0; i < 4; i++) {
  342. /* start encode (expects 518 writes to buff) */
  343. writel(0, &lpc32xx_nand_mlc_registers->ecc_enc_reg);
  344. /* copy first 512 bytes from buffer */
  345. memcpy(&lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
  346. /* copy next 6 bytes from OOB buffer -- excluding ECC */
  347. memcpy(&lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
  348. /* wait for ECC to return to ready state */
  349. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  350. status = readl(&lpc32xx_nand_mlc_registers->isr);
  351. if (status & ISR_ECC_READY)
  352. break;
  353. udelay(1);
  354. }
  355. /* if ECC stalled, return failure */
  356. if (!(status & ISR_ECC_READY))
  357. return -1;
  358. /* Trigger auto encode (writes 528 bytes to NAND) */
  359. writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_enc_reg);
  360. /* wait for controller to return to ready state */
  361. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  362. status = readl(&lpc32xx_nand_mlc_registers->isr);
  363. if (status & ISR_CONTROLLER_READY)
  364. break;
  365. udelay(1);
  366. }
  367. /* if controller stalled, return error */
  368. if (!(status & ISR_CONTROLLER_READY))
  369. return -1;
  370. }
  371. return 0;
  372. }
  373. /**
  374. * lpc32xx_write_page_raw - write raw (in-band, out-of-band and ECC) data
  375. * @mtd: mtd info structure
  376. * @chip: nand chip info structure
  377. * @buf: buffer to store read data
  378. * @oob_required: caller requires OOB data read to chip->oob_poi
  379. * @page: page number to read
  380. *
  381. * Use large block write but without encode.
  382. *
  383. * The initial Write Serial Input and final Auto Program commands are
  384. * sent by the caller.
  385. *
  386. * This function will write the full out-of-band data, including the
  387. * ECC area. Therefore, it can write pages with valid *or* invalid ECC.
  388. */
  389. static int lpc32xx_write_page_raw(struct mtd_info *mtd,
  390. struct nand_chip *chip, const uint8_t *buf, int oob_required,
  391. int page)
  392. {
  393. unsigned int i;
  394. struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
  395. /* when we get here we've already had the Read Mode(1) */
  396. for (i = 0; i < 4; i++) {
  397. /* copy first 512 bytes from buffer */
  398. memcpy(lpc32xx_nand_mlc_registers->buff, buf+512*i, 512);
  399. /* copy next 6 bytes into OOB buffer -- excluding ECC */
  400. memcpy(lpc32xx_nand_mlc_registers->buff, &oob->free[i], 6);
  401. /* copy next 10 bytes into OOB buffer -- that is 'ECC' */
  402. memcpy(lpc32xx_nand_mlc_registers->buff, &oob->ecc[i], 10);
  403. }
  404. return 0;
  405. }
  406. /**
  407. * lpc32xx_write_oob - write out-of-band data
  408. * @mtd: mtd info structure
  409. * @chip: nand chip info structure
  410. * @page: page number to read
  411. *
  412. * Since ECC covers in- and out-of-band data, writing out-of-band data
  413. * with ECC will render the page ECC wrong -- or, if the page was blank,
  414. * then it will produce a good ECC but a later in-band data write will
  415. * render it wrong.
  416. *
  417. * Therefore, do not compute or write any ECC, and always return success.
  418. *
  419. * This implies that we do four writes, since non-ECC out-of-band data
  420. * are not contiguous in a large page.
  421. */
  422. static int lpc32xx_write_oob(struct mtd_info *mtd, struct nand_chip *chip,
  423. int page)
  424. {
  425. /* update oob on all 4 subpages in sequence */
  426. unsigned int i, status, timeout;
  427. struct lpc32xx_oob *oob = (struct lpc32xx_oob *)chip->oob_poi;
  428. for (i = 0; i < 4; i++) {
  429. /* start data input */
  430. chip->cmdfunc(mtd, NAND_CMD_SEQIN, 0x200+0x210*i, page);
  431. /* copy 6 non-ECC out-of-band bytes directly into NAND */
  432. memcpy(lpc32xx_nand_mlc_registers->data, &oob->free[i], 6);
  433. /* program page */
  434. chip->cmdfunc(mtd, NAND_CMD_PAGEPROG, -1, -1);
  435. /* wait for NAND to return to ready state */
  436. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  437. status = readl(&lpc32xx_nand_mlc_registers->isr);
  438. if (status & ISR_NAND_READY)
  439. break;
  440. udelay(1);
  441. }
  442. /* if NAND stalled, return error */
  443. if (!(status & ISR_NAND_READY))
  444. return -1;
  445. }
  446. return 0;
  447. }
  448. /**
  449. * lpc32xx_waitfunc - wait until a command is done
  450. * @mtd: MTD device structure
  451. * @chip: NAND chip structure
  452. *
  453. * Wait for controller and FLASH to both be ready.
  454. */
  455. static int lpc32xx_waitfunc(struct mtd_info *mtd, struct nand_chip *chip)
  456. {
  457. int status;
  458. unsigned int timeout;
  459. /* wait until both controller and NAND are ready */
  460. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  461. status = readl(&lpc32xx_nand_mlc_registers->isr);
  462. if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
  463. == (ISR_CONTROLLER_READY || ISR_NAND_READY))
  464. break;
  465. udelay(1);
  466. }
  467. /* if controller or NAND stalled, return error */
  468. if ((status & (ISR_CONTROLLER_READY || ISR_NAND_READY))
  469. != (ISR_CONTROLLER_READY || ISR_NAND_READY))
  470. return -1;
  471. /* write NAND status command */
  472. writel(NAND_CMD_STATUS, &lpc32xx_nand_mlc_registers->cmd);
  473. /* read back status and return it */
  474. return readb(&lpc32xx_nand_mlc_registers->data);
  475. }
  476. /*
  477. * We are self-initializing, so we need our own chip struct
  478. */
  479. static struct nand_chip lpc32xx_chip;
  480. /*
  481. * Initialize the controller
  482. */
  483. void board_nand_init(void)
  484. {
  485. struct mtd_info *mtd = nand_to_mtd(&lpc32xx_chip);
  486. int ret;
  487. /* Set all BOARDSPECIFIC (actually core-specific) fields */
  488. lpc32xx_chip.IO_ADDR_R = &lpc32xx_nand_mlc_registers->buff;
  489. lpc32xx_chip.IO_ADDR_W = &lpc32xx_nand_mlc_registers->buff;
  490. lpc32xx_chip.cmd_ctrl = lpc32xx_cmd_ctrl;
  491. /* do not set init_size: nand_base.c will read sizes from chip */
  492. lpc32xx_chip.dev_ready = lpc32xx_dev_ready;
  493. /* do not set setup_read_retry: this is NAND-chip-specific */
  494. /* do not set chip_delay: we have dev_ready defined. */
  495. lpc32xx_chip.options |= NAND_NO_SUBPAGE_WRITE;
  496. /* Set needed ECC fields */
  497. lpc32xx_chip.ecc.mode = NAND_ECC_HW;
  498. lpc32xx_chip.ecc.layout = &lpc32xx_largepage_ecclayout;
  499. lpc32xx_chip.ecc.size = 512;
  500. lpc32xx_chip.ecc.bytes = 10;
  501. lpc32xx_chip.ecc.strength = 4;
  502. lpc32xx_chip.ecc.read_page = lpc32xx_read_page_hwecc;
  503. lpc32xx_chip.ecc.read_page_raw = lpc32xx_read_page_raw;
  504. lpc32xx_chip.ecc.write_page = lpc32xx_write_page_hwecc;
  505. lpc32xx_chip.ecc.write_page_raw = lpc32xx_write_page_raw;
  506. lpc32xx_chip.ecc.read_oob = lpc32xx_read_oob;
  507. lpc32xx_chip.ecc.write_oob = lpc32xx_write_oob;
  508. lpc32xx_chip.waitfunc = lpc32xx_waitfunc;
  509. lpc32xx_chip.read_byte = lpc32xx_read_byte; /* FIXME: NEEDED? */
  510. /* BBT options: read from last two pages */
  511. lpc32xx_chip.bbt_options |= NAND_BBT_USE_FLASH | NAND_BBT_LASTBLOCK
  512. | NAND_BBT_SCANLASTPAGE | NAND_BBT_SCAN2NDPAGE
  513. | NAND_BBT_WRITE;
  514. /* Initialize NAND interface */
  515. lpc32xx_nand_init();
  516. /* identify chip */
  517. ret = nand_scan_ident(mtd, CONFIG_SYS_MAX_NAND_CHIPS, NULL);
  518. if (ret) {
  519. pr_err("nand_scan_ident returned %i", ret);
  520. return;
  521. }
  522. /* finish scanning the chip */
  523. ret = nand_scan_tail(mtd);
  524. if (ret) {
  525. pr_err("nand_scan_tail returned %i", ret);
  526. return;
  527. }
  528. /* chip is good, register it */
  529. ret = nand_register(0, mtd);
  530. if (ret)
  531. pr_err("nand_register returned %i", ret);
  532. }
  533. #else /* defined(CONFIG_SPL_BUILD) */
  534. void nand_init(void)
  535. {
  536. /* enable NAND controller */
  537. lpc32xx_mlc_nand_init();
  538. /* initialize NAND controller */
  539. lpc32xx_nand_init();
  540. }
  541. void nand_deselect(void)
  542. {
  543. /* nothing to do, but SPL requires this function */
  544. }
  545. static int read_single_page(uint8_t *dest, int page,
  546. struct lpc32xx_oob *oob)
  547. {
  548. int status, i, timeout, err, max_bitflips = 0;
  549. /* enter read mode */
  550. writel(NAND_CMD_READ0, &lpc32xx_nand_mlc_registers->cmd);
  551. /* send column (lsb then MSB) and page (lsb to MSB) */
  552. writel(0, &lpc32xx_nand_mlc_registers->addr);
  553. writel(0, &lpc32xx_nand_mlc_registers->addr);
  554. writel(page & 0xff, &lpc32xx_nand_mlc_registers->addr);
  555. writel((page>>8) & 0xff, &lpc32xx_nand_mlc_registers->addr);
  556. writel((page>>16) & 0xff, &lpc32xx_nand_mlc_registers->addr);
  557. /* start reading */
  558. writel(NAND_CMD_READSTART, &lpc32xx_nand_mlc_registers->cmd);
  559. /* large page auto decode read */
  560. for (i = 0; i < 4; i++) {
  561. /* start auto decode (reads 528 NAND bytes) */
  562. writel(0, &lpc32xx_nand_mlc_registers->ecc_auto_dec_reg);
  563. /* wait for controller to return to ready state */
  564. for (timeout = LPC32X_NAND_TIMEOUT; timeout; timeout--) {
  565. status = readl(&lpc32xx_nand_mlc_registers->isr);
  566. if (status & ISR_CONTROLLER_READY)
  567. break;
  568. udelay(1);
  569. }
  570. /* if controller stalled, return error */
  571. if (!(status & ISR_CONTROLLER_READY))
  572. return -1;
  573. /* if decoder failure, return error */
  574. if (status & ISR_DECODER_FAILURE)
  575. return -1;
  576. /* keep count of maximum bitflips performed */
  577. if (status & ISR_DECODER_ERROR) {
  578. err = ISR_DECODER_ERRORS(status);
  579. if (err > max_bitflips)
  580. max_bitflips = err;
  581. }
  582. /* copy first 512 bytes into buffer */
  583. memcpy(dest+i*512, lpc32xx_nand_mlc_registers->buff, 512);
  584. /* copy next 6 bytes bytes into OOB buffer */
  585. memcpy(&oob->free[i], lpc32xx_nand_mlc_registers->buff, 6);
  586. }
  587. return max_bitflips;
  588. }
  589. /*
  590. * Load U-Boot signed image.
  591. * This loads an image from NAND, skipping bad blocks.
  592. * A block is declared bad if at least one of its readable pages has
  593. * a bad block marker in its OOB at position 0.
  594. * If all pages ion a block are unreadable, the block is considered
  595. * bad (i.e., assumed not to be part of the image) and skipped.
  596. *
  597. * IMPORTANT NOTE:
  598. *
  599. * If the first block of the image is fully unreadable, it will be
  600. * ignored and skipped as if it had been marked bad. If it was not
  601. * actually marked bad at the time of writing the image, the resulting
  602. * image loaded will lack a header and magic number. It could thus be
  603. * considered as a raw, headerless, image and SPL might erroneously
  604. * jump into it.
  605. *
  606. * In order to avoid this risk, LPC32XX-based boards which use this
  607. * driver MUST define CONFIG_SPL_PANIC_ON_RAW_IMAGE.
  608. */
  609. #define BYTES_PER_PAGE 2048
  610. #define PAGES_PER_BLOCK 64
  611. #define BYTES_PER_BLOCK (BYTES_PER_PAGE * PAGES_PER_BLOCK)
  612. #define PAGES_PER_CHIP_MAX 524288
  613. int nand_spl_load_image(uint32_t offs, unsigned int size, void *dst)
  614. {
  615. int bytes_left = size;
  616. int pages_left = DIV_ROUND_UP(size, BYTES_PER_PAGE);
  617. int blocks_left = DIV_ROUND_UP(size, BYTES_PER_BLOCK);
  618. int block = 0;
  619. int page = offs / BYTES_PER_PAGE;
  620. /* perform reads block by block */
  621. while (blocks_left) {
  622. /* compute first page number to read */
  623. void *block_page_dst = dst;
  624. /* read at most one block, possibly less */
  625. int block_bytes_left = bytes_left;
  626. if (block_bytes_left > BYTES_PER_BLOCK)
  627. block_bytes_left = BYTES_PER_BLOCK;
  628. /* keep track of good, failed, and "bad" pages */
  629. int block_pages_good = 0;
  630. int block_pages_bad = 0;
  631. int block_pages_err = 0;
  632. /* we shall read a full block of pages, maybe less */
  633. int block_pages_left = pages_left;
  634. if (block_pages_left > PAGES_PER_BLOCK)
  635. block_pages_left = PAGES_PER_BLOCK;
  636. int block_pages = block_pages_left;
  637. int block_page = page;
  638. /* while pages are left and the block is not known as bad */
  639. while ((block_pages > 0) && (block_pages_bad == 0)) {
  640. /* we will read OOB, too, for bad block markers */
  641. struct lpc32xx_oob oob;
  642. /* read page */
  643. int res = read_single_page(block_page_dst, block_page,
  644. &oob);
  645. /* count readable pages */
  646. if (res >= 0) {
  647. /* this page is good */
  648. block_pages_good++;
  649. /* this page is bad */
  650. if ((oob.free[0].free_oob_bytes[0] != 0xff)
  651. | (oob.free[0].free_oob_bytes[1] != 0xff))
  652. block_pages_bad++;
  653. } else
  654. /* count errors */
  655. block_pages_err++;
  656. /* we're done with this page */
  657. block_page++;
  658. block_page_dst += BYTES_PER_PAGE;
  659. if (block_pages)
  660. block_pages--;
  661. }
  662. /* a fully unreadable block is considered bad */
  663. if (block_pages_good == 0)
  664. block_pages_bad = block_pages_err;
  665. /* errors are fatal only in good blocks */
  666. if ((block_pages_err > 0) && (block_pages_bad == 0))
  667. return -1;
  668. /* we keep reads only of good blocks */
  669. if (block_pages_bad == 0) {
  670. dst += block_bytes_left;
  671. bytes_left -= block_bytes_left;
  672. pages_left -= block_pages_left;
  673. blocks_left--;
  674. }
  675. /* good or bad, we're done with this block */
  676. block++;
  677. page += PAGES_PER_BLOCK;
  678. }
  679. /* report success */
  680. return 0;
  681. }
  682. #endif /* CONFIG_SPL_BUILD */