fsl_ifc_nand.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0+
  2. /* Integrated Flash Controller NAND Machine Driver
  3. *
  4. * Copyright (c) 2012 Freescale Semiconductor, Inc
  5. *
  6. * Authors: Dipen Dudhat <Dipen.Dudhat@freescale.com>
  7. */
  8. #include <common.h>
  9. #include <malloc.h>
  10. #include <nand.h>
  11. #include <linux/mtd/mtd.h>
  12. #include <linux/mtd/rawnand.h>
  13. #include <linux/mtd/nand_ecc.h>
  14. #include <asm/io.h>
  15. #include <linux/errno.h>
  16. #include <fsl_ifc.h>
  17. #ifndef CONFIG_SYS_FSL_IFC_BANK_COUNT
  18. #define CONFIG_SYS_FSL_IFC_BANK_COUNT 4
  19. #endif
  20. #define MAX_BANKS CONFIG_SYS_FSL_IFC_BANK_COUNT
  21. #define ERR_BYTE 0xFF /* Value returned for read bytes
  22. when read failed */
  23. struct fsl_ifc_ctrl;
  24. /* mtd information per set */
  25. struct fsl_ifc_mtd {
  26. struct nand_chip chip;
  27. struct fsl_ifc_ctrl *ctrl;
  28. struct device *dev;
  29. int bank; /* Chip select bank number */
  30. unsigned int bufnum_mask; /* bufnum = page & bufnum_mask */
  31. u8 __iomem *vbase; /* Chip select base virtual address */
  32. };
  33. /* overview of the fsl ifc controller */
  34. struct fsl_ifc_ctrl {
  35. struct nand_hw_control controller;
  36. struct fsl_ifc_mtd *chips[MAX_BANKS];
  37. /* device info */
  38. struct fsl_ifc regs;
  39. void __iomem *addr; /* Address of assigned IFC buffer */
  40. unsigned int page; /* Last page written to / read from */
  41. unsigned int read_bytes; /* Number of bytes read during command */
  42. unsigned int column; /* Saved column from SEQIN */
  43. unsigned int index; /* Pointer to next byte to 'read' */
  44. unsigned int status; /* status read from NEESR after last op */
  45. unsigned int oob; /* Non zero if operating on OOB data */
  46. unsigned int eccread; /* Non zero for a full-page ECC read */
  47. };
  48. static struct fsl_ifc_ctrl *ifc_ctrl;
  49. /* 512-byte page with 4-bit ECC, 8-bit */
  50. static struct nand_ecclayout oob_512_8bit_ecc4 = {
  51. .eccbytes = 8,
  52. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  53. .oobfree = { {0, 5}, {6, 2} },
  54. };
  55. /* 512-byte page with 4-bit ECC, 16-bit */
  56. static struct nand_ecclayout oob_512_16bit_ecc4 = {
  57. .eccbytes = 8,
  58. .eccpos = {8, 9, 10, 11, 12, 13, 14, 15},
  59. .oobfree = { {2, 6}, },
  60. };
  61. /* 2048-byte page size with 4-bit ECC */
  62. static struct nand_ecclayout oob_2048_ecc4 = {
  63. .eccbytes = 32,
  64. .eccpos = {
  65. 8, 9, 10, 11, 12, 13, 14, 15,
  66. 16, 17, 18, 19, 20, 21, 22, 23,
  67. 24, 25, 26, 27, 28, 29, 30, 31,
  68. 32, 33, 34, 35, 36, 37, 38, 39,
  69. },
  70. .oobfree = { {2, 6}, {40, 24} },
  71. };
  72. /* 4096-byte page size with 4-bit ECC */
  73. static struct nand_ecclayout oob_4096_ecc4 = {
  74. .eccbytes = 64,
  75. .eccpos = {
  76. 8, 9, 10, 11, 12, 13, 14, 15,
  77. 16, 17, 18, 19, 20, 21, 22, 23,
  78. 24, 25, 26, 27, 28, 29, 30, 31,
  79. 32, 33, 34, 35, 36, 37, 38, 39,
  80. 40, 41, 42, 43, 44, 45, 46, 47,
  81. 48, 49, 50, 51, 52, 53, 54, 55,
  82. 56, 57, 58, 59, 60, 61, 62, 63,
  83. 64, 65, 66, 67, 68, 69, 70, 71,
  84. },
  85. .oobfree = { {2, 6}, {72, 56} },
  86. };
  87. /* 4096-byte page size with 8-bit ECC -- requires 218-byte OOB */
  88. static struct nand_ecclayout oob_4096_ecc8 = {
  89. .eccbytes = 128,
  90. .eccpos = {
  91. 8, 9, 10, 11, 12, 13, 14, 15,
  92. 16, 17, 18, 19, 20, 21, 22, 23,
  93. 24, 25, 26, 27, 28, 29, 30, 31,
  94. 32, 33, 34, 35, 36, 37, 38, 39,
  95. 40, 41, 42, 43, 44, 45, 46, 47,
  96. 48, 49, 50, 51, 52, 53, 54, 55,
  97. 56, 57, 58, 59, 60, 61, 62, 63,
  98. 64, 65, 66, 67, 68, 69, 70, 71,
  99. 72, 73, 74, 75, 76, 77, 78, 79,
  100. 80, 81, 82, 83, 84, 85, 86, 87,
  101. 88, 89, 90, 91, 92, 93, 94, 95,
  102. 96, 97, 98, 99, 100, 101, 102, 103,
  103. 104, 105, 106, 107, 108, 109, 110, 111,
  104. 112, 113, 114, 115, 116, 117, 118, 119,
  105. 120, 121, 122, 123, 124, 125, 126, 127,
  106. 128, 129, 130, 131, 132, 133, 134, 135,
  107. },
  108. .oobfree = { {2, 6}, {136, 82} },
  109. };
  110. /* 8192-byte page size with 4-bit ECC */
  111. static struct nand_ecclayout oob_8192_ecc4 = {
  112. .eccbytes = 128,
  113. .eccpos = {
  114. 8, 9, 10, 11, 12, 13, 14, 15,
  115. 16, 17, 18, 19, 20, 21, 22, 23,
  116. 24, 25, 26, 27, 28, 29, 30, 31,
  117. 32, 33, 34, 35, 36, 37, 38, 39,
  118. 40, 41, 42, 43, 44, 45, 46, 47,
  119. 48, 49, 50, 51, 52, 53, 54, 55,
  120. 56, 57, 58, 59, 60, 61, 62, 63,
  121. 64, 65, 66, 67, 68, 69, 70, 71,
  122. 72, 73, 74, 75, 76, 77, 78, 79,
  123. 80, 81, 82, 83, 84, 85, 86, 87,
  124. 88, 89, 90, 91, 92, 93, 94, 95,
  125. 96, 97, 98, 99, 100, 101, 102, 103,
  126. 104, 105, 106, 107, 108, 109, 110, 111,
  127. 112, 113, 114, 115, 116, 117, 118, 119,
  128. 120, 121, 122, 123, 124, 125, 126, 127,
  129. 128, 129, 130, 131, 132, 133, 134, 135,
  130. },
  131. .oobfree = { {2, 6}, {136, 208} },
  132. };
  133. /* 8192-byte page size with 8-bit ECC -- requires 218-byte OOB */
  134. static struct nand_ecclayout oob_8192_ecc8 = {
  135. .eccbytes = 256,
  136. .eccpos = {
  137. 8, 9, 10, 11, 12, 13, 14, 15,
  138. 16, 17, 18, 19, 20, 21, 22, 23,
  139. 24, 25, 26, 27, 28, 29, 30, 31,
  140. 32, 33, 34, 35, 36, 37, 38, 39,
  141. 40, 41, 42, 43, 44, 45, 46, 47,
  142. 48, 49, 50, 51, 52, 53, 54, 55,
  143. 56, 57, 58, 59, 60, 61, 62, 63,
  144. 64, 65, 66, 67, 68, 69, 70, 71,
  145. 72, 73, 74, 75, 76, 77, 78, 79,
  146. 80, 81, 82, 83, 84, 85, 86, 87,
  147. 88, 89, 90, 91, 92, 93, 94, 95,
  148. 96, 97, 98, 99, 100, 101, 102, 103,
  149. 104, 105, 106, 107, 108, 109, 110, 111,
  150. 112, 113, 114, 115, 116, 117, 118, 119,
  151. 120, 121, 122, 123, 124, 125, 126, 127,
  152. 128, 129, 130, 131, 132, 133, 134, 135,
  153. 136, 137, 138, 139, 140, 141, 142, 143,
  154. 144, 145, 146, 147, 148, 149, 150, 151,
  155. 152, 153, 154, 155, 156, 157, 158, 159,
  156. 160, 161, 162, 163, 164, 165, 166, 167,
  157. 168, 169, 170, 171, 172, 173, 174, 175,
  158. 176, 177, 178, 179, 180, 181, 182, 183,
  159. 184, 185, 186, 187, 188, 189, 190, 191,
  160. 192, 193, 194, 195, 196, 197, 198, 199,
  161. 200, 201, 202, 203, 204, 205, 206, 207,
  162. 208, 209, 210, 211, 212, 213, 214, 215,
  163. 216, 217, 218, 219, 220, 221, 222, 223,
  164. 224, 225, 226, 227, 228, 229, 230, 231,
  165. 232, 233, 234, 235, 236, 237, 238, 239,
  166. 240, 241, 242, 243, 244, 245, 246, 247,
  167. 248, 249, 250, 251, 252, 253, 254, 255,
  168. 256, 257, 258, 259, 260, 261, 262, 263,
  169. },
  170. .oobfree = { {2, 6}, {264, 80} },
  171. };
  172. /*
  173. * Generic flash bbt descriptors
  174. */
  175. static u8 bbt_pattern[] = {'B', 'b', 't', '0' };
  176. static u8 mirror_pattern[] = {'1', 't', 'b', 'B' };
  177. static struct nand_bbt_descr bbt_main_descr = {
  178. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  179. NAND_BBT_2BIT | NAND_BBT_VERSION,
  180. .offs = 2, /* 0 on 8-bit small page */
  181. .len = 4,
  182. .veroffs = 6,
  183. .maxblocks = 4,
  184. .pattern = bbt_pattern,
  185. };
  186. static struct nand_bbt_descr bbt_mirror_descr = {
  187. .options = NAND_BBT_LASTBLOCK | NAND_BBT_CREATE | NAND_BBT_WRITE |
  188. NAND_BBT_2BIT | NAND_BBT_VERSION,
  189. .offs = 2, /* 0 on 8-bit small page */
  190. .len = 4,
  191. .veroffs = 6,
  192. .maxblocks = 4,
  193. .pattern = mirror_pattern,
  194. };
  195. /*
  196. * Set up the IFC hardware block and page address fields, and the ifc nand
  197. * structure addr field to point to the correct IFC buffer in memory
  198. */
  199. static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob)
  200. {
  201. struct nand_chip *chip = mtd_to_nand(mtd);
  202. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  203. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  204. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  205. int buf_num;
  206. ctrl->page = page_addr;
  207. /* Program ROW0/COL0 */
  208. ifc_out32(&ifc->ifc_nand.row0, page_addr);
  209. ifc_out32(&ifc->ifc_nand.col0, (oob ? IFC_NAND_COL_MS : 0) | column);
  210. buf_num = page_addr & priv->bufnum_mask;
  211. ctrl->addr = priv->vbase + buf_num * (mtd->writesize * 2);
  212. ctrl->index = column;
  213. /* for OOB data point to the second half of the buffer */
  214. if (oob)
  215. ctrl->index += mtd->writesize;
  216. }
  217. /* returns nonzero if entire page is blank */
  218. static int check_read_ecc(struct mtd_info *mtd, struct fsl_ifc_ctrl *ctrl,
  219. u32 eccstat, unsigned int bufnum)
  220. {
  221. return (eccstat >> ((3 - bufnum % 4) * 8)) & 15;
  222. }
  223. /*
  224. * execute IFC NAND command and wait for it to complete
  225. */
  226. static int fsl_ifc_run_command(struct mtd_info *mtd)
  227. {
  228. struct nand_chip *chip = mtd_to_nand(mtd);
  229. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  230. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  231. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  232. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  233. u32 time_start;
  234. u32 eccstat;
  235. int i;
  236. /* set the chip select for NAND Transaction */
  237. ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  238. /* start read/write seq */
  239. ifc_out32(&ifc->ifc_nand.nandseq_strt,
  240. IFC_NAND_SEQ_STRT_FIR_STRT);
  241. /* wait for NAND Machine complete flag or timeout */
  242. time_start = get_timer(0);
  243. while (get_timer(time_start) < timeo) {
  244. ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  245. if (ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  246. break;
  247. }
  248. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ctrl->status);
  249. if (ctrl->status & IFC_NAND_EVTER_STAT_FTOER)
  250. printf("%s: Flash Time Out Error\n", __func__);
  251. if (ctrl->status & IFC_NAND_EVTER_STAT_WPER)
  252. printf("%s: Write Protect Error\n", __func__);
  253. if (ctrl->eccread) {
  254. int errors;
  255. int bufnum = ctrl->page & priv->bufnum_mask;
  256. int sector_start = bufnum * chip->ecc.steps;
  257. int sector_end = sector_start + chip->ecc.steps - 1;
  258. u32 *eccstat_regs;
  259. eccstat_regs = ifc->ifc_nand.nand_eccstat;
  260. eccstat = ifc_in32(&eccstat_regs[sector_start / 4]);
  261. for (i = sector_start; i <= sector_end; i++) {
  262. if ((i != sector_start) && !(i % 4))
  263. eccstat = ifc_in32(&eccstat_regs[i / 4]);
  264. errors = check_read_ecc(mtd, ctrl, eccstat, i);
  265. if (errors == 15) {
  266. /*
  267. * Uncorrectable error.
  268. * We'll check for blank pages later.
  269. *
  270. * We disable ECCER reporting due to erratum
  271. * IFC-A002770 -- so report it now if we
  272. * see an uncorrectable error in ECCSTAT.
  273. */
  274. ctrl->status |= IFC_NAND_EVTER_STAT_ECCER;
  275. continue;
  276. }
  277. mtd->ecc_stats.corrected += errors;
  278. }
  279. ctrl->eccread = 0;
  280. }
  281. /* returns 0 on success otherwise non-zero) */
  282. return ctrl->status == IFC_NAND_EVTER_STAT_OPC ? 0 : -EIO;
  283. }
  284. static void fsl_ifc_do_read(struct nand_chip *chip,
  285. int oob,
  286. struct mtd_info *mtd)
  287. {
  288. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  289. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  290. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  291. /* Program FIR/IFC_NAND_FCR0 for Small/Large page */
  292. if (mtd->writesize > 512) {
  293. ifc_out32(&ifc->ifc_nand.nand_fir0,
  294. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  295. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  296. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  297. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP3_SHIFT) |
  298. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP4_SHIFT));
  299. ifc_out32(&ifc->ifc_nand.nand_fir1, 0x0);
  300. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  301. (NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT) |
  302. (NAND_CMD_READSTART << IFC_NAND_FCR0_CMD1_SHIFT));
  303. } else {
  304. ifc_out32(&ifc->ifc_nand.nand_fir0,
  305. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  306. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  307. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  308. (IFC_FIR_OP_RBCD << IFC_NAND_FIR0_OP3_SHIFT));
  309. if (oob)
  310. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  311. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT);
  312. else
  313. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  314. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT);
  315. }
  316. }
  317. /* cmdfunc send commands to the IFC NAND Machine */
  318. static void fsl_ifc_cmdfunc(struct mtd_info *mtd, unsigned int command,
  319. int column, int page_addr)
  320. {
  321. struct nand_chip *chip = mtd_to_nand(mtd);
  322. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  323. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  324. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  325. /* clear the read buffer */
  326. ctrl->read_bytes = 0;
  327. if (command != NAND_CMD_PAGEPROG)
  328. ctrl->index = 0;
  329. switch (command) {
  330. /* READ0 read the entire buffer to use hardware ECC. */
  331. case NAND_CMD_READ0: {
  332. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  333. set_addr(mtd, 0, page_addr, 0);
  334. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  335. ctrl->index += column;
  336. if (chip->ecc.mode == NAND_ECC_HW)
  337. ctrl->eccread = 1;
  338. fsl_ifc_do_read(chip, 0, mtd);
  339. fsl_ifc_run_command(mtd);
  340. return;
  341. }
  342. /* READOOB reads only the OOB because no ECC is performed. */
  343. case NAND_CMD_READOOB:
  344. ifc_out32(&ifc->ifc_nand.nand_fbcr, mtd->oobsize - column);
  345. set_addr(mtd, column, page_addr, 1);
  346. ctrl->read_bytes = mtd->writesize + mtd->oobsize;
  347. fsl_ifc_do_read(chip, 1, mtd);
  348. fsl_ifc_run_command(mtd);
  349. return;
  350. /* READID must read all possible bytes while CEB is active */
  351. case NAND_CMD_READID:
  352. case NAND_CMD_PARAM: {
  353. int timing = IFC_FIR_OP_RB;
  354. if (command == NAND_CMD_PARAM)
  355. timing = IFC_FIR_OP_RBCD;
  356. ifc_out32(&ifc->ifc_nand.nand_fir0,
  357. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  358. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  359. (timing << IFC_NAND_FIR0_OP2_SHIFT));
  360. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  361. command << IFC_NAND_FCR0_CMD0_SHIFT);
  362. ifc_out32(&ifc->ifc_nand.row3, column);
  363. /*
  364. * although currently it's 8 bytes for READID, we always read
  365. * the maximum 256 bytes(for PARAM)
  366. */
  367. ifc_out32(&ifc->ifc_nand.nand_fbcr, 256);
  368. ctrl->read_bytes = 256;
  369. set_addr(mtd, 0, 0, 0);
  370. fsl_ifc_run_command(mtd);
  371. return;
  372. }
  373. /* ERASE1 stores the block and page address */
  374. case NAND_CMD_ERASE1:
  375. set_addr(mtd, 0, page_addr, 0);
  376. return;
  377. /* ERASE2 uses the block and page address from ERASE1 */
  378. case NAND_CMD_ERASE2:
  379. ifc_out32(&ifc->ifc_nand.nand_fir0,
  380. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  381. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  382. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR0_OP2_SHIFT));
  383. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  384. (NAND_CMD_ERASE1 << IFC_NAND_FCR0_CMD0_SHIFT) |
  385. (NAND_CMD_ERASE2 << IFC_NAND_FCR0_CMD1_SHIFT));
  386. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  387. ctrl->read_bytes = 0;
  388. fsl_ifc_run_command(mtd);
  389. return;
  390. /* SEQIN sets up the addr buffer and all registers except the length */
  391. case NAND_CMD_SEQIN: {
  392. u32 nand_fcr0;
  393. ctrl->column = column;
  394. ctrl->oob = 0;
  395. if (mtd->writesize > 512) {
  396. nand_fcr0 =
  397. (NAND_CMD_SEQIN << IFC_NAND_FCR0_CMD0_SHIFT) |
  398. (NAND_CMD_STATUS << IFC_NAND_FCR0_CMD1_SHIFT) |
  399. (NAND_CMD_PAGEPROG << IFC_NAND_FCR0_CMD2_SHIFT);
  400. ifc_out32(&ifc->ifc_nand.nand_fir0,
  401. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  402. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP1_SHIFT) |
  403. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  404. (IFC_FIR_OP_WBCD <<
  405. IFC_NAND_FIR0_OP3_SHIFT) |
  406. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP4_SHIFT));
  407. ifc_out32(&ifc->ifc_nand.nand_fir1,
  408. (IFC_FIR_OP_CW1 << IFC_NAND_FIR1_OP5_SHIFT) |
  409. (IFC_FIR_OP_RDSTAT <<
  410. IFC_NAND_FIR1_OP6_SHIFT) |
  411. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP7_SHIFT));
  412. } else {
  413. nand_fcr0 = ((NAND_CMD_PAGEPROG <<
  414. IFC_NAND_FCR0_CMD1_SHIFT) |
  415. (NAND_CMD_SEQIN <<
  416. IFC_NAND_FCR0_CMD2_SHIFT) |
  417. (NAND_CMD_STATUS <<
  418. IFC_NAND_FCR0_CMD3_SHIFT));
  419. ifc_out32(&ifc->ifc_nand.nand_fir0,
  420. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  421. (IFC_FIR_OP_CMD2 << IFC_NAND_FIR0_OP1_SHIFT) |
  422. (IFC_FIR_OP_CA0 << IFC_NAND_FIR0_OP2_SHIFT) |
  423. (IFC_FIR_OP_RA0 << IFC_NAND_FIR0_OP3_SHIFT) |
  424. (IFC_FIR_OP_WBCD << IFC_NAND_FIR0_OP4_SHIFT));
  425. ifc_out32(&ifc->ifc_nand.nand_fir1,
  426. (IFC_FIR_OP_CMD1 << IFC_NAND_FIR1_OP5_SHIFT) |
  427. (IFC_FIR_OP_CW3 << IFC_NAND_FIR1_OP6_SHIFT) |
  428. (IFC_FIR_OP_RDSTAT <<
  429. IFC_NAND_FIR1_OP7_SHIFT) |
  430. (IFC_FIR_OP_NOP << IFC_NAND_FIR1_OP8_SHIFT));
  431. if (column >= mtd->writesize)
  432. nand_fcr0 |=
  433. NAND_CMD_READOOB << IFC_NAND_FCR0_CMD0_SHIFT;
  434. else
  435. nand_fcr0 |=
  436. NAND_CMD_READ0 << IFC_NAND_FCR0_CMD0_SHIFT;
  437. }
  438. if (column >= mtd->writesize) {
  439. /* OOB area --> READOOB */
  440. column -= mtd->writesize;
  441. ctrl->oob = 1;
  442. }
  443. ifc_out32(&ifc->ifc_nand.nand_fcr0, nand_fcr0);
  444. set_addr(mtd, column, page_addr, ctrl->oob);
  445. return;
  446. }
  447. /* PAGEPROG reuses all of the setup from SEQIN and adds the length */
  448. case NAND_CMD_PAGEPROG:
  449. if (ctrl->oob)
  450. ifc_out32(&ifc->ifc_nand.nand_fbcr,
  451. ctrl->index - ctrl->column);
  452. else
  453. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0);
  454. fsl_ifc_run_command(mtd);
  455. return;
  456. case NAND_CMD_STATUS:
  457. ifc_out32(&ifc->ifc_nand.nand_fir0,
  458. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  459. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP1_SHIFT));
  460. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  461. NAND_CMD_STATUS << IFC_NAND_FCR0_CMD0_SHIFT);
  462. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  463. set_addr(mtd, 0, 0, 0);
  464. ctrl->read_bytes = 1;
  465. fsl_ifc_run_command(mtd);
  466. /*
  467. * The chip always seems to report that it is
  468. * write-protected, even when it is not.
  469. */
  470. if (chip->options & NAND_BUSWIDTH_16)
  471. ifc_out16(ctrl->addr,
  472. ifc_in16(ctrl->addr) | NAND_STATUS_WP);
  473. else
  474. out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP);
  475. return;
  476. case NAND_CMD_RESET:
  477. ifc_out32(&ifc->ifc_nand.nand_fir0,
  478. IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT);
  479. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  480. NAND_CMD_RESET << IFC_NAND_FCR0_CMD0_SHIFT);
  481. fsl_ifc_run_command(mtd);
  482. return;
  483. default:
  484. printf("%s: error, unsupported command 0x%x.\n",
  485. __func__, command);
  486. }
  487. }
  488. /*
  489. * Write buf to the IFC NAND Controller Data Buffer
  490. */
  491. static void fsl_ifc_write_buf(struct mtd_info *mtd, const u8 *buf, int len)
  492. {
  493. struct nand_chip *chip = mtd_to_nand(mtd);
  494. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  495. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  496. unsigned int bufsize = mtd->writesize + mtd->oobsize;
  497. if (len <= 0) {
  498. printf("%s of %d bytes", __func__, len);
  499. ctrl->status = 0;
  500. return;
  501. }
  502. if ((unsigned int)len > bufsize - ctrl->index) {
  503. printf("%s beyond end of buffer "
  504. "(%d requested, %u available)\n",
  505. __func__, len, bufsize - ctrl->index);
  506. len = bufsize - ctrl->index;
  507. }
  508. memcpy_toio(ctrl->addr + ctrl->index, buf, len);
  509. ctrl->index += len;
  510. }
  511. /*
  512. * read a byte from either the IFC hardware buffer if it has any data left
  513. * otherwise issue a command to read a single byte.
  514. */
  515. static u8 fsl_ifc_read_byte(struct mtd_info *mtd)
  516. {
  517. struct nand_chip *chip = mtd_to_nand(mtd);
  518. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  519. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  520. unsigned int offset;
  521. /*
  522. * If there are still bytes in the IFC buffer, then use the
  523. * next byte.
  524. */
  525. if (ctrl->index < ctrl->read_bytes) {
  526. offset = ctrl->index++;
  527. return in_8(ctrl->addr + offset);
  528. }
  529. printf("%s beyond end of buffer\n", __func__);
  530. return ERR_BYTE;
  531. }
  532. /*
  533. * Read two bytes from the IFC hardware buffer
  534. * read function for 16-bit buswith
  535. */
  536. static uint8_t fsl_ifc_read_byte16(struct mtd_info *mtd)
  537. {
  538. struct nand_chip *chip = mtd_to_nand(mtd);
  539. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  540. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  541. uint16_t data;
  542. /*
  543. * If there are still bytes in the IFC buffer, then use the
  544. * next byte.
  545. */
  546. if (ctrl->index < ctrl->read_bytes) {
  547. data = ifc_in16(ctrl->addr + ctrl->index);
  548. ctrl->index += 2;
  549. return (uint8_t)data;
  550. }
  551. printf("%s beyond end of buffer\n", __func__);
  552. return ERR_BYTE;
  553. }
  554. /*
  555. * Read from the IFC Controller Data Buffer
  556. */
  557. static void fsl_ifc_read_buf(struct mtd_info *mtd, u8 *buf, int len)
  558. {
  559. struct nand_chip *chip = mtd_to_nand(mtd);
  560. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  561. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  562. int avail;
  563. if (len < 0)
  564. return;
  565. avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index);
  566. memcpy_fromio(buf, ctrl->addr + ctrl->index, avail);
  567. ctrl->index += avail;
  568. if (len > avail)
  569. printf("%s beyond end of buffer "
  570. "(%d requested, %d available)\n",
  571. __func__, len, avail);
  572. }
  573. /* This function is called after Program and Erase Operations to
  574. * check for success or failure.
  575. */
  576. static int fsl_ifc_wait(struct mtd_info *mtd, struct nand_chip *chip)
  577. {
  578. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  579. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  580. struct fsl_ifc_runtime *ifc = ctrl->regs.rregs;
  581. u32 nand_fsr;
  582. int status;
  583. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  584. return NAND_STATUS_FAIL;
  585. /* Use READ_STATUS command, but wait for the device to be ready */
  586. ifc_out32(&ifc->ifc_nand.nand_fir0,
  587. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  588. (IFC_FIR_OP_RDSTAT << IFC_NAND_FIR0_OP1_SHIFT));
  589. ifc_out32(&ifc->ifc_nand.nand_fcr0, NAND_CMD_STATUS <<
  590. IFC_NAND_FCR0_CMD0_SHIFT);
  591. ifc_out32(&ifc->ifc_nand.nand_fbcr, 1);
  592. set_addr(mtd, 0, 0, 0);
  593. ctrl->read_bytes = 1;
  594. fsl_ifc_run_command(mtd);
  595. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  596. return NAND_STATUS_FAIL;
  597. nand_fsr = ifc_in32(&ifc->ifc_nand.nand_fsr);
  598. status = nand_fsr >> 24;
  599. /* Chip sometimes reporting write protect even when it's not */
  600. return status | NAND_STATUS_WP;
  601. }
  602. /*
  603. * The controller does not check for bitflips in erased pages,
  604. * therefore software must check instead.
  605. */
  606. static int
  607. check_erased_page(struct nand_chip *chip, u8 *buf, struct mtd_info *mtd)
  608. {
  609. u8 *ecc = chip->oob_poi;
  610. const int ecc_size = chip->ecc.bytes;
  611. const int pkt_size = chip->ecc.size;
  612. int i, res, bitflips;
  613. /* IFC starts ecc bytes at offset 8 in the spare area. */
  614. ecc += 8;
  615. bitflips = 0;
  616. for (i = 0; i < chip->ecc.steps; i++) {
  617. res = nand_check_erased_ecc_chunk(buf, pkt_size, ecc, ecc_size,
  618. NULL, 0, chip->ecc.strength);
  619. if (res < 0) {
  620. printf("fsl-ifc: NAND Flash ECC Uncorrectable Error\n");
  621. mtd->ecc_stats.failed++;
  622. } else if (res > 0) {
  623. mtd->ecc_stats.corrected += res;
  624. }
  625. bitflips = max(res, bitflips);
  626. buf += pkt_size;
  627. ecc += ecc_size;
  628. }
  629. return bitflips;
  630. }
  631. static int fsl_ifc_read_page(struct mtd_info *mtd, struct nand_chip *chip,
  632. uint8_t *buf, int oob_required, int page)
  633. {
  634. struct fsl_ifc_mtd *priv = nand_get_controller_data(chip);
  635. struct fsl_ifc_ctrl *ctrl = priv->ctrl;
  636. fsl_ifc_read_buf(mtd, buf, mtd->writesize);
  637. fsl_ifc_read_buf(mtd, chip->oob_poi, mtd->oobsize);
  638. if (ctrl->status & IFC_NAND_EVTER_STAT_ECCER)
  639. return check_erased_page(chip, buf, mtd);
  640. if (ctrl->status != IFC_NAND_EVTER_STAT_OPC)
  641. mtd->ecc_stats.failed++;
  642. return 0;
  643. }
  644. /* ECC will be calculated automatically, and errors will be detected in
  645. * waitfunc.
  646. */
  647. static int fsl_ifc_write_page(struct mtd_info *mtd, struct nand_chip *chip,
  648. const uint8_t *buf, int oob_required, int page)
  649. {
  650. fsl_ifc_write_buf(mtd, buf, mtd->writesize);
  651. fsl_ifc_write_buf(mtd, chip->oob_poi, mtd->oobsize);
  652. return 0;
  653. }
  654. static void fsl_ifc_ctrl_init(void)
  655. {
  656. uint32_t ver = 0;
  657. ifc_ctrl = kzalloc(sizeof(*ifc_ctrl), GFP_KERNEL);
  658. if (!ifc_ctrl)
  659. return;
  660. ifc_ctrl->regs.gregs = IFC_FCM_BASE_ADDR;
  661. ver = ifc_in32(&ifc_ctrl->regs.gregs->ifc_rev);
  662. if (ver >= FSL_IFC_V2_0_0)
  663. ifc_ctrl->regs.rregs =
  664. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_64KOFFSET;
  665. else
  666. ifc_ctrl->regs.rregs =
  667. (void *)CONFIG_SYS_IFC_ADDR + IFC_RREGS_4KOFFSET;
  668. /* clear event registers */
  669. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_stat, ~0U);
  670. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.pgrdcmpl_evt_stat, ~0U);
  671. /* Enable error and event for any detected errors */
  672. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.nand_evter_en,
  673. IFC_NAND_EVTER_EN_OPC_EN |
  674. IFC_NAND_EVTER_EN_PGRDCMPL_EN |
  675. IFC_NAND_EVTER_EN_FTOER_EN |
  676. IFC_NAND_EVTER_EN_WPER_EN);
  677. ifc_out32(&ifc_ctrl->regs.rregs->ifc_nand.ncfgr, 0x0);
  678. }
  679. static void fsl_ifc_select_chip(struct mtd_info *mtd, int chip)
  680. {
  681. }
  682. static int fsl_ifc_sram_init(struct fsl_ifc_mtd *priv, uint32_t ver)
  683. {
  684. struct fsl_ifc_runtime *ifc = ifc_ctrl->regs.rregs;
  685. uint32_t cs = 0, csor = 0, csor_8k = 0, csor_ext = 0;
  686. uint32_t ncfgr = 0;
  687. u32 timeo = (CONFIG_SYS_HZ * 10) / 1000;
  688. u32 time_start;
  689. if (ver > FSL_IFC_V1_1_0) {
  690. ncfgr = ifc_in32(&ifc->ifc_nand.ncfgr);
  691. ifc_out32(&ifc->ifc_nand.ncfgr, ncfgr | IFC_NAND_SRAM_INIT_EN);
  692. /* wait for SRAM_INIT bit to be clear or timeout */
  693. time_start = get_timer(0);
  694. while (get_timer(time_start) < timeo) {
  695. ifc_ctrl->status =
  696. ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  697. if (!(ifc_ctrl->status & IFC_NAND_SRAM_INIT_EN))
  698. return 0;
  699. }
  700. printf("fsl-ifc: Failed to Initialise SRAM\n");
  701. return 1;
  702. }
  703. cs = priv->bank;
  704. /* Save CSOR and CSOR_ext */
  705. csor = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor);
  706. csor_ext = ifc_in32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext);
  707. /* chage PageSize 8K and SpareSize 1K*/
  708. csor_8k = (csor & ~(CSOR_NAND_PGS_MASK)) | 0x0018C000;
  709. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor_8k);
  710. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, 0x0000400);
  711. /* READID */
  712. ifc_out32(&ifc->ifc_nand.nand_fir0,
  713. (IFC_FIR_OP_CW0 << IFC_NAND_FIR0_OP0_SHIFT) |
  714. (IFC_FIR_OP_UA << IFC_NAND_FIR0_OP1_SHIFT) |
  715. (IFC_FIR_OP_RB << IFC_NAND_FIR0_OP2_SHIFT));
  716. ifc_out32(&ifc->ifc_nand.nand_fcr0,
  717. NAND_CMD_READID << IFC_NAND_FCR0_CMD0_SHIFT);
  718. ifc_out32(&ifc->ifc_nand.row3, 0x0);
  719. ifc_out32(&ifc->ifc_nand.nand_fbcr, 0x0);
  720. /* Program ROW0/COL0 */
  721. ifc_out32(&ifc->ifc_nand.row0, 0x0);
  722. ifc_out32(&ifc->ifc_nand.col0, 0x0);
  723. /* set the chip select for NAND Transaction */
  724. ifc_out32(&ifc->ifc_nand.nand_csel, priv->bank << IFC_NAND_CSEL_SHIFT);
  725. /* start read seq */
  726. ifc_out32(&ifc->ifc_nand.nandseq_strt, IFC_NAND_SEQ_STRT_FIR_STRT);
  727. time_start = get_timer(0);
  728. while (get_timer(time_start) < timeo) {
  729. ifc_ctrl->status = ifc_in32(&ifc->ifc_nand.nand_evter_stat);
  730. if (ifc_ctrl->status & IFC_NAND_EVTER_STAT_OPC)
  731. break;
  732. }
  733. if (ifc_ctrl->status != IFC_NAND_EVTER_STAT_OPC) {
  734. printf("fsl-ifc: Failed to Initialise SRAM\n");
  735. return 1;
  736. }
  737. ifc_out32(&ifc->ifc_nand.nand_evter_stat, ifc_ctrl->status);
  738. /* Restore CSOR and CSOR_ext */
  739. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor, csor);
  740. ifc_out32(&ifc_ctrl->regs.gregs->csor_cs[cs].csor_ext, csor_ext);
  741. return 0;
  742. }
  743. static int fsl_ifc_chip_init(int devnum, u8 *addr)
  744. {
  745. struct mtd_info *mtd;
  746. struct nand_chip *nand;
  747. struct fsl_ifc_mtd *priv;
  748. struct nand_ecclayout *layout;
  749. struct fsl_ifc_fcm *gregs = NULL;
  750. uint32_t cspr = 0, csor = 0, ver = 0;
  751. int ret = 0;
  752. if (!ifc_ctrl) {
  753. fsl_ifc_ctrl_init();
  754. if (!ifc_ctrl)
  755. return -1;
  756. }
  757. priv = kzalloc(sizeof(*priv), GFP_KERNEL);
  758. if (!priv)
  759. return -ENOMEM;
  760. priv->ctrl = ifc_ctrl;
  761. priv->vbase = addr;
  762. gregs = ifc_ctrl->regs.gregs;
  763. /* Find which chip select it is connected to.
  764. */
  765. for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) {
  766. phys_addr_t phys_addr = virt_to_phys(addr);
  767. cspr = ifc_in32(&gregs->cspr_cs[priv->bank].cspr);
  768. csor = ifc_in32(&gregs->csor_cs[priv->bank].csor);
  769. if ((cspr & CSPR_V) && (cspr & CSPR_MSEL) == CSPR_MSEL_NAND &&
  770. (cspr & CSPR_BA) == CSPR_PHYS_ADDR(phys_addr))
  771. break;
  772. }
  773. if (priv->bank >= MAX_BANKS) {
  774. printf("%s: address did not match any "
  775. "chip selects\n", __func__);
  776. kfree(priv);
  777. return -ENODEV;
  778. }
  779. nand = &priv->chip;
  780. mtd = nand_to_mtd(nand);
  781. ifc_ctrl->chips[priv->bank] = priv;
  782. /* fill in nand_chip structure */
  783. /* set up function call table */
  784. nand->write_buf = fsl_ifc_write_buf;
  785. nand->read_buf = fsl_ifc_read_buf;
  786. nand->select_chip = fsl_ifc_select_chip;
  787. nand->cmdfunc = fsl_ifc_cmdfunc;
  788. nand->waitfunc = fsl_ifc_wait;
  789. /* set up nand options */
  790. nand->bbt_td = &bbt_main_descr;
  791. nand->bbt_md = &bbt_mirror_descr;
  792. /* set up nand options */
  793. nand->options = NAND_NO_SUBPAGE_WRITE;
  794. nand->bbt_options = NAND_BBT_USE_FLASH;
  795. if (cspr & CSPR_PORT_SIZE_16) {
  796. nand->read_byte = fsl_ifc_read_byte16;
  797. nand->options |= NAND_BUSWIDTH_16;
  798. } else {
  799. nand->read_byte = fsl_ifc_read_byte;
  800. }
  801. nand->controller = &ifc_ctrl->controller;
  802. nand_set_controller_data(nand, priv);
  803. nand->ecc.read_page = fsl_ifc_read_page;
  804. nand->ecc.write_page = fsl_ifc_write_page;
  805. /* Hardware generates ECC per 512 Bytes */
  806. nand->ecc.size = 512;
  807. nand->ecc.bytes = 8;
  808. switch (csor & CSOR_NAND_PGS_MASK) {
  809. case CSOR_NAND_PGS_512:
  810. if (nand->options & NAND_BUSWIDTH_16) {
  811. layout = &oob_512_16bit_ecc4;
  812. } else {
  813. layout = &oob_512_8bit_ecc4;
  814. /* Avoid conflict with bad block marker */
  815. bbt_main_descr.offs = 0;
  816. bbt_mirror_descr.offs = 0;
  817. }
  818. nand->ecc.strength = 4;
  819. priv->bufnum_mask = 15;
  820. break;
  821. case CSOR_NAND_PGS_2K:
  822. layout = &oob_2048_ecc4;
  823. nand->ecc.strength = 4;
  824. priv->bufnum_mask = 3;
  825. break;
  826. case CSOR_NAND_PGS_4K:
  827. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  828. CSOR_NAND_ECC_MODE_4) {
  829. layout = &oob_4096_ecc4;
  830. nand->ecc.strength = 4;
  831. } else {
  832. layout = &oob_4096_ecc8;
  833. nand->ecc.strength = 8;
  834. nand->ecc.bytes = 16;
  835. }
  836. priv->bufnum_mask = 1;
  837. break;
  838. case CSOR_NAND_PGS_8K:
  839. if ((csor & CSOR_NAND_ECC_MODE_MASK) ==
  840. CSOR_NAND_ECC_MODE_4) {
  841. layout = &oob_8192_ecc4;
  842. nand->ecc.strength = 4;
  843. } else {
  844. layout = &oob_8192_ecc8;
  845. nand->ecc.strength = 8;
  846. nand->ecc.bytes = 16;
  847. }
  848. priv->bufnum_mask = 0;
  849. break;
  850. default:
  851. printf("ifc nand: bad csor %#x: bad page size\n", csor);
  852. return -ENODEV;
  853. }
  854. /* Must also set CSOR_NAND_ECC_ENC_EN if DEC_EN set */
  855. if (csor & CSOR_NAND_ECC_DEC_EN) {
  856. nand->ecc.mode = NAND_ECC_HW;
  857. nand->ecc.layout = layout;
  858. } else {
  859. nand->ecc.mode = NAND_ECC_SOFT;
  860. }
  861. ver = ifc_in32(&gregs->ifc_rev);
  862. if (ver >= FSL_IFC_V1_1_0)
  863. ret = fsl_ifc_sram_init(priv, ver);
  864. if (ret)
  865. return ret;
  866. if (ver >= FSL_IFC_V2_0_0)
  867. priv->bufnum_mask = (priv->bufnum_mask * 2) + 1;
  868. ret = nand_scan_ident(mtd, 1, NULL);
  869. if (ret)
  870. return ret;
  871. ret = nand_scan_tail(mtd);
  872. if (ret)
  873. return ret;
  874. ret = nand_register(devnum, mtd);
  875. if (ret)
  876. return ret;
  877. return 0;
  878. }
  879. #ifndef CONFIG_SYS_NAND_BASE_LIST
  880. #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
  881. #endif
  882. static unsigned long base_address[CONFIG_SYS_MAX_NAND_DEVICE] =
  883. CONFIG_SYS_NAND_BASE_LIST;
  884. void board_nand_init(void)
  885. {
  886. int i;
  887. for (i = 0; i < CONFIG_SYS_MAX_NAND_DEVICE; i++)
  888. fsl_ifc_chip_init(i, (u8 *)base_address[i]);
  889. }