cmd_nand.c 44 KB

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  1. /*
  2. * Driver for NAND support, Rick Bronson
  3. * borrowed heavily from:
  4. * (c) 1999 Machine Vision Holdings, Inc.
  5. * (c) 1999, 2000 David Woodhouse <dwmw2@infradead.org>
  6. */
  7. #include <common.h>
  8. #include <command.h>
  9. #include <malloc.h>
  10. #include <asm/io.h>
  11. #include <watchdog.h>
  12. #ifdef CONFIG_SHOW_BOOT_PROGRESS
  13. # include <status_led.h>
  14. # define SHOW_BOOT_PROGRESS(arg) show_boot_progress(arg)
  15. #else
  16. # define SHOW_BOOT_PROGRESS(arg)
  17. #endif
  18. #if (CONFIG_COMMANDS & CFG_CMD_NAND)
  19. #include <linux/mtd/nand.h>
  20. #include <linux/mtd/nand_ids.h>
  21. #include <jffs2/jffs2.h>
  22. #ifdef CONFIG_OMAP1510
  23. void archflashwp(void *archdata, int wp);
  24. #endif
  25. #define ROUND_DOWN(value,boundary) ((value) & (~((boundary)-1)))
  26. /*
  27. * Definition of the out of band configuration structure
  28. */
  29. struct nand_oob_config {
  30. int ecc_pos[6]; /* position of ECC bytes inside oob */
  31. int badblock_pos; /* position of bad block flag inside oob -1 = inactive */
  32. int eccvalid_pos; /* position of ECC valid flag inside oob -1 = inactive */
  33. } oob_config = { {0}, 0, 0};
  34. #undef NAND_DEBUG
  35. #undef PSYCHO_DEBUG
  36. /* ****************** WARNING *********************
  37. * When ALLOW_ERASE_BAD_DEBUG is non-zero the erase command will
  38. * erase (or at least attempt to erase) blocks that are marked
  39. * bad. This can be very handy if you are _sure_ that the block
  40. * is OK, say because you marked a good block bad to test bad
  41. * block handling and you are done testing, or if you have
  42. * accidentally marked blocks bad.
  43. *
  44. * Erasing factory marked bad blocks is a _bad_ idea. If the
  45. * erase succeeds there is no reliable way to find them again,
  46. * and attempting to program or erase bad blocks can affect
  47. * the data in _other_ (good) blocks.
  48. */
  49. #define ALLOW_ERASE_BAD_DEBUG 0
  50. #define CONFIG_MTD_NAND_ECC /* enable ECC */
  51. #define CONFIG_MTD_NAND_ECC_JFFS2
  52. /* bits for nand_rw() `cmd'; or together as needed */
  53. #define NANDRW_READ 0x01
  54. #define NANDRW_WRITE 0x00
  55. #define NANDRW_JFFS2 0x02
  56. #define NANDRW_JFFS2_SKIP 0x04
  57. /*
  58. * Function Prototypes
  59. */
  60. static void nand_print(struct nand_chip *nand);
  61. static int nand_rw (struct nand_chip* nand, int cmd,
  62. size_t start, size_t len,
  63. size_t * retlen, u_char * buf);
  64. static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean);
  65. static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
  66. size_t * retlen, u_char *buf, u_char *ecc_code);
  67. static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
  68. size_t * retlen, const u_char * buf, u_char * ecc_code);
  69. static void nand_print_bad(struct nand_chip *nand);
  70. static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
  71. size_t * retlen, u_char * buf);
  72. static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
  73. size_t * retlen, const u_char * buf);
  74. static int NanD_WaitReady(struct nand_chip *nand, int ale_wait);
  75. #ifdef CONFIG_MTD_NAND_ECC
  76. static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc);
  77. static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code);
  78. #endif
  79. struct nand_chip nand_dev_desc[CFG_MAX_NAND_DEVICE] = {{0}};
  80. /* Current NAND Device */
  81. static int curr_device = -1;
  82. /* ------------------------------------------------------------------------- */
  83. int do_nand (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  84. {
  85. int rcode = 0;
  86. switch (argc) {
  87. case 0:
  88. case 1:
  89. printf ("Usage:\n%s\n", cmdtp->usage);
  90. return 1;
  91. case 2:
  92. if (strcmp(argv[1],"info") == 0) {
  93. int i;
  94. putc ('\n');
  95. for (i=0; i<CFG_MAX_NAND_DEVICE; ++i) {
  96. if(nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN)
  97. continue; /* list only known devices */
  98. printf ("Device %d: ", i);
  99. nand_print(&nand_dev_desc[i]);
  100. }
  101. return 0;
  102. } else if (strcmp(argv[1],"device") == 0) {
  103. if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
  104. puts ("\nno devices available\n");
  105. return 1;
  106. }
  107. printf ("\nDevice %d: ", curr_device);
  108. nand_print(&nand_dev_desc[curr_device]);
  109. return 0;
  110. } else if (strcmp(argv[1],"bad") == 0) {
  111. if ((curr_device < 0) || (curr_device >= CFG_MAX_NAND_DEVICE)) {
  112. puts ("\nno devices available\n");
  113. return 1;
  114. }
  115. printf ("\nDevice %d bad blocks:\n", curr_device);
  116. nand_print_bad(&nand_dev_desc[curr_device]);
  117. return 0;
  118. }
  119. printf ("Usage:\n%s\n", cmdtp->usage);
  120. return 1;
  121. case 3:
  122. if (strcmp(argv[1],"device") == 0) {
  123. int dev = (int)simple_strtoul(argv[2], NULL, 10);
  124. printf ("\nDevice %d: ", dev);
  125. if (dev >= CFG_MAX_NAND_DEVICE) {
  126. puts ("unknown device\n");
  127. return 1;
  128. }
  129. nand_print(&nand_dev_desc[dev]);
  130. /*nand_print (dev);*/
  131. if (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN) {
  132. return 1;
  133. }
  134. curr_device = dev;
  135. puts ("... is now current device\n");
  136. return 0;
  137. }
  138. else if (strcmp(argv[1],"erase") == 0 && strcmp(argv[2], "clean") == 0) {
  139. struct nand_chip* nand = &nand_dev_desc[curr_device];
  140. ulong off = 0;
  141. ulong size = nand->totlen;
  142. int ret;
  143. printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
  144. curr_device, off, size);
  145. ret = nand_erase (nand, off, size, 1);
  146. printf("%s\n", ret ? "ERROR" : "OK");
  147. return ret;
  148. }
  149. printf ("Usage:\n%s\n", cmdtp->usage);
  150. return 1;
  151. default:
  152. /* at least 4 args */
  153. if (strncmp(argv[1], "read", 4) == 0 ||
  154. strncmp(argv[1], "write", 5) == 0) {
  155. ulong addr = simple_strtoul(argv[2], NULL, 16);
  156. ulong off = simple_strtoul(argv[3], NULL, 16);
  157. ulong size = simple_strtoul(argv[4], NULL, 16);
  158. int cmd = (strncmp(argv[1], "read", 4) == 0) ?
  159. NANDRW_READ : NANDRW_WRITE;
  160. int ret, total;
  161. char* cmdtail = strchr(argv[1], '.');
  162. if (cmdtail && !strncmp(cmdtail, ".oob", 2)) {
  163. /* read out-of-band data */
  164. if (cmd & NANDRW_READ) {
  165. ret = nand_read_oob(nand_dev_desc + curr_device,
  166. off, size, &total,
  167. (u_char*)addr);
  168. }
  169. else {
  170. ret = nand_write_oob(nand_dev_desc + curr_device,
  171. off, size, &total,
  172. (u_char*)addr);
  173. }
  174. return ret;
  175. }
  176. else if (cmdtail && !strncmp(cmdtail, ".jffs2", 2))
  177. cmd |= NANDRW_JFFS2; /* skip bad blocks */
  178. else if (cmdtail && !strncmp(cmdtail, ".jffs2s", 2)) {
  179. cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */
  180. if (cmd & NANDRW_READ)
  181. cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */
  182. }
  183. #ifdef SXNI855T
  184. /* need ".e" same as ".j" for compatibility with older units */
  185. else if (cmdtail && !strcmp(cmdtail, ".e"))
  186. cmd |= NANDRW_JFFS2; /* skip bad blocks */
  187. #endif
  188. else if (cmdtail) {
  189. printf ("Usage:\n%s\n", cmdtp->usage);
  190. return 1;
  191. }
  192. printf ("\nNAND %s: device %d offset %ld, size %ld ... ",
  193. (cmd & NANDRW_READ) ? "read" : "write",
  194. curr_device, off, size);
  195. ret = nand_rw(nand_dev_desc + curr_device, cmd, off, size,
  196. &total, (u_char*)addr);
  197. printf (" %d bytes %s: %s\n", total,
  198. (cmd & NANDRW_READ) ? "read" : "write",
  199. ret ? "ERROR" : "OK");
  200. return ret;
  201. } else if (strcmp(argv[1],"erase") == 0 &&
  202. (argc == 4 || strcmp("clean", argv[2]) == 0)) {
  203. int clean = argc == 5;
  204. ulong off = simple_strtoul(argv[2 + clean], NULL, 16);
  205. ulong size = simple_strtoul(argv[3 + clean], NULL, 16);
  206. int ret;
  207. printf ("\nNAND erase: device %d offset %ld, size %ld ... ",
  208. curr_device, off, size);
  209. ret = nand_erase (nand_dev_desc + curr_device, off, size, clean);
  210. printf("%s\n", ret ? "ERROR" : "OK");
  211. return ret;
  212. } else {
  213. printf ("Usage:\n%s\n", cmdtp->usage);
  214. rcode = 1;
  215. }
  216. return rcode;
  217. }
  218. }
  219. U_BOOT_CMD(
  220. nand, 5, 1, do_nand,
  221. "nand - NAND sub-system\n",
  222. "info - show available NAND devices\n"
  223. "nand device [dev] - show or set current device\n"
  224. "nand read[.jffs2[s]] addr off size\n"
  225. "nand write[.jffs2] addr off size - read/write `size' bytes starting\n"
  226. " at offset `off' to/from memory address `addr'\n"
  227. "nand erase [clean] [off size] - erase `size' bytes from\n"
  228. " offset `off' (entire device if not specified)\n"
  229. "nand bad - show bad blocks\n"
  230. "nand read.oob addr off size - read out-of-band data\n"
  231. "nand write.oob addr off size - read out-of-band data\n"
  232. );
  233. int do_nandboot (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[])
  234. {
  235. char *boot_device = NULL;
  236. char *ep;
  237. int dev;
  238. ulong cnt;
  239. ulong addr;
  240. ulong offset = 0;
  241. image_header_t *hdr;
  242. int rcode = 0;
  243. switch (argc) {
  244. case 1:
  245. addr = CFG_LOAD_ADDR;
  246. boot_device = getenv ("bootdevice");
  247. break;
  248. case 2:
  249. addr = simple_strtoul(argv[1], NULL, 16);
  250. boot_device = getenv ("bootdevice");
  251. break;
  252. case 3:
  253. addr = simple_strtoul(argv[1], NULL, 16);
  254. boot_device = argv[2];
  255. break;
  256. case 4:
  257. addr = simple_strtoul(argv[1], NULL, 16);
  258. boot_device = argv[2];
  259. offset = simple_strtoul(argv[3], NULL, 16);
  260. break;
  261. default:
  262. printf ("Usage:\n%s\n", cmdtp->usage);
  263. SHOW_BOOT_PROGRESS (-1);
  264. return 1;
  265. }
  266. if (!boot_device) {
  267. puts ("\n** No boot device **\n");
  268. SHOW_BOOT_PROGRESS (-1);
  269. return 1;
  270. }
  271. dev = simple_strtoul(boot_device, &ep, 16);
  272. if ((dev >= CFG_MAX_NAND_DEVICE) ||
  273. (nand_dev_desc[dev].ChipID == NAND_ChipID_UNKNOWN)) {
  274. printf ("\n** Device %d not available\n", dev);
  275. SHOW_BOOT_PROGRESS (-1);
  276. return 1;
  277. }
  278. printf ("\nLoading from device %d: %s at 0x%lx (offset 0x%lx)\n",
  279. dev, nand_dev_desc[dev].name, nand_dev_desc[dev].IO_ADDR,
  280. offset);
  281. if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset,
  282. SECTORSIZE, NULL, (u_char *)addr)) {
  283. printf ("** Read error on %d\n", dev);
  284. SHOW_BOOT_PROGRESS (-1);
  285. return 1;
  286. }
  287. hdr = (image_header_t *)addr;
  288. if (ntohl(hdr->ih_magic) == IH_MAGIC) {
  289. print_image_hdr (hdr);
  290. cnt = (ntohl(hdr->ih_size) + sizeof(image_header_t));
  291. cnt -= SECTORSIZE;
  292. } else {
  293. printf ("\n** Bad Magic Number 0x%x **\n", hdr->ih_magic);
  294. SHOW_BOOT_PROGRESS (-1);
  295. return 1;
  296. }
  297. if (nand_rw (nand_dev_desc + dev, NANDRW_READ, offset + SECTORSIZE, cnt,
  298. NULL, (u_char *)(addr+SECTORSIZE))) {
  299. printf ("** Read error on %d\n", dev);
  300. SHOW_BOOT_PROGRESS (-1);
  301. return 1;
  302. }
  303. /* Loading ok, update default load address */
  304. load_addr = addr;
  305. /* Check if we should attempt an auto-start */
  306. if (((ep = getenv("autostart")) != NULL) && (strcmp(ep,"yes") == 0)) {
  307. char *local_args[2];
  308. extern int do_bootm (cmd_tbl_t *, int, int, char *[]);
  309. local_args[0] = argv[0];
  310. local_args[1] = NULL;
  311. printf ("Automatic boot of image at addr 0x%08lx ...\n", addr);
  312. do_bootm (cmdtp, 0, 1, local_args);
  313. rcode = 1;
  314. }
  315. return rcode;
  316. }
  317. U_BOOT_CMD(
  318. nboot, 4, 1, do_nandboot,
  319. "nboot - boot from NAND device\n",
  320. "loadAddr dev\n"
  321. );
  322. /* returns 0 if block containing pos is OK:
  323. * valid erase block and
  324. * not marked bad, or no bad mark position is specified
  325. * returns 1 if marked bad or otherwise invalid
  326. */
  327. int check_block(struct nand_chip* nand, unsigned long pos)
  328. {
  329. int retlen;
  330. uint8_t oob_data;
  331. int page0 = pos & (-nand->erasesize);
  332. int page1 = page0 + nand->oobblock;
  333. int badpos = oob_config.badblock_pos;
  334. if (pos >= nand->totlen)
  335. return 1;
  336. if (badpos < 0)
  337. return 0; /* no way to check, assume OK */
  338. /* Note - bad block marker can be on first or second page */
  339. if (nand_read_oob(nand, page0 + badpos, 1, &retlen, &oob_data) ||
  340. oob_data != 0xff ||
  341. nand_read_oob(nand, page1 + badpos, 1, &retlen, &oob_data) ||
  342. oob_data != 0xff)
  343. return 1;
  344. return 0;
  345. }
  346. /* print bad blocks in NAND flash */
  347. static void nand_print_bad(struct nand_chip* nand)
  348. {
  349. unsigned long pos;
  350. for (pos = 0; pos < nand->totlen; pos += nand->erasesize) {
  351. if (check_block(nand, pos))
  352. printf(" 0x%8.8lx\n", pos);
  353. }
  354. puts("\n");
  355. }
  356. /* cmd: 0: NANDRW_WRITE write, fail on bad block
  357. * 1: NANDRW_READ read, fail on bad block
  358. * 2: NANDRW_WRITE | NANDRW_JFFS2 write, skip bad blocks
  359. * 3: NANDRW_READ | NANDRW_JFFS2 read, data all 0xff for bad blocks
  360. * 7: NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP read, skip bad blocks
  361. */
  362. static int nand_rw (struct nand_chip* nand, int cmd,
  363. size_t start, size_t len,
  364. size_t * retlen, u_char * buf)
  365. {
  366. int ret = 0, n, total = 0;
  367. char eccbuf[6];
  368. /* eblk (once set) is the start of the erase block containing the
  369. * data being processed.
  370. */
  371. unsigned long eblk = ~0; /* force mismatch on first pass */
  372. unsigned long erasesize = nand->erasesize;
  373. while (len) {
  374. if ((start & (-erasesize)) != eblk) {
  375. /* have crossed into new erase block, deal with
  376. * it if it is sure marked bad.
  377. */
  378. eblk = start & (-erasesize); /* start of block */
  379. if (check_block(nand, eblk)) {
  380. if (cmd == (NANDRW_READ | NANDRW_JFFS2)) {
  381. while (len > 0 &&
  382. start - eblk < erasesize) {
  383. *(buf++) = 0xff;
  384. ++start;
  385. ++total;
  386. --len;
  387. }
  388. continue;
  389. }
  390. else if (cmd == (NANDRW_READ | NANDRW_JFFS2 | NANDRW_JFFS2_SKIP)) {
  391. start += erasesize;
  392. continue;
  393. }
  394. else if (cmd == (NANDRW_WRITE | NANDRW_JFFS2)) {
  395. /* skip bad block */
  396. start += erasesize;
  397. continue;
  398. }
  399. else {
  400. ret = 1;
  401. break;
  402. }
  403. }
  404. }
  405. /* The ECC will not be calculated correctly if
  406. less than 512 is written or read */
  407. /* Is request at least 512 bytes AND it starts on a proper boundry */
  408. if((start != ROUND_DOWN(start, 0x200)) || (len < 0x200))
  409. printf("Warning block writes should be at least 512 bytes and start on a 512 byte boundry\n");
  410. if (cmd & NANDRW_READ)
  411. ret = nand_read_ecc(nand, start,
  412. min(len, eblk + erasesize - start),
  413. &n, (u_char*)buf, eccbuf);
  414. else
  415. ret = nand_write_ecc(nand, start,
  416. min(len, eblk + erasesize - start),
  417. &n, (u_char*)buf, eccbuf);
  418. if (ret)
  419. break;
  420. start += n;
  421. buf += n;
  422. total += n;
  423. len -= n;
  424. }
  425. if (retlen)
  426. *retlen = total;
  427. return ret;
  428. }
  429. static void nand_print(struct nand_chip *nand)
  430. {
  431. if (nand->numchips > 1) {
  432. printf("%s at 0x%lx,\n"
  433. "\t %d chips %s, size %d MB, \n"
  434. "\t total size %ld MB, sector size %ld kB\n",
  435. nand->name, nand->IO_ADDR, nand->numchips,
  436. nand->chips_name, 1 << (nand->chipshift - 20),
  437. nand->totlen >> 20, nand->erasesize >> 10);
  438. }
  439. else {
  440. printf("%s at 0x%lx (", nand->chips_name, nand->IO_ADDR);
  441. print_size(nand->totlen, ", ");
  442. print_size(nand->erasesize, " sector)\n");
  443. }
  444. }
  445. /* ------------------------------------------------------------------------- */
  446. static int NanD_WaitReady(struct nand_chip *nand, int ale_wait)
  447. {
  448. /* This is inline, to optimise the common case, where it's ready instantly */
  449. int ret = 0;
  450. #ifdef NAND_NO_RB /* in config file, shorter delays currently wrap accesses */
  451. if(ale_wait)
  452. NAND_WAIT_READY(nand); /* do the worst case 25us wait */
  453. else
  454. udelay(10);
  455. #else /* has functional r/b signal */
  456. NAND_WAIT_READY(nand);
  457. #endif
  458. return ret;
  459. }
  460. /* NanD_Command: Send a flash command to the flash chip */
  461. static inline int NanD_Command(struct nand_chip *nand, unsigned char command)
  462. {
  463. unsigned long nandptr = nand->IO_ADDR;
  464. /* Assert the CLE (Command Latch Enable) line to the flash chip */
  465. NAND_CTL_SETCLE(nandptr);
  466. /* Send the command */
  467. WRITE_NAND_COMMAND(command, nandptr);
  468. /* Lower the CLE line */
  469. NAND_CTL_CLRCLE(nandptr);
  470. #ifdef NAND_NO_RB
  471. if(command == NAND_CMD_RESET){
  472. u_char ret_val;
  473. NanD_Command(nand, NAND_CMD_STATUS);
  474. do{
  475. ret_val = READ_NAND(nandptr);/* wait till ready */
  476. } while((ret_val & 0x40) != 0x40);
  477. }
  478. #endif
  479. return NanD_WaitReady(nand, 0);
  480. }
  481. /* NanD_Address: Set the current address for the flash chip */
  482. static int NanD_Address(struct nand_chip *nand, int numbytes, unsigned long ofs)
  483. {
  484. unsigned long nandptr;
  485. int i;
  486. nandptr = nand->IO_ADDR;
  487. /* Assert the ALE (Address Latch Enable) line to the flash chip */
  488. NAND_CTL_SETALE(nandptr);
  489. /* Send the address */
  490. /* Devices with 256-byte page are addressed as:
  491. * Column (bits 0-7), Page (bits 8-15, 16-23, 24-31)
  492. * there is no device on the market with page256
  493. * and more than 24 bits.
  494. * Devices with 512-byte page are addressed as:
  495. * Column (bits 0-7), Page (bits 9-16, 17-24, 25-31)
  496. * 25-31 is sent only if the chip support it.
  497. * bit 8 changes the read command to be sent
  498. * (NAND_CMD_READ0 or NAND_CMD_READ1).
  499. */
  500. if (numbytes == ADDR_COLUMN || numbytes == ADDR_COLUMN_PAGE)
  501. WRITE_NAND_ADDRESS(ofs, nandptr);
  502. ofs = ofs >> nand->page_shift;
  503. if (numbytes == ADDR_PAGE || numbytes == ADDR_COLUMN_PAGE)
  504. for (i = 0; i < nand->pageadrlen; i++, ofs = ofs >> 8)
  505. WRITE_NAND_ADDRESS(ofs, nandptr);
  506. /* Lower the ALE line */
  507. NAND_CTL_CLRALE(nandptr);
  508. /* Wait for the chip to respond */
  509. return NanD_WaitReady(nand, 1);
  510. }
  511. /* NanD_SelectChip: Select a given flash chip within the current floor */
  512. static inline int NanD_SelectChip(struct nand_chip *nand, int chip)
  513. {
  514. /* Wait for it to be ready */
  515. return NanD_WaitReady(nand, 0);
  516. }
  517. /* NanD_IdentChip: Identify a given NAND chip given {floor,chip} */
  518. static int NanD_IdentChip(struct nand_chip *nand, int floor, int chip)
  519. {
  520. int mfr, id, i;
  521. NAND_ENABLE_CE(nand); /* set pin low */
  522. /* Reset the chip */
  523. if (NanD_Command(nand, NAND_CMD_RESET)) {
  524. #ifdef NAND_DEBUG
  525. printf("NanD_Command (reset) for %d,%d returned true\n",
  526. floor, chip);
  527. #endif
  528. NAND_DISABLE_CE(nand); /* set pin high */
  529. return 0;
  530. }
  531. /* Read the NAND chip ID: 1. Send ReadID command */
  532. if (NanD_Command(nand, NAND_CMD_READID)) {
  533. #ifdef NAND_DEBUG
  534. printf("NanD_Command (ReadID) for %d,%d returned true\n",
  535. floor, chip);
  536. #endif
  537. NAND_DISABLE_CE(nand); /* set pin high */
  538. return 0;
  539. }
  540. /* Read the NAND chip ID: 2. Send address byte zero */
  541. NanD_Address(nand, ADDR_COLUMN, 0);
  542. /* Read the manufacturer and device id codes from the device */
  543. mfr = READ_NAND(nand->IO_ADDR);
  544. id = READ_NAND(nand->IO_ADDR);
  545. NAND_DISABLE_CE(nand); /* set pin high */
  546. /* No response - return failure */
  547. if (mfr == 0xff || mfr == 0) {
  548. #ifdef NAND_DEBUG
  549. printf("NanD_Command (ReadID) got %d %d\n", mfr, id);
  550. #endif
  551. return 0;
  552. }
  553. /* Check it's the same as the first chip we identified.
  554. * M-Systems say that any given nand_chip device should only
  555. * contain _one_ type of flash part, although that's not a
  556. * hardware restriction. */
  557. if (nand->mfr) {
  558. if (nand->mfr == mfr && nand->id == id)
  559. return 1; /* This is another the same the first */
  560. else
  561. printf("Flash chip at floor %d, chip %d is different:\n",
  562. floor, chip);
  563. }
  564. /* Print and store the manufacturer and ID codes. */
  565. for (i = 0; nand_flash_ids[i].name != NULL; i++) {
  566. if (mfr == nand_flash_ids[i].manufacture_id &&
  567. id == nand_flash_ids[i].model_id) {
  568. #ifdef NAND_DEBUG
  569. printf("Flash chip found:\n\t Manufacturer ID: 0x%2.2X, "
  570. "Chip ID: 0x%2.2X (%s)\n", mfr, id,
  571. nand_flash_ids[i].name);
  572. #endif
  573. if (!nand->mfr) {
  574. nand->mfr = mfr;
  575. nand->id = id;
  576. nand->chipshift =
  577. nand_flash_ids[i].chipshift;
  578. nand->page256 = nand_flash_ids[i].page256;
  579. nand->eccsize = 256;
  580. if (nand->page256) {
  581. nand->oobblock = 256;
  582. nand->oobsize = 8;
  583. nand->page_shift = 8;
  584. } else {
  585. nand->oobblock = 512;
  586. nand->oobsize = 16;
  587. nand->page_shift = 9;
  588. }
  589. nand->pageadrlen =
  590. nand_flash_ids[i].pageadrlen;
  591. nand->erasesize =
  592. nand_flash_ids[i].erasesize;
  593. nand->chips_name =
  594. nand_flash_ids[i].name;
  595. return 1;
  596. }
  597. return 0;
  598. }
  599. }
  600. #ifdef NAND_DEBUG
  601. /* We haven't fully identified the chip. Print as much as we know. */
  602. printf("Unknown flash chip found: %2.2X %2.2X\n",
  603. id, mfr);
  604. #endif
  605. return 0;
  606. }
  607. /* NanD_ScanChips: Find all NAND chips present in a nand_chip, and identify them */
  608. static void NanD_ScanChips(struct nand_chip *nand)
  609. {
  610. int floor, chip;
  611. int numchips[NAND_MAX_FLOORS];
  612. int maxchips = NAND_MAX_CHIPS;
  613. int ret = 1;
  614. nand->numchips = 0;
  615. nand->mfr = 0;
  616. nand->id = 0;
  617. /* For each floor, find the number of valid chips it contains */
  618. for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
  619. ret = 1;
  620. numchips[floor] = 0;
  621. for (chip = 0; chip < maxchips && ret != 0; chip++) {
  622. ret = NanD_IdentChip(nand, floor, chip);
  623. if (ret) {
  624. numchips[floor]++;
  625. nand->numchips++;
  626. }
  627. }
  628. }
  629. /* If there are none at all that we recognise, bail */
  630. if (!nand->numchips) {
  631. #ifdef NAND_DEBUG
  632. puts ("No NAND flash chips recognised.\n");
  633. #endif
  634. return;
  635. }
  636. /* Allocate an array to hold the information for each chip */
  637. nand->chips = malloc(sizeof(struct Nand) * nand->numchips);
  638. if (!nand->chips) {
  639. puts ("No memory for allocating chip info structures\n");
  640. return;
  641. }
  642. ret = 0;
  643. /* Fill out the chip array with {floor, chipno} for each
  644. * detected chip in the device. */
  645. for (floor = 0; floor < NAND_MAX_FLOORS; floor++) {
  646. for (chip = 0; chip < numchips[floor]; chip++) {
  647. nand->chips[ret].floor = floor;
  648. nand->chips[ret].chip = chip;
  649. nand->chips[ret].curadr = 0;
  650. nand->chips[ret].curmode = 0x50;
  651. ret++;
  652. }
  653. }
  654. /* Calculate and print the total size of the device */
  655. nand->totlen = nand->numchips * (1 << nand->chipshift);
  656. #ifdef NAND_DEBUG
  657. printf("%d flash chips found. Total nand_chip size: %ld MB\n",
  658. nand->numchips, nand->totlen >> 20);
  659. #endif
  660. }
  661. /* we need to be fast here, 1 us per read translates to 1 second per meg */
  662. static void NanD_ReadBuf(struct nand_chip *nand, u_char *data_buf, int cntr)
  663. {
  664. unsigned long nandptr = nand->IO_ADDR;
  665. while (cntr >= 16) {
  666. *data_buf++ = READ_NAND(nandptr);
  667. *data_buf++ = READ_NAND(nandptr);
  668. *data_buf++ = READ_NAND(nandptr);
  669. *data_buf++ = READ_NAND(nandptr);
  670. *data_buf++ = READ_NAND(nandptr);
  671. *data_buf++ = READ_NAND(nandptr);
  672. *data_buf++ = READ_NAND(nandptr);
  673. *data_buf++ = READ_NAND(nandptr);
  674. *data_buf++ = READ_NAND(nandptr);
  675. *data_buf++ = READ_NAND(nandptr);
  676. *data_buf++ = READ_NAND(nandptr);
  677. *data_buf++ = READ_NAND(nandptr);
  678. *data_buf++ = READ_NAND(nandptr);
  679. *data_buf++ = READ_NAND(nandptr);
  680. *data_buf++ = READ_NAND(nandptr);
  681. *data_buf++ = READ_NAND(nandptr);
  682. cntr -= 16;
  683. }
  684. while (cntr > 0) {
  685. *data_buf++ = READ_NAND(nandptr);
  686. cntr--;
  687. }
  688. }
  689. /*
  690. * NAND read with ECC
  691. */
  692. static int nand_read_ecc(struct nand_chip *nand, size_t start, size_t len,
  693. size_t * retlen, u_char *buf, u_char *ecc_code)
  694. {
  695. int col, page;
  696. int ecc_status = 0;
  697. #ifdef CONFIG_MTD_NAND_ECC
  698. int j;
  699. int ecc_failed = 0;
  700. u_char *data_poi;
  701. u_char ecc_calc[6];
  702. #endif
  703. /* Do not allow reads past end of device */
  704. if ((start + len) > nand->totlen) {
  705. printf ("%s: Attempt read beyond end of device %x %x %x\n", __FUNCTION__, (uint) start, (uint) len, (uint) nand->totlen);
  706. *retlen = 0;
  707. return -1;
  708. }
  709. /* First we calculate the starting page */
  710. /*page = shr(start, nand->page_shift);*/
  711. page = start >> nand->page_shift;
  712. /* Get raw starting column */
  713. col = start & (nand->oobblock - 1);
  714. /* Initialize return value */
  715. *retlen = 0;
  716. /* Select the NAND device */
  717. NAND_ENABLE_CE(nand); /* set pin low */
  718. /* Loop until all data read */
  719. while (*retlen < len) {
  720. #ifdef CONFIG_MTD_NAND_ECC
  721. /* Do we have this page in cache ? */
  722. if (nand->cache_page == page)
  723. goto readdata;
  724. /* Send the read command */
  725. NanD_Command(nand, NAND_CMD_READ0);
  726. NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
  727. /* Read in a page + oob data */
  728. NanD_ReadBuf(nand, nand->data_buf, nand->oobblock + nand->oobsize);
  729. /* copy data into cache, for read out of cache and if ecc fails */
  730. if (nand->data_cache)
  731. memcpy (nand->data_cache, nand->data_buf, nand->oobblock + nand->oobsize);
  732. /* Pick the ECC bytes out of the oob data */
  733. for (j = 0; j < 6; j++)
  734. ecc_code[j] = nand->data_buf[(nand->oobblock + oob_config.ecc_pos[j])];
  735. /* Calculate the ECC and verify it */
  736. /* If block was not written with ECC, skip ECC */
  737. if (oob_config.eccvalid_pos != -1 &&
  738. (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0x0f) != 0x0f) {
  739. nand_calculate_ecc (&nand->data_buf[0], &ecc_calc[0]);
  740. switch (nand_correct_data (&nand->data_buf[0], &ecc_code[0], &ecc_calc[0])) {
  741. case -1:
  742. printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
  743. ecc_failed++;
  744. break;
  745. case 1:
  746. case 2: /* transfer ECC corrected data to cache */
  747. if (nand->data_cache)
  748. memcpy (nand->data_cache, nand->data_buf, 256);
  749. break;
  750. }
  751. }
  752. if (oob_config.eccvalid_pos != -1 &&
  753. nand->oobblock == 512 && (nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] & 0xf0) != 0xf0) {
  754. nand_calculate_ecc (&nand->data_buf[256], &ecc_calc[3]);
  755. switch (nand_correct_data (&nand->data_buf[256], &ecc_code[3], &ecc_calc[3])) {
  756. case -1:
  757. printf ("%s: Failed ECC read, page 0x%08x\n", __FUNCTION__, page);
  758. ecc_failed++;
  759. break;
  760. case 1:
  761. case 2: /* transfer ECC corrected data to cache */
  762. if (nand->data_cache)
  763. memcpy (&nand->data_cache[256], &nand->data_buf[256], 256);
  764. break;
  765. }
  766. }
  767. readdata:
  768. /* Read the data from ECC data buffer into return buffer */
  769. data_poi = (nand->data_cache) ? nand->data_cache : nand->data_buf;
  770. data_poi += col;
  771. if ((*retlen + (nand->oobblock - col)) >= len) {
  772. memcpy (buf + *retlen, data_poi, len - *retlen);
  773. *retlen = len;
  774. } else {
  775. memcpy (buf + *retlen, data_poi, nand->oobblock - col);
  776. *retlen += nand->oobblock - col;
  777. }
  778. /* Set cache page address, invalidate, if ecc_failed */
  779. nand->cache_page = (nand->data_cache && !ecc_failed) ? page : -1;
  780. ecc_status += ecc_failed;
  781. ecc_failed = 0;
  782. #else
  783. /* Send the read command */
  784. NanD_Command(nand, NAND_CMD_READ0);
  785. NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
  786. /* Read the data directly into the return buffer */
  787. if ((*retlen + (nand->oobblock - col)) >= len) {
  788. NanD_ReadBuf(nand, buf + *retlen, len - *retlen);
  789. *retlen = len;
  790. /* We're done */
  791. continue;
  792. } else {
  793. NanD_ReadBuf(nand, buf + *retlen, nand->oobblock - col);
  794. *retlen += nand->oobblock - col;
  795. }
  796. #endif
  797. /* For subsequent reads align to page boundary. */
  798. col = 0;
  799. /* Increment page address */
  800. page++;
  801. }
  802. /* De-select the NAND device */
  803. NAND_DISABLE_CE(nand); /* set pin high */
  804. /*
  805. * Return success, if no ECC failures, else -EIO
  806. * fs driver will take care of that, because
  807. * retlen == desired len and result == -EIO
  808. */
  809. return ecc_status ? -1 : 0;
  810. }
  811. /*
  812. * Nand_page_program function is used for write and writev !
  813. */
  814. static int nand_write_page (struct nand_chip *nand,
  815. int page, int col, int last, u_char * ecc_code)
  816. {
  817. int i;
  818. unsigned long nandptr = nand->IO_ADDR;
  819. #ifdef CONFIG_MTD_NAND_ECC
  820. #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
  821. int ecc_bytes = (nand->oobblock == 512) ? 6 : 3;
  822. #endif
  823. #endif
  824. /* pad oob area */
  825. for (i = nand->oobblock; i < nand->oobblock + nand->oobsize; i++)
  826. nand->data_buf[i] = 0xff;
  827. #ifdef CONFIG_MTD_NAND_ECC
  828. /* Zero out the ECC array */
  829. for (i = 0; i < 6; i++)
  830. ecc_code[i] = 0x00;
  831. /* Read back previous written data, if col > 0 */
  832. if (col) {
  833. NanD_Command(nand, NAND_CMD_READ0);
  834. NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
  835. for (i = 0; i < col; i++)
  836. nand->data_buf[i] = READ_NAND (nandptr);
  837. }
  838. /* Calculate and write the ECC if we have enough data */
  839. if ((col < nand->eccsize) && (last >= nand->eccsize)) {
  840. nand_calculate_ecc (&nand->data_buf[0], &(ecc_code[0]));
  841. for (i = 0; i < 3; i++)
  842. nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
  843. if (oob_config.eccvalid_pos != -1)
  844. nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] = 0xf0;
  845. }
  846. /* Calculate and write the second ECC if we have enough data */
  847. if ((nand->oobblock == 512) && (last == nand->oobblock)) {
  848. nand_calculate_ecc (&nand->data_buf[256], &(ecc_code[3]));
  849. for (i = 3; i < 6; i++)
  850. nand->data_buf[(nand->oobblock + oob_config.ecc_pos[i])] = ecc_code[i];
  851. if (oob_config.eccvalid_pos != -1)
  852. nand->data_buf[nand->oobblock + oob_config.eccvalid_pos] &= 0x0f;
  853. }
  854. #endif
  855. /* Prepad for partial page programming !!! */
  856. for (i = 0; i < col; i++)
  857. nand->data_buf[i] = 0xff;
  858. /* Postpad for partial page programming !!! oob is already padded */
  859. for (i = last; i < nand->oobblock; i++)
  860. nand->data_buf[i] = 0xff;
  861. /* Send command to begin auto page programming */
  862. NanD_Command(nand, NAND_CMD_READ0);
  863. NanD_Command(nand, NAND_CMD_SEQIN);
  864. NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
  865. /* Write out complete page of data */
  866. for (i = 0; i < (nand->oobblock + nand->oobsize); i++)
  867. WRITE_NAND(nand->data_buf[i], nand->IO_ADDR);
  868. /* Send command to actually program the data */
  869. NanD_Command(nand, NAND_CMD_PAGEPROG);
  870. NanD_Command(nand, NAND_CMD_STATUS);
  871. #ifdef NAND_NO_RB
  872. { u_char ret_val;
  873. do{
  874. ret_val = READ_NAND(nandptr); /* wait till ready */
  875. } while((ret_val & 0x40) != 0x40);
  876. }
  877. #endif
  878. /* See if device thinks it succeeded */
  879. if (READ_NAND(nand->IO_ADDR) & 0x01) {
  880. printf ("%s: Failed write, page 0x%08x, ", __FUNCTION__, page);
  881. return -1;
  882. }
  883. #ifdef CONFIG_MTD_NAND_VERIFY_WRITE
  884. /*
  885. * The NAND device assumes that it is always writing to
  886. * a cleanly erased page. Hence, it performs its internal
  887. * write verification only on bits that transitioned from
  888. * 1 to 0. The device does NOT verify the whole page on a
  889. * byte by byte basis. It is possible that the page was
  890. * not completely erased or the page is becoming unusable
  891. * due to wear. The read with ECC would catch the error
  892. * later when the ECC page check fails, but we would rather
  893. * catch it early in the page write stage. Better to write
  894. * no data than invalid data.
  895. */
  896. /* Send command to read back the page */
  897. if (col < nand->eccsize)
  898. NanD_Command(nand, NAND_CMD_READ0);
  899. else
  900. NanD_Command(nand, NAND_CMD_READ1);
  901. NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
  902. /* Loop through and verify the data */
  903. for (i = col; i < last; i++) {
  904. if (nand->data_buf[i] != readb (nand->IO_ADDR)) {
  905. printf ("%s: Failed write verify, page 0x%08x ", __FUNCTION__, page);
  906. return -1;
  907. }
  908. }
  909. #ifdef CONFIG_MTD_NAND_ECC
  910. /*
  911. * We also want to check that the ECC bytes wrote
  912. * correctly for the same reasons stated above.
  913. */
  914. NanD_Command(nand, NAND_CMD_READOOB);
  915. NanD_Address(nand, ADDR_COLUMN_PAGE, (page << nand->page_shift) + col);
  916. for (i = 0; i < nand->oobsize; i++)
  917. nand->data_buf[i] = readb (nand->IO_ADDR);
  918. for (i = 0; i < ecc_bytes; i++) {
  919. if ((nand->data_buf[(oob_config.ecc_pos[i])] != ecc_code[i]) && ecc_code[i]) {
  920. printf ("%s: Failed ECC write "
  921. "verify, page 0x%08x, " "%6i bytes were succesful\n", __FUNCTION__, page, i);
  922. return -1;
  923. }
  924. }
  925. #endif
  926. #endif
  927. return 0;
  928. }
  929. static int nand_write_ecc (struct nand_chip* nand, size_t to, size_t len,
  930. size_t * retlen, const u_char * buf, u_char * ecc_code)
  931. {
  932. int i, page, col, cnt, ret = 0;
  933. /* Do not allow write past end of device */
  934. if ((to + len) > nand->totlen) {
  935. printf ("%s: Attempt to write past end of page\n", __FUNCTION__);
  936. return -1;
  937. }
  938. /* Shift to get page */
  939. page = ((int) to) >> nand->page_shift;
  940. /* Get the starting column */
  941. col = to & (nand->oobblock - 1);
  942. /* Initialize return length value */
  943. *retlen = 0;
  944. /* Select the NAND device */
  945. #ifdef CONFIG_OMAP1510
  946. archflashwp(0,0);
  947. #endif
  948. NAND_ENABLE_CE(nand); /* set pin low */
  949. /* Check the WP bit */
  950. NanD_Command(nand, NAND_CMD_STATUS);
  951. if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
  952. printf ("%s: Device is write protected!!!\n", __FUNCTION__);
  953. ret = -1;
  954. goto out;
  955. }
  956. /* Loop until all data is written */
  957. while (*retlen < len) {
  958. /* Invalidate cache, if we write to this page */
  959. if (nand->cache_page == page)
  960. nand->cache_page = -1;
  961. /* Write data into buffer */
  962. if ((col + len) >= nand->oobblock)
  963. for (i = col, cnt = 0; i < nand->oobblock; i++, cnt++)
  964. nand->data_buf[i] = buf[(*retlen + cnt)];
  965. else
  966. for (i = col, cnt = 0; cnt < (len - *retlen); i++, cnt++)
  967. nand->data_buf[i] = buf[(*retlen + cnt)];
  968. /* We use the same function for write and writev !) */
  969. ret = nand_write_page (nand, page, col, i, ecc_code);
  970. if (ret)
  971. goto out;
  972. /* Next data start at page boundary */
  973. col = 0;
  974. /* Update written bytes count */
  975. *retlen += cnt;
  976. /* Increment page address */
  977. page++;
  978. }
  979. /* Return happy */
  980. *retlen = len;
  981. out:
  982. /* De-select the NAND device */
  983. NAND_DISABLE_CE(nand); /* set pin high */
  984. #ifdef CONFIG_OMAP1510
  985. archflashwp(0,1);
  986. #endif
  987. return ret;
  988. }
  989. /* read from the 16 bytes of oob data that correspond to a 512 byte
  990. * page or 2 256-byte pages.
  991. */
  992. static int nand_read_oob(struct nand_chip* nand, size_t ofs, size_t len,
  993. size_t * retlen, u_char * buf)
  994. {
  995. int len256 = 0;
  996. struct Nand *mychip;
  997. int ret = 0;
  998. mychip = &nand->chips[ofs >> nand->chipshift];
  999. /* update address for 2M x 8bit devices. OOB starts on the second */
  1000. /* page to maintain compatibility with nand_read_ecc. */
  1001. if (nand->page256) {
  1002. if (!(ofs & 0x8))
  1003. ofs += 0x100;
  1004. else
  1005. ofs -= 0x8;
  1006. }
  1007. NAND_ENABLE_CE(nand); /* set pin low */
  1008. NanD_Command(nand, NAND_CMD_READOOB);
  1009. NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
  1010. /* treat crossing 8-byte OOB data for 2M x 8bit devices */
  1011. /* Note: datasheet says it should automaticaly wrap to the */
  1012. /* next OOB block, but it didn't work here. mf. */
  1013. if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
  1014. len256 = (ofs | 0x7) + 1 - ofs;
  1015. NanD_ReadBuf(nand, buf, len256);
  1016. NanD_Command(nand, NAND_CMD_READOOB);
  1017. NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
  1018. }
  1019. NanD_ReadBuf(nand, &buf[len256], len - len256);
  1020. *retlen = len;
  1021. /* Reading the full OOB data drops us off of the end of the page,
  1022. * causing the flash device to go into busy mode, so we need
  1023. * to wait until ready 11.4.1 and Toshiba TC58256FT nands */
  1024. ret = NanD_WaitReady(nand, 1);
  1025. NAND_DISABLE_CE(nand); /* set pin high */
  1026. return ret;
  1027. }
  1028. /* write to the 16 bytes of oob data that correspond to a 512 byte
  1029. * page or 2 256-byte pages.
  1030. */
  1031. static int nand_write_oob(struct nand_chip* nand, size_t ofs, size_t len,
  1032. size_t * retlen, const u_char * buf)
  1033. {
  1034. int len256 = 0;
  1035. int i;
  1036. unsigned long nandptr = nand->IO_ADDR;
  1037. #ifdef PSYCHO_DEBUG
  1038. printf("nand_write_oob(%lx, %d): %2.2X %2.2X %2.2X %2.2X ... %2.2X %2.2X .. %2.2X %2.2X\n",
  1039. (long)ofs, len, buf[0], buf[1], buf[2], buf[3],
  1040. buf[8], buf[9], buf[14],buf[15]);
  1041. #endif
  1042. NAND_ENABLE_CE(nand); /* set pin low to enable chip */
  1043. /* Reset the chip */
  1044. NanD_Command(nand, NAND_CMD_RESET);
  1045. /* issue the Read2 command to set the pointer to the Spare Data Area. */
  1046. NanD_Command(nand, NAND_CMD_READOOB);
  1047. NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
  1048. /* update address for 2M x 8bit devices. OOB starts on the second */
  1049. /* page to maintain compatibility with nand_read_ecc. */
  1050. if (nand->page256) {
  1051. if (!(ofs & 0x8))
  1052. ofs += 0x100;
  1053. else
  1054. ofs -= 0x8;
  1055. }
  1056. /* issue the Serial Data In command to initial the Page Program process */
  1057. NanD_Command(nand, NAND_CMD_SEQIN);
  1058. NanD_Address(nand, ADDR_COLUMN_PAGE, ofs);
  1059. /* treat crossing 8-byte OOB data for 2M x 8bit devices */
  1060. /* Note: datasheet says it should automaticaly wrap to the */
  1061. /* next OOB block, but it didn't work here. mf. */
  1062. if (nand->page256 && ofs + len > (ofs | 0x7) + 1) {
  1063. len256 = (ofs | 0x7) + 1 - ofs;
  1064. for (i = 0; i < len256; i++)
  1065. WRITE_NAND(buf[i], nandptr);
  1066. NanD_Command(nand, NAND_CMD_PAGEPROG);
  1067. NanD_Command(nand, NAND_CMD_STATUS);
  1068. #ifdef NAND_NO_RB
  1069. { u_char ret_val;
  1070. do{
  1071. ret_val = READ_NAND(nandptr); /* wait till ready */
  1072. }while((ret_val & 0x40) != 0x40);
  1073. }
  1074. #endif
  1075. if (READ_NAND(nandptr) & 1) {
  1076. puts ("Error programming oob data\n");
  1077. /* There was an error */
  1078. NAND_DISABLE_CE(nand); /* set pin high */
  1079. *retlen = 0;
  1080. return -1;
  1081. }
  1082. NanD_Command(nand, NAND_CMD_SEQIN);
  1083. NanD_Address(nand, ADDR_COLUMN_PAGE, ofs & (~0x1ff));
  1084. }
  1085. for (i = len256; i < len; i++)
  1086. WRITE_NAND(buf[i], nandptr);
  1087. NanD_Command(nand, NAND_CMD_PAGEPROG);
  1088. NanD_Command(nand, NAND_CMD_STATUS);
  1089. #ifdef NAND_NO_RB
  1090. { u_char ret_val;
  1091. do{
  1092. ret_val = READ_NAND(nandptr); /* wait till ready */
  1093. } while((ret_val & 0x40) != 0x40);
  1094. }
  1095. #endif
  1096. if (READ_NAND(nandptr) & 1) {
  1097. puts ("Error programming oob data\n");
  1098. /* There was an error */
  1099. NAND_DISABLE_CE(nand); /* set pin high */
  1100. *retlen = 0;
  1101. return -1;
  1102. }
  1103. NAND_DISABLE_CE(nand); /* set pin high */
  1104. *retlen = len;
  1105. return 0;
  1106. }
  1107. static int nand_erase(struct nand_chip* nand, size_t ofs, size_t len, int clean)
  1108. {
  1109. /* This is defined as a structure so it will work on any system
  1110. * using native endian jffs2 (the default).
  1111. */
  1112. static struct jffs2_unknown_node clean_marker = {
  1113. JFFS2_MAGIC_BITMASK,
  1114. JFFS2_NODETYPE_CLEANMARKER,
  1115. 8 /* 8 bytes in this node */
  1116. };
  1117. unsigned long nandptr;
  1118. struct Nand *mychip;
  1119. int ret = 0;
  1120. if (ofs & (nand->erasesize-1) || len & (nand->erasesize-1)) {
  1121. printf ("Offset and size must be sector aligned, erasesize = %d\n",
  1122. (int) nand->erasesize);
  1123. return -1;
  1124. }
  1125. nandptr = nand->IO_ADDR;
  1126. /* Select the NAND device */
  1127. #ifdef CONFIG_OMAP1510
  1128. archflashwp(0,0);
  1129. #endif
  1130. NAND_ENABLE_CE(nand); /* set pin low */
  1131. /* Check the WP bit */
  1132. NanD_Command(nand, NAND_CMD_STATUS);
  1133. if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
  1134. printf ("nand_write_ecc: Device is write protected!!!\n");
  1135. ret = -1;
  1136. goto out;
  1137. }
  1138. /* Check the WP bit */
  1139. NanD_Command(nand, NAND_CMD_STATUS);
  1140. if (!(READ_NAND(nand->IO_ADDR) & 0x80)) {
  1141. printf ("%s: Device is write protected!!!\n", __FUNCTION__);
  1142. ret = -1;
  1143. goto out;
  1144. }
  1145. /* FIXME: Do nand in the background. Use timers or schedule_task() */
  1146. while(len) {
  1147. /*mychip = &nand->chips[shr(ofs, nand->chipshift)];*/
  1148. mychip = &nand->chips[ofs >> nand->chipshift];
  1149. /* always check for bad block first, genuine bad blocks
  1150. * should _never_ be erased.
  1151. */
  1152. if (ALLOW_ERASE_BAD_DEBUG || !check_block(nand, ofs)) {
  1153. /* Select the NAND device */
  1154. NAND_ENABLE_CE(nand); /* set pin low */
  1155. NanD_Command(nand, NAND_CMD_ERASE1);
  1156. NanD_Address(nand, ADDR_PAGE, ofs);
  1157. NanD_Command(nand, NAND_CMD_ERASE2);
  1158. NanD_Command(nand, NAND_CMD_STATUS);
  1159. #ifdef NAND_NO_RB
  1160. { u_char ret_val;
  1161. do{
  1162. ret_val = READ_NAND(nandptr); /* wait till ready */
  1163. } while((ret_val & 0x40) != 0x40);
  1164. }
  1165. #endif
  1166. if (READ_NAND(nandptr) & 1) {
  1167. printf ("%s: Error erasing at 0x%lx\n",
  1168. __FUNCTION__, (long)ofs);
  1169. /* There was an error */
  1170. ret = -1;
  1171. goto out;
  1172. }
  1173. if (clean) {
  1174. int n; /* return value not used */
  1175. int p, l;
  1176. /* clean marker position and size depend
  1177. * on the page size, since 256 byte pages
  1178. * only have 8 bytes of oob data
  1179. */
  1180. if (nand->page256) {
  1181. p = NAND_JFFS2_OOB8_FSDAPOS;
  1182. l = NAND_JFFS2_OOB8_FSDALEN;
  1183. }
  1184. else {
  1185. p = NAND_JFFS2_OOB16_FSDAPOS;
  1186. l = NAND_JFFS2_OOB16_FSDALEN;
  1187. }
  1188. ret = nand_write_oob(nand, ofs + p, l, &n,
  1189. (u_char *)&clean_marker);
  1190. /* quit here if write failed */
  1191. if (ret)
  1192. goto out;
  1193. }
  1194. }
  1195. ofs += nand->erasesize;
  1196. len -= nand->erasesize;
  1197. }
  1198. out:
  1199. /* De-select the NAND device */
  1200. NAND_DISABLE_CE(nand); /* set pin high */
  1201. #ifdef CONFIG_OMAP1510
  1202. archflashwp(0,1);
  1203. #endif
  1204. return ret;
  1205. }
  1206. static inline int nandcheck(unsigned long potential, unsigned long physadr)
  1207. {
  1208. return 0;
  1209. }
  1210. unsigned long nand_probe(unsigned long physadr)
  1211. {
  1212. struct nand_chip *nand = NULL;
  1213. int i = 0, ChipID = 1;
  1214. #ifdef CONFIG_MTD_NAND_ECC_JFFS2
  1215. oob_config.ecc_pos[0] = NAND_JFFS2_OOB_ECCPOS0;
  1216. oob_config.ecc_pos[1] = NAND_JFFS2_OOB_ECCPOS1;
  1217. oob_config.ecc_pos[2] = NAND_JFFS2_OOB_ECCPOS2;
  1218. oob_config.ecc_pos[3] = NAND_JFFS2_OOB_ECCPOS3;
  1219. oob_config.ecc_pos[4] = NAND_JFFS2_OOB_ECCPOS4;
  1220. oob_config.ecc_pos[5] = NAND_JFFS2_OOB_ECCPOS5;
  1221. oob_config.eccvalid_pos = 4;
  1222. #else
  1223. oob_config.ecc_pos[0] = NAND_NOOB_ECCPOS0;
  1224. oob_config.ecc_pos[1] = NAND_NOOB_ECCPOS1;
  1225. oob_config.ecc_pos[2] = NAND_NOOB_ECCPOS2;
  1226. oob_config.ecc_pos[3] = NAND_NOOB_ECCPOS3;
  1227. oob_config.ecc_pos[4] = NAND_NOOB_ECCPOS4;
  1228. oob_config.ecc_pos[5] = NAND_NOOB_ECCPOS5;
  1229. oob_config.eccvalid_pos = NAND_NOOB_ECCVPOS;
  1230. #endif
  1231. oob_config.badblock_pos = 5;
  1232. for (i=0; i<CFG_MAX_NAND_DEVICE; i++) {
  1233. if (nand_dev_desc[i].ChipID == NAND_ChipID_UNKNOWN) {
  1234. nand = &nand_dev_desc[i];
  1235. break;
  1236. }
  1237. }
  1238. if (!nand)
  1239. return (0);
  1240. memset((char *)nand, 0, sizeof(struct nand_chip));
  1241. nand->IO_ADDR = physadr;
  1242. nand->cache_page = -1; /* init the cache page */
  1243. NanD_ScanChips(nand);
  1244. if (nand->totlen == 0) {
  1245. /* no chips found, clean up and quit */
  1246. memset((char *)nand, 0, sizeof(struct nand_chip));
  1247. nand->ChipID = NAND_ChipID_UNKNOWN;
  1248. return (0);
  1249. }
  1250. nand->ChipID = ChipID;
  1251. if (curr_device == -1)
  1252. curr_device = i;
  1253. nand->data_buf = malloc (nand->oobblock + nand->oobsize);
  1254. if (!nand->data_buf) {
  1255. puts ("Cannot allocate memory for data structures.\n");
  1256. return (0);
  1257. }
  1258. return (nand->totlen);
  1259. }
  1260. #ifdef CONFIG_MTD_NAND_ECC
  1261. /*
  1262. * Pre-calculated 256-way 1 byte column parity
  1263. */
  1264. static const u_char nand_ecc_precalc_table[] = {
  1265. 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00,
  1266. 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
  1267. 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
  1268. 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
  1269. 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
  1270. 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
  1271. 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
  1272. 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
  1273. 0x6a, 0x3f, 0x3c, 0x69, 0x33, 0x66, 0x65, 0x30, 0x30, 0x65, 0x66, 0x33, 0x69, 0x3c, 0x3f, 0x6a,
  1274. 0x0f, 0x5a, 0x59, 0x0c, 0x56, 0x03, 0x00, 0x55, 0x55, 0x00, 0x03, 0x56, 0x0c, 0x59, 0x5a, 0x0f,
  1275. 0x0c, 0x59, 0x5a, 0x0f, 0x55, 0x00, 0x03, 0x56, 0x56, 0x03, 0x00, 0x55, 0x0f, 0x5a, 0x59, 0x0c,
  1276. 0x69, 0x3c, 0x3f, 0x6a, 0x30, 0x65, 0x66, 0x33, 0x33, 0x66, 0x65, 0x30, 0x6a, 0x3f, 0x3c, 0x69,
  1277. 0x03, 0x56, 0x55, 0x00, 0x5a, 0x0f, 0x0c, 0x59, 0x59, 0x0c, 0x0f, 0x5a, 0x00, 0x55, 0x56, 0x03,
  1278. 0x66, 0x33, 0x30, 0x65, 0x3f, 0x6a, 0x69, 0x3c, 0x3c, 0x69, 0x6a, 0x3f, 0x65, 0x30, 0x33, 0x66,
  1279. 0x65, 0x30, 0x33, 0x66, 0x3c, 0x69, 0x6a, 0x3f, 0x3f, 0x6a, 0x69, 0x3c, 0x66, 0x33, 0x30, 0x65,
  1280. 0x00, 0x55, 0x56, 0x03, 0x59, 0x0c, 0x0f, 0x5a, 0x5a, 0x0f, 0x0c, 0x59, 0x03, 0x56, 0x55, 0x00
  1281. };
  1282. /*
  1283. * Creates non-inverted ECC code from line parity
  1284. */
  1285. static void nand_trans_result(u_char reg2, u_char reg3,
  1286. u_char *ecc_code)
  1287. {
  1288. u_char a, b, i, tmp1, tmp2;
  1289. /* Initialize variables */
  1290. a = b = 0x80;
  1291. tmp1 = tmp2 = 0;
  1292. /* Calculate first ECC byte */
  1293. for (i = 0; i < 4; i++) {
  1294. if (reg3 & a) /* LP15,13,11,9 --> ecc_code[0] */
  1295. tmp1 |= b;
  1296. b >>= 1;
  1297. if (reg2 & a) /* LP14,12,10,8 --> ecc_code[0] */
  1298. tmp1 |= b;
  1299. b >>= 1;
  1300. a >>= 1;
  1301. }
  1302. /* Calculate second ECC byte */
  1303. b = 0x80;
  1304. for (i = 0; i < 4; i++) {
  1305. if (reg3 & a) /* LP7,5,3,1 --> ecc_code[1] */
  1306. tmp2 |= b;
  1307. b >>= 1;
  1308. if (reg2 & a) /* LP6,4,2,0 --> ecc_code[1] */
  1309. tmp2 |= b;
  1310. b >>= 1;
  1311. a >>= 1;
  1312. }
  1313. /* Store two of the ECC bytes */
  1314. ecc_code[0] = tmp1;
  1315. ecc_code[1] = tmp2;
  1316. }
  1317. /*
  1318. * Calculate 3 byte ECC code for 256 byte block
  1319. */
  1320. static void nand_calculate_ecc (const u_char *dat, u_char *ecc_code)
  1321. {
  1322. u_char idx, reg1, reg3;
  1323. int j;
  1324. /* Initialize variables */
  1325. reg1 = reg3 = 0;
  1326. ecc_code[0] = ecc_code[1] = ecc_code[2] = 0;
  1327. /* Build up column parity */
  1328. for(j = 0; j < 256; j++) {
  1329. /* Get CP0 - CP5 from table */
  1330. idx = nand_ecc_precalc_table[dat[j]];
  1331. reg1 ^= idx;
  1332. /* All bit XOR = 1 ? */
  1333. if (idx & 0x40) {
  1334. reg3 ^= (u_char) j;
  1335. }
  1336. }
  1337. /* Create non-inverted ECC code from line parity */
  1338. nand_trans_result((reg1 & 0x40) ? ~reg3 : reg3, reg3, ecc_code);
  1339. /* Calculate final ECC code */
  1340. ecc_code[0] = ~ecc_code[0];
  1341. ecc_code[1] = ~ecc_code[1];
  1342. ecc_code[2] = ((~reg1) << 2) | 0x03;
  1343. }
  1344. /*
  1345. * Detect and correct a 1 bit error for 256 byte block
  1346. */
  1347. static int nand_correct_data (u_char *dat, u_char *read_ecc, u_char *calc_ecc)
  1348. {
  1349. u_char a, b, c, d1, d2, d3, add, bit, i;
  1350. /* Do error detection */
  1351. d1 = calc_ecc[0] ^ read_ecc[0];
  1352. d2 = calc_ecc[1] ^ read_ecc[1];
  1353. d3 = calc_ecc[2] ^ read_ecc[2];
  1354. if ((d1 | d2 | d3) == 0) {
  1355. /* No errors */
  1356. return 0;
  1357. }
  1358. else {
  1359. a = (d1 ^ (d1 >> 1)) & 0x55;
  1360. b = (d2 ^ (d2 >> 1)) & 0x55;
  1361. c = (d3 ^ (d3 >> 1)) & 0x54;
  1362. /* Found and will correct single bit error in the data */
  1363. if ((a == 0x55) && (b == 0x55) && (c == 0x54)) {
  1364. c = 0x80;
  1365. add = 0;
  1366. a = 0x80;
  1367. for (i=0; i<4; i++) {
  1368. if (d1 & c)
  1369. add |= a;
  1370. c >>= 2;
  1371. a >>= 1;
  1372. }
  1373. c = 0x80;
  1374. for (i=0; i<4; i++) {
  1375. if (d2 & c)
  1376. add |= a;
  1377. c >>= 2;
  1378. a >>= 1;
  1379. }
  1380. bit = 0;
  1381. b = 0x04;
  1382. c = 0x80;
  1383. for (i=0; i<3; i++) {
  1384. if (d3 & c)
  1385. bit |= b;
  1386. c >>= 2;
  1387. b >>= 1;
  1388. }
  1389. b = 0x01;
  1390. a = dat[add];
  1391. a ^= (b << bit);
  1392. dat[add] = a;
  1393. return 1;
  1394. }
  1395. else {
  1396. i = 0;
  1397. while (d1) {
  1398. if (d1 & 0x01)
  1399. ++i;
  1400. d1 >>= 1;
  1401. }
  1402. while (d2) {
  1403. if (d2 & 0x01)
  1404. ++i;
  1405. d2 >>= 1;
  1406. }
  1407. while (d3) {
  1408. if (d3 & 0x01)
  1409. ++i;
  1410. d3 >>= 1;
  1411. }
  1412. if (i == 1) {
  1413. /* ECC Code Error Correction */
  1414. read_ecc[0] = calc_ecc[0];
  1415. read_ecc[1] = calc_ecc[1];
  1416. read_ecc[2] = calc_ecc[2];
  1417. return 2;
  1418. }
  1419. else {
  1420. /* Uncorrectable Error */
  1421. return -1;
  1422. }
  1423. }
  1424. }
  1425. /* Should never happen */
  1426. return -1;
  1427. }
  1428. #endif
  1429. #endif /* (CONFIG_COMMANDS & CFG_CMD_NAND) */