stm32mp15xx-dhcor-u-boot.dtsi 2.4 KB

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  1. // SPDX-License-Identifier: (GPL-2.0 OR BSD-3-Clause)
  2. /*
  3. * Copyright : STMicroelectronics 2018
  4. *
  5. * Copyright (C) Linaro Ltd 2019 - All Rights Reserved
  6. * Author: Manivannan Sadhasivam <manivannan.sadhasivam@linaro.org>
  7. * Copyright (C) 2020 Marek Vasut <marex@denx.de>
  8. */
  9. #include <dt-bindings/clock/stm32mp1-clksrc.h>
  10. #include "stm32mp15-u-boot.dtsi"
  11. #include "stm32mp15-ddr3-dhsom-2x1Gb-1066-binG.dtsi"
  12. #include "stm32mp15-ddr3-dhsom-2x2Gb-1066-binG.dtsi"
  13. #include "stm32mp15-ddr3-dhsom-2x4Gb-1066-binG.dtsi"
  14. / {
  15. u-boot,dm-pre-reloc;
  16. config {
  17. dh,ddr3-coding-gpios = <&gpiog 0 0>, <&gpiog 1 0>;
  18. dh,som-coding-gpios = <&gpioz 7 0>, <&gpiof 3 0>;
  19. };
  20. };
  21. &gpiof {
  22. snor-nwp {
  23. gpio-hog;
  24. gpios = <7 0>;
  25. output-high;
  26. line-name = "spi-nor-nwp";
  27. };
  28. };
  29. &i2c4 {
  30. u-boot,dm-pre-reloc;
  31. };
  32. &i2c4_pins_a {
  33. u-boot,dm-pre-reloc;
  34. pins {
  35. u-boot,dm-pre-reloc;
  36. };
  37. };
  38. &pmic {
  39. u-boot,dm-pre-reloc;
  40. };
  41. &qspi {
  42. u-boot,dm-spl;
  43. };
  44. &rcc {
  45. st,clksrc = <
  46. CLK_MPU_PLL1P
  47. CLK_AXI_PLL2P
  48. CLK_MCU_PLL3P
  49. CLK_PLL12_HSE
  50. CLK_PLL3_HSE
  51. CLK_PLL4_HSE
  52. CLK_RTC_LSE
  53. CLK_MCO1_DISABLED
  54. CLK_MCO2_DISABLED
  55. >;
  56. st,clkdiv = <
  57. 1 /*MPU*/
  58. 0 /*AXI*/
  59. 0 /*MCU*/
  60. 1 /*APB1*/
  61. 1 /*APB2*/
  62. 1 /*APB3*/
  63. 1 /*APB4*/
  64. 2 /*APB5*/
  65. 23 /*RTC*/
  66. 0 /*MCO1*/
  67. 0 /*MCO2*/
  68. >;
  69. st,pkcs = <
  70. CLK_CKPER_HSE
  71. CLK_FMC_ACLK
  72. CLK_QSPI_ACLK
  73. CLK_ETH_DISABLED
  74. CLK_SDMMC12_PLL4P
  75. CLK_DSI_DSIPLL
  76. CLK_STGEN_HSE
  77. CLK_USBPHY_HSE
  78. CLK_SPI2S1_PLL3Q
  79. CLK_SPI2S23_PLL3Q
  80. CLK_SPI45_HSI
  81. CLK_SPI6_HSI
  82. CLK_I2C46_HSI
  83. CLK_SDMMC3_PLL4P
  84. CLK_USBO_USBPHY
  85. CLK_ADC_CKPER
  86. CLK_CEC_LSE
  87. CLK_I2C12_HSI
  88. CLK_I2C35_HSI
  89. CLK_UART1_HSI
  90. CLK_UART24_HSI
  91. CLK_UART35_HSI
  92. CLK_UART6_HSI
  93. CLK_UART78_HSI
  94. CLK_SPDIF_PLL4P
  95. CLK_FDCAN_PLL4R
  96. CLK_SAI1_PLL3Q
  97. CLK_SAI2_PLL3Q
  98. CLK_SAI3_PLL3Q
  99. CLK_SAI4_PLL3Q
  100. CLK_RNG1_LSI
  101. CLK_RNG2_LSI
  102. CLK_LPTIM1_PCLK1
  103. CLK_LPTIM23_PCLK3
  104. CLK_LPTIM45_LSE
  105. >;
  106. /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */
  107. pll2: st,pll@1 {
  108. compatible = "st,stm32mp1-pll";
  109. reg = <1>;
  110. cfg = < 2 65 1 0 0 PQR(1,1,1) >;
  111. frac = < 0x1400 >;
  112. u-boot,dm-pre-reloc;
  113. };
  114. /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */
  115. pll3: st,pll@2 {
  116. compatible = "st,stm32mp1-pll";
  117. reg = <2>;
  118. cfg = < 1 33 1 16 36 PQR(1,1,1) >;
  119. frac = < 0x1a04 >;
  120. u-boot,dm-pre-reloc;
  121. };
  122. /* VCO = 600.0 MHz => P = 99, Q = 74, R = 99 */
  123. pll4: st,pll@3 {
  124. compatible = "st,stm32mp1-pll";
  125. reg = <3>;
  126. cfg = < 3 98 5 7 5 PQR(1,1,1) >;
  127. u-boot,dm-pre-reloc;
  128. };
  129. };