ddr3_init.c 29 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (C) Marvell International Ltd. and its affiliates
  4. */
  5. #include <common.h>
  6. #include <i2c.h>
  7. #include <spl.h>
  8. #include <asm/io.h>
  9. #include <asm/arch/cpu.h>
  10. #include <asm/arch/soc.h>
  11. #include "ddr3_init.h"
  12. #if defined(MV88F78X60)
  13. #include "ddr3_axp_vars.h"
  14. #elif defined(MV88F67XX)
  15. #include "ddr3_a370_vars.h"
  16. #elif defined(MV88F672X)
  17. #include "ddr3_a375_vars.h"
  18. #endif
  19. #ifdef STATIC_TRAINING
  20. static void ddr3_static_training_init(void);
  21. #endif
  22. #ifdef DUNIT_STATIC
  23. static void ddr3_static_mc_init(void);
  24. #endif
  25. #if defined(DUNIT_STATIC) || defined(STATIC_TRAINING)
  26. MV_DRAM_MODES *ddr3_get_static_ddr_mode(void);
  27. #endif
  28. #if defined(MV88F672X)
  29. void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps);
  30. #endif
  31. u32 mv_board_id_get(void);
  32. extern void ddr3_set_sw_wl_rl_debug(u32);
  33. extern void ddr3_set_pbs(u32);
  34. extern void ddr3_set_log_level(u32 val);
  35. static u32 log_level = DDR3_LOG_LEVEL;
  36. static u32 ddr3_init_main(void);
  37. /*
  38. * Name: ddr3_set_log_level
  39. * Desc: This routine initialize the log_level acording to nLogLevel
  40. * which getting from user
  41. * Args: nLogLevel
  42. * Notes:
  43. * Returns: None.
  44. */
  45. void ddr3_set_log_level(u32 val)
  46. {
  47. log_level = val;
  48. }
  49. /*
  50. * Name: ddr3_get_log_level
  51. * Desc: This routine returns the log level
  52. * Args: none
  53. * Notes:
  54. * Returns: log level.
  55. */
  56. u32 ddr3_get_log_level(void)
  57. {
  58. return log_level;
  59. }
  60. static void debug_print_reg(u32 reg)
  61. {
  62. printf("0x%08x = 0x%08x\n", reg, reg_read(reg));
  63. }
  64. static void print_dunit_setup(void)
  65. {
  66. puts("\n########### LOG LEVEL 1 (D-UNIT SETUP)###########\n");
  67. #ifdef DUNIT_STATIC
  68. puts("\nStatic D-UNIT Setup:\n");
  69. #endif
  70. #ifdef DUNIT_SPD
  71. puts("\nDynamic(using SPD) D-UNIT Setup:\n");
  72. #endif
  73. debug_print_reg(REG_SDRAM_CONFIG_ADDR);
  74. debug_print_reg(REG_DUNIT_CTRL_LOW_ADDR);
  75. debug_print_reg(REG_SDRAM_TIMING_LOW_ADDR);
  76. debug_print_reg(REG_SDRAM_TIMING_HIGH_ADDR);
  77. debug_print_reg(REG_SDRAM_ADDRESS_CTRL_ADDR);
  78. debug_print_reg(REG_SDRAM_OPEN_PAGES_ADDR);
  79. debug_print_reg(REG_SDRAM_OPERATION_ADDR);
  80. debug_print_reg(REG_SDRAM_MODE_ADDR);
  81. debug_print_reg(REG_SDRAM_EXT_MODE_ADDR);
  82. debug_print_reg(REG_DDR_CONT_HIGH_ADDR);
  83. debug_print_reg(REG_ODT_TIME_LOW_ADDR);
  84. debug_print_reg(REG_SDRAM_ERROR_ADDR);
  85. debug_print_reg(REG_SDRAM_AUTO_PWR_SAVE_ADDR);
  86. debug_print_reg(REG_OUDDR3_TIMING_ADDR);
  87. debug_print_reg(REG_ODT_TIME_HIGH_ADDR);
  88. debug_print_reg(REG_SDRAM_ODT_CTRL_LOW_ADDR);
  89. debug_print_reg(REG_SDRAM_ODT_CTRL_HIGH_ADDR);
  90. debug_print_reg(REG_DUNIT_ODT_CTRL_ADDR);
  91. #ifndef MV88F67XX
  92. debug_print_reg(REG_DRAM_FIFO_CTRL_ADDR);
  93. debug_print_reg(REG_DRAM_AXI_CTRL_ADDR);
  94. debug_print_reg(REG_DRAM_ADDR_CTRL_DRIVE_STRENGTH_ADDR);
  95. debug_print_reg(REG_DRAM_DATA_DQS_DRIVE_STRENGTH_ADDR);
  96. debug_print_reg(REG_DRAM_VER_CAL_MACHINE_CTRL_ADDR);
  97. debug_print_reg(REG_DRAM_MAIN_PADS_CAL_ADDR);
  98. debug_print_reg(REG_DRAM_HOR_CAL_MACHINE_CTRL_ADDR);
  99. debug_print_reg(REG_CS_SIZE_SCRATCH_ADDR);
  100. debug_print_reg(REG_DYNAMIC_POWER_SAVE_ADDR);
  101. debug_print_reg(REG_READ_DATA_SAMPLE_DELAYS_ADDR);
  102. debug_print_reg(REG_READ_DATA_READY_DELAYS_ADDR);
  103. debug_print_reg(REG_DDR3_MR0_ADDR);
  104. debug_print_reg(REG_DDR3_MR1_ADDR);
  105. debug_print_reg(REG_DDR3_MR2_ADDR);
  106. debug_print_reg(REG_DDR3_MR3_ADDR);
  107. debug_print_reg(REG_DDR3_RANK_CTRL_ADDR);
  108. debug_print_reg(REG_DRAM_PHY_CONFIG_ADDR);
  109. debug_print_reg(REG_STATIC_DRAM_DLB_CONTROL);
  110. debug_print_reg(DLB_BUS_OPTIMIZATION_WEIGHTS_REG);
  111. debug_print_reg(DLB_AGING_REGISTER);
  112. debug_print_reg(DLB_EVICTION_CONTROL_REG);
  113. debug_print_reg(DLB_EVICTION_TIMERS_REGISTER_REG);
  114. #if defined(MV88F672X)
  115. debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(0));
  116. debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(0));
  117. debug_print_reg(REG_FASTPATH_WIN_CTRL_ADDR(1));
  118. debug_print_reg(REG_FASTPATH_WIN_BASE_ADDR(1));
  119. #else
  120. debug_print_reg(REG_FASTPATH_WIN_0_CTRL_ADDR);
  121. #endif
  122. debug_print_reg(REG_CDI_CONFIG_ADDR);
  123. #endif
  124. }
  125. #if !defined(STATIC_TRAINING)
  126. static void ddr3_restore_and_set_final_windows(u32 *win_backup)
  127. {
  128. u32 ui, reg, cs;
  129. u32 win_ctrl_reg, num_of_win_regs;
  130. u32 cs_ena = ddr3_get_cs_ena_from_reg();
  131. #if defined(MV88F672X)
  132. if (DDR3_FAST_PATH_EN == 0)
  133. return;
  134. #endif
  135. #if defined(MV88F672X)
  136. win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
  137. num_of_win_regs = 8;
  138. #else
  139. win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
  140. num_of_win_regs = 16;
  141. #endif
  142. /* Return XBAR windows 4-7 or 16-19 init configuration */
  143. for (ui = 0; ui < num_of_win_regs; ui++)
  144. reg_write((win_ctrl_reg + 0x4 * ui), win_backup[ui]);
  145. DEBUG_INIT_FULL_S("DDR3 Training Sequence - Switching XBAR Window to FastPath Window\n");
  146. #if defined(MV88F672X)
  147. /* Set L2 filtering to 1G */
  148. reg_write(0x8c04, 0x40000000);
  149. /* Open fast path windows */
  150. for (cs = 0; cs < MAX_CS; cs++) {
  151. if (cs_ena & (1 << cs)) {
  152. /* set fast path window control for the cs */
  153. reg = 0x1FFFFFE1;
  154. reg |= (cs << 2);
  155. reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
  156. /* Open fast path Window */
  157. reg_write(REG_FASTPATH_WIN_CTRL_ADDR(cs), reg);
  158. /* set fast path window base address for the cs */
  159. reg = (((SDRAM_CS_SIZE + 1) * cs) & 0xFFFF0000);
  160. /* Set base address */
  161. reg_write(REG_FASTPATH_WIN_BASE_ADDR(cs), reg);
  162. }
  163. }
  164. #else
  165. reg = 0x1FFFFFE1;
  166. for (cs = 0; cs < MAX_CS; cs++) {
  167. if (cs_ena & (1 << cs)) {
  168. reg |= (cs << 2);
  169. break;
  170. }
  171. }
  172. /* Open fast path Window to - 0.5G */
  173. reg_write(REG_FASTPATH_WIN_0_CTRL_ADDR, reg);
  174. #endif
  175. }
  176. static void ddr3_save_and_set_training_windows(u32 *win_backup)
  177. {
  178. u32 cs_ena = ddr3_get_cs_ena_from_reg();
  179. u32 reg, tmp_count, cs, ui;
  180. u32 win_ctrl_reg, win_base_reg, win_remap_reg;
  181. u32 num_of_win_regs, win_jump_index;
  182. #if defined(MV88F672X)
  183. /* Disable L2 filtering */
  184. reg_write(0x8c04, 0);
  185. win_ctrl_reg = REG_XBAR_WIN_16_CTRL_ADDR;
  186. win_base_reg = REG_XBAR_WIN_16_BASE_ADDR;
  187. win_remap_reg = REG_XBAR_WIN_16_REMAP_ADDR;
  188. win_jump_index = 0x8;
  189. num_of_win_regs = 8;
  190. #else
  191. win_ctrl_reg = REG_XBAR_WIN_4_CTRL_ADDR;
  192. win_base_reg = REG_XBAR_WIN_4_BASE_ADDR;
  193. win_remap_reg = REG_XBAR_WIN_4_REMAP_ADDR;
  194. win_jump_index = 0x10;
  195. num_of_win_regs = 16;
  196. #endif
  197. /* Close XBAR Window 19 - Not needed */
  198. /* {0x000200e8} - Open Mbus Window - 2G */
  199. reg_write(REG_XBAR_WIN_19_CTRL_ADDR, 0);
  200. /* Save XBAR Windows 4-19 init configurations */
  201. for (ui = 0; ui < num_of_win_regs; ui++)
  202. win_backup[ui] = reg_read(win_ctrl_reg + 0x4 * ui);
  203. /* Open XBAR Windows 4-7 or 16-19 for other CS */
  204. reg = 0;
  205. tmp_count = 0;
  206. for (cs = 0; cs < MAX_CS; cs++) {
  207. if (cs_ena & (1 << cs)) {
  208. switch (cs) {
  209. case 0:
  210. reg = 0x0E00;
  211. break;
  212. case 1:
  213. reg = 0x0D00;
  214. break;
  215. case 2:
  216. reg = 0x0B00;
  217. break;
  218. case 3:
  219. reg = 0x0700;
  220. break;
  221. }
  222. reg |= (1 << 0);
  223. reg |= (SDRAM_CS_SIZE & 0xFFFF0000);
  224. reg_write(win_ctrl_reg + win_jump_index * tmp_count,
  225. reg);
  226. reg = ((SDRAM_CS_SIZE + 1) * (tmp_count)) & 0xFFFF0000;
  227. reg_write(win_base_reg + win_jump_index * tmp_count,
  228. reg);
  229. if (win_remap_reg <= REG_XBAR_WIN_7_REMAP_ADDR) {
  230. reg_write(win_remap_reg +
  231. win_jump_index * tmp_count, 0);
  232. }
  233. tmp_count++;
  234. }
  235. }
  236. }
  237. #endif /* !defined(STATIC_TRAINING) */
  238. /*
  239. * Name: ddr3_init - Main DDR3 Init function
  240. * Desc: This routine initialize the DDR3 MC and runs HW training.
  241. * Args: None.
  242. * Notes:
  243. * Returns: None.
  244. */
  245. int ddr3_init(void)
  246. {
  247. unsigned int status;
  248. ddr3_set_pbs(DDR3_PBS);
  249. ddr3_set_sw_wl_rl_debug(DDR3_RUN_SW_WHEN_HW_FAIL);
  250. status = ddr3_init_main();
  251. if (status == MV_DDR3_TRAINING_ERR_BAD_SAR)
  252. DEBUG_INIT_S("DDR3 Training Error: Bad sample at reset");
  253. if (status == MV_DDR3_TRAINING_ERR_BAD_DIMM_SETUP)
  254. DEBUG_INIT_S("DDR3 Training Error: Bad DIMM setup");
  255. if (status == MV_DDR3_TRAINING_ERR_MAX_CS_LIMIT)
  256. DEBUG_INIT_S("DDR3 Training Error: Max CS limit");
  257. if (status == MV_DDR3_TRAINING_ERR_MAX_ENA_CS_LIMIT)
  258. DEBUG_INIT_S("DDR3 Training Error: Max enable CS limit");
  259. if (status == MV_DDR3_TRAINING_ERR_BAD_R_DIMM_SETUP)
  260. DEBUG_INIT_S("DDR3 Training Error: Bad R-DIMM setup");
  261. if (status == MV_DDR3_TRAINING_ERR_TWSI_FAIL)
  262. DEBUG_INIT_S("DDR3 Training Error: TWSI failure");
  263. if (status == MV_DDR3_TRAINING_ERR_DIMM_TYPE_NO_MATCH)
  264. DEBUG_INIT_S("DDR3 Training Error: DIMM type no match");
  265. if (status == MV_DDR3_TRAINING_ERR_TWSI_BAD_TYPE)
  266. DEBUG_INIT_S("DDR3 Training Error: TWSI bad type");
  267. if (status == MV_DDR3_TRAINING_ERR_BUS_WIDTH_NOT_MATCH)
  268. DEBUG_INIT_S("DDR3 Training Error: bus width no match");
  269. if (status > MV_DDR3_TRAINING_ERR_HW_FAIL_BASE)
  270. DEBUG_INIT_C("DDR3 Training Error: HW Failure 0x", status, 8);
  271. return status;
  272. }
  273. static void print_ddr_target_freq(u32 cpu_freq, u32 fab_opt)
  274. {
  275. puts("\nDDR3 Training Sequence - Run DDR3 at ");
  276. switch (cpu_freq) {
  277. #if defined(MV88F672X)
  278. case 21:
  279. puts("533 Mhz\n");
  280. break;
  281. #else
  282. case 1:
  283. puts("533 Mhz\n");
  284. break;
  285. case 2:
  286. if (fab_opt == 5)
  287. puts("600 Mhz\n");
  288. if (fab_opt == 9)
  289. puts("400 Mhz\n");
  290. break;
  291. case 3:
  292. puts("667 Mhz\n");
  293. break;
  294. case 4:
  295. if (fab_opt == 5)
  296. puts("750 Mhz\n");
  297. if (fab_opt == 9)
  298. puts("500 Mhz\n");
  299. break;
  300. case 0xa:
  301. puts("400 Mhz\n");
  302. break;
  303. case 0xb:
  304. if (fab_opt == 5)
  305. puts("800 Mhz\n");
  306. if (fab_opt == 9)
  307. puts("553 Mhz\n");
  308. if (fab_opt == 0xA)
  309. puts("640 Mhz\n");
  310. break;
  311. #endif
  312. default:
  313. puts("NOT DEFINED FREQ\n");
  314. }
  315. }
  316. static u32 ddr3_init_main(void)
  317. {
  318. u32 target_freq;
  319. u32 reg = 0;
  320. u32 cpu_freq, fab_opt, hclk_time_ps, soc_num;
  321. __maybe_unused u32 ecc = DRAM_ECC;
  322. __maybe_unused int dqs_clk_aligned = 0;
  323. __maybe_unused u32 scrub_offs, scrub_size;
  324. __maybe_unused u32 ddr_width = BUS_WIDTH;
  325. __maybe_unused int status;
  326. __maybe_unused u32 win_backup[16];
  327. /* SoC/Board special Initializtions */
  328. fab_opt = ddr3_get_fab_opt();
  329. #ifdef CONFIG_SPD_EEPROM
  330. i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE);
  331. #endif
  332. ddr3_print_version();
  333. DEBUG_INIT_S("4\n");
  334. /* Lib version 5.5.4 */
  335. fab_opt = ddr3_get_fab_opt();
  336. /* Switching CPU to MRVL ID */
  337. soc_num = (reg_read(REG_SAMPLE_RESET_HIGH_ADDR) & SAR1_CPU_CORE_MASK) >>
  338. SAR1_CPU_CORE_OFFSET;
  339. switch (soc_num) {
  340. case 0x3:
  341. reg_bit_set(CPU_CONFIGURATION_REG(3), CPU_MRVL_ID_OFFSET);
  342. reg_bit_set(CPU_CONFIGURATION_REG(2), CPU_MRVL_ID_OFFSET);
  343. case 0x1:
  344. reg_bit_set(CPU_CONFIGURATION_REG(1), CPU_MRVL_ID_OFFSET);
  345. case 0x0:
  346. reg_bit_set(CPU_CONFIGURATION_REG(0), CPU_MRVL_ID_OFFSET);
  347. default:
  348. break;
  349. }
  350. /* Power down deskew PLL */
  351. #if !defined(MV88F672X)
  352. /* 0x18780 [25] */
  353. reg = (reg_read(REG_DDRPHY_APLL_CTRL_ADDR) & ~(1 << 25));
  354. reg_write(REG_DDRPHY_APLL_CTRL_ADDR, reg);
  355. #endif
  356. /*
  357. * Stage 0 - Set board configuration
  358. */
  359. cpu_freq = ddr3_get_cpu_freq();
  360. if (fab_opt > FAB_OPT)
  361. fab_opt = FAB_OPT - 1;
  362. if (ddr3_get_log_level() > 0)
  363. print_ddr_target_freq(cpu_freq, fab_opt);
  364. #if defined(MV88F672X)
  365. get_target_freq(cpu_freq, &target_freq, &hclk_time_ps);
  366. #else
  367. target_freq = cpu_ddr_ratios[fab_opt][cpu_freq];
  368. hclk_time_ps = cpu_fab_clk_to_hclk[fab_opt][cpu_freq];
  369. #endif
  370. if ((target_freq == 0) || (hclk_time_ps == 0)) {
  371. DEBUG_INIT_S("DDR3 Training Sequence - FAILED - Wrong Sample at Reset Configurations\n");
  372. if (target_freq == 0) {
  373. DEBUG_INIT_C("target_freq", target_freq, 2);
  374. DEBUG_INIT_C("fab_opt", fab_opt, 2);
  375. DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
  376. } else if (hclk_time_ps == 0) {
  377. DEBUG_INIT_C("hclk_time_ps", hclk_time_ps, 2);
  378. DEBUG_INIT_C("fab_opt", fab_opt, 2);
  379. DEBUG_INIT_C("cpu_freq", cpu_freq, 2);
  380. }
  381. return MV_DDR3_TRAINING_ERR_BAD_SAR;
  382. }
  383. #if defined(ECC_SUPPORT)
  384. scrub_offs = U_BOOT_START_ADDR;
  385. scrub_size = U_BOOT_SCRUB_SIZE;
  386. #else
  387. scrub_offs = 0;
  388. scrub_size = 0;
  389. #endif
  390. #if defined(ECC_SUPPORT) && defined(AUTO_DETECTION_SUPPORT)
  391. ecc = 0;
  392. if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_ECC))
  393. ecc = 1;
  394. #endif
  395. #ifdef DQS_CLK_ALIGNED
  396. dqs_clk_aligned = 1;
  397. #endif
  398. /* Check if DRAM is already initialized */
  399. if (reg_read(REG_BOOTROM_ROUTINE_ADDR) &
  400. (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS)) {
  401. DEBUG_INIT_S("DDR3 Training Sequence - 2nd boot - Skip\n");
  402. return MV_OK;
  403. }
  404. /*
  405. * Stage 1 - Dunit Setup
  406. */
  407. #ifdef DUNIT_STATIC
  408. /*
  409. * For Static D-Unit Setup use must set the correct static values
  410. * at the ddr3_*soc*_vars.h file
  411. */
  412. DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static MC Init\n");
  413. ddr3_static_mc_init();
  414. #ifdef ECC_SUPPORT
  415. ecc = DRAM_ECC;
  416. if (ecc) {
  417. reg = reg_read(REG_SDRAM_CONFIG_ADDR);
  418. reg |= (1 << REG_SDRAM_CONFIG_ECC_OFFS);
  419. reg_write(REG_SDRAM_CONFIG_ADDR, reg);
  420. }
  421. #endif
  422. #endif
  423. #if defined(MV88F78X60) || defined(MV88F672X)
  424. #if defined(AUTO_DETECTION_SUPPORT)
  425. /*
  426. * Configurations for both static and dynamic MC setups
  427. *
  428. * Dynamically Set 32Bit and ECC for AXP (Relevant only for
  429. * Marvell DB boards)
  430. */
  431. if (ddr3_check_config(BUS_WIDTH_ECC_TWSI_ADDR, CONFIG_BUS_WIDTH)) {
  432. ddr_width = 32;
  433. DEBUG_INIT_S("DDR3 Training Sequence - DRAM bus width 32Bit\n");
  434. }
  435. #endif
  436. #if defined(MV88F672X)
  437. reg = reg_read(REG_SDRAM_CONFIG_ADDR);
  438. if ((reg >> 15) & 1)
  439. ddr_width = 32;
  440. else
  441. ddr_width = 16;
  442. #endif
  443. #endif
  444. #ifdef DUNIT_SPD
  445. status = ddr3_dunit_setup(ecc, hclk_time_ps, &ddr_width);
  446. if (MV_OK != status) {
  447. DEBUG_INIT_S("DDR3 Training Sequence - FAILED (ddr3 Dunit Setup)\n");
  448. return status;
  449. }
  450. #endif
  451. /* Fix read ready phases for all SOC in reg 0x15C8 */
  452. reg = reg_read(REG_TRAINING_DEBUG_3_ADDR);
  453. reg &= ~(REG_TRAINING_DEBUG_3_MASK);
  454. reg |= 0x4; /* Phase 0 */
  455. reg &= ~(REG_TRAINING_DEBUG_3_MASK << REG_TRAINING_DEBUG_3_OFFS);
  456. reg |= (0x4 << (1 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 1 */
  457. reg &= ~(REG_TRAINING_DEBUG_3_MASK << (3 * REG_TRAINING_DEBUG_3_OFFS));
  458. reg |= (0x6 << (3 * REG_TRAINING_DEBUG_3_OFFS)); /* Phase 3 */
  459. reg &= ~(REG_TRAINING_DEBUG_3_MASK << (4 * REG_TRAINING_DEBUG_3_OFFS));
  460. reg |= (0x6 << (4 * REG_TRAINING_DEBUG_3_OFFS));
  461. reg &= ~(REG_TRAINING_DEBUG_3_MASK << (5 * REG_TRAINING_DEBUG_3_OFFS));
  462. reg |= (0x6 << (5 * REG_TRAINING_DEBUG_3_OFFS));
  463. reg_write(REG_TRAINING_DEBUG_3_ADDR, reg);
  464. #if defined(MV88F672X)
  465. /*
  466. * AxiBrespMode[8] = Compliant,
  467. * AxiAddrDecodeCntrl[11] = Internal,
  468. * AxiDataBusWidth[0] = 128bit
  469. */
  470. /* 0x14A8 - AXI Control Register */
  471. reg_write(REG_DRAM_AXI_CTRL_ADDR, 0);
  472. #else
  473. /* 0x14A8 - AXI Control Register */
  474. reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000100);
  475. reg_write(REG_CDI_CONFIG_ADDR, 0x00000006);
  476. if ((ddr_width == 64) && (reg_read(REG_DDR_IO_ADDR) &
  477. (1 << REG_DDR_IO_CLK_RATIO_OFFS))) {
  478. /* 0x14A8 - AXI Control Register */
  479. reg_write(REG_DRAM_AXI_CTRL_ADDR, 0x00000101);
  480. reg_write(REG_CDI_CONFIG_ADDR, 0x00000007);
  481. }
  482. #endif
  483. #if !defined(MV88F67XX)
  484. /*
  485. * ARMADA-370 activate DLB later at the u-boot,
  486. * Armada38x - No DLB activation at this time
  487. */
  488. reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0x18C01E);
  489. #if defined(MV88F78X60)
  490. /* WA according to eratta GL-8672902*/
  491. if (mv_ctrl_rev_get() == MV_78XX0_B0_REV)
  492. reg_write(DLB_BUS_OPTIMIZATION_WEIGHTS_REG, 0xc19e);
  493. #endif
  494. reg_write(DLB_AGING_REGISTER, 0x0f7f007f);
  495. reg_write(DLB_EVICTION_CONTROL_REG, 0x0);
  496. reg_write(DLB_EVICTION_TIMERS_REGISTER_REG, 0x00FF3C1F);
  497. reg_write(MBUS_UNITS_PRIORITY_CONTROL_REG, 0x55555555);
  498. reg_write(FABRIC_UNITS_PRIORITY_CONTROL_REG, 0xAA);
  499. reg_write(MBUS_UNITS_PREFETCH_CONTROL_REG, 0xffff);
  500. reg_write(FABRIC_UNITS_PREFETCH_CONTROL_REG, 0xf0f);
  501. #if defined(MV88F78X60)
  502. /* WA according to eratta GL-8672902 */
  503. if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
  504. reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
  505. reg |= DLB_ENABLE;
  506. reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
  507. }
  508. #endif /* end defined(MV88F78X60) */
  509. #endif /* end !defined(MV88F67XX) */
  510. if (ddr3_get_log_level() >= MV_LOG_LEVEL_1)
  511. print_dunit_setup();
  512. /*
  513. * Stage 2 - Training Values Setup
  514. */
  515. #ifdef STATIC_TRAINING
  516. /*
  517. * DRAM Init - After all the D-unit values are set, its time to init
  518. * the D-unit
  519. */
  520. /* Wait for '0' */
  521. reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
  522. do {
  523. reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
  524. (1 << REG_SDRAM_INIT_CTRL_OFFS);
  525. } while (reg);
  526. /* ddr3 init using static parameters - HW training is disabled */
  527. DEBUG_INIT_FULL_S("DDR3 Training Sequence - Static Training Parameters\n");
  528. ddr3_static_training_init();
  529. #if defined(MV88F78X60)
  530. /*
  531. * If ECC is enabled, need to scrub the U-Boot area memory region -
  532. * Run training function with Xor bypass just to scrub the memory
  533. */
  534. status = ddr3_hw_training(target_freq, ddr_width,
  535. 1, scrub_offs, scrub_size,
  536. dqs_clk_aligned, DDR3_TRAINING_DEBUG,
  537. REG_DIMM_SKIP_WL);
  538. if (MV_OK != status) {
  539. DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
  540. return status;
  541. }
  542. #endif
  543. #else
  544. /* Set X-BAR windows for the training sequence */
  545. ddr3_save_and_set_training_windows(win_backup);
  546. /* Run DDR3 Training Sequence */
  547. /* DRAM Init */
  548. reg_write(REG_SDRAM_INIT_CTRL_ADDR, 0x1);
  549. do {
  550. reg = (reg_read(REG_SDRAM_INIT_CTRL_ADDR)) &
  551. (1 << REG_SDRAM_INIT_CTRL_OFFS);
  552. } while (reg); /* Wait for '0' */
  553. /* ddr3 init using DDR3 HW training procedure */
  554. DEBUG_INIT_FULL_S("DDR3 Training Sequence - HW Training Procedure\n");
  555. status = ddr3_hw_training(target_freq, ddr_width,
  556. 0, scrub_offs, scrub_size,
  557. dqs_clk_aligned, DDR3_TRAINING_DEBUG,
  558. REG_DIMM_SKIP_WL);
  559. if (MV_OK != status) {
  560. DEBUG_INIT_FULL_S("DDR3 Training Sequence - FAILED\n");
  561. return status;
  562. }
  563. #endif
  564. /*
  565. * Stage 3 - Finish
  566. */
  567. #if defined(MV88F78X60) || defined(MV88F672X)
  568. /* Disable ECC Ignore bit */
  569. reg = reg_read(REG_SDRAM_CONFIG_ADDR) &
  570. ~(1 << REG_SDRAM_CONFIG_IERR_OFFS);
  571. reg_write(REG_SDRAM_CONFIG_ADDR, reg);
  572. #endif
  573. #if !defined(STATIC_TRAINING)
  574. /* Restore and set windows */
  575. ddr3_restore_and_set_final_windows(win_backup);
  576. #endif
  577. /* Update DRAM init indication in bootROM register */
  578. reg = reg_read(REG_BOOTROM_ROUTINE_ADDR);
  579. reg_write(REG_BOOTROM_ROUTINE_ADDR,
  580. reg | (1 << REG_BOOTROM_ROUTINE_DRAM_INIT_OFFS));
  581. #if !defined(MV88F67XX)
  582. #if defined(MV88F78X60)
  583. if (mv_ctrl_rev_get() == MV_78XX0_B0_REV) {
  584. reg = reg_read(REG_SDRAM_CONFIG_ADDR);
  585. if (ecc == 0)
  586. reg_write(REG_SDRAM_CONFIG_ADDR, reg | (1 << 19));
  587. }
  588. #endif /* end defined(MV88F78X60) */
  589. reg_write(DLB_EVICTION_CONTROL_REG, 0x9);
  590. reg = reg_read(REG_STATIC_DRAM_DLB_CONTROL);
  591. reg |= (DLB_ENABLE | DLB_WRITE_COALESING | DLB_AXI_PREFETCH_EN |
  592. DLB_MBUS_PREFETCH_EN | PREFETCH_NLNSZTR);
  593. reg_write(REG_STATIC_DRAM_DLB_CONTROL, reg);
  594. #endif /* end !defined(MV88F67XX) */
  595. #ifdef STATIC_TRAINING
  596. DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully (S)\n");
  597. #else
  598. DEBUG_INIT_S("DDR3 Training Sequence - Ended Successfully\n");
  599. #endif
  600. return MV_OK;
  601. }
  602. /*
  603. * Name: ddr3_get_cpu_freq
  604. * Desc: read S@R and return CPU frequency
  605. * Args:
  606. * Notes:
  607. * Returns: required value
  608. */
  609. u32 ddr3_get_cpu_freq(void)
  610. {
  611. u32 reg, cpu_freq;
  612. #if defined(MV88F672X)
  613. /* Read sample at reset setting */
  614. reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); /* 0xE8200 */
  615. cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
  616. REG_SAMPLE_RESET_CPU_FREQ_OFFS;
  617. #else
  618. /* Read sample at reset setting */
  619. reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR); /* 0x18230 [23:21] */
  620. #if defined(MV88F78X60)
  621. cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
  622. REG_SAMPLE_RESET_CPU_FREQ_OFFS;
  623. reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR); /* 0x18234 [20] */
  624. cpu_freq |= (((reg >> REG_SAMPLE_RESET_HIGH_CPU_FREQ_OFFS) & 0x1) << 3);
  625. #elif defined(MV88F67XX)
  626. cpu_freq = (reg & REG_SAMPLE_RESET_CPU_FREQ_MASK) >>
  627. REG_SAMPLE_RESET_CPU_FREQ_OFFS;
  628. #endif
  629. #endif
  630. return cpu_freq;
  631. }
  632. /*
  633. * Name: ddr3_get_fab_opt
  634. * Desc: read S@R and return CPU frequency
  635. * Args:
  636. * Notes:
  637. * Returns: required value
  638. */
  639. u32 ddr3_get_fab_opt(void)
  640. {
  641. __maybe_unused u32 reg, fab_opt;
  642. #if defined(MV88F672X)
  643. return 0; /* No fabric */
  644. #else
  645. /* Read sample at reset setting */
  646. reg = reg_read(REG_SAMPLE_RESET_LOW_ADDR);
  647. fab_opt = (reg & REG_SAMPLE_RESET_FAB_MASK) >>
  648. REG_SAMPLE_RESET_FAB_OFFS;
  649. #if defined(MV88F78X60)
  650. reg = reg_read(REG_SAMPLE_RESET_HIGH_ADDR);
  651. fab_opt |= (((reg >> 19) & 0x1) << 4);
  652. #endif
  653. return fab_opt;
  654. #endif
  655. }
  656. /*
  657. * Name: ddr3_get_vco_freq
  658. * Desc: read S@R and return VCO frequency
  659. * Args:
  660. * Notes:
  661. * Returns: required value
  662. */
  663. u32 ddr3_get_vco_freq(void)
  664. {
  665. u32 fab, cpu_freq, ui_vco_freq;
  666. fab = ddr3_get_fab_opt();
  667. cpu_freq = ddr3_get_cpu_freq();
  668. if (fab == 2 || fab == 3 || fab == 7 || fab == 8 || fab == 10 ||
  669. fab == 15 || fab == 17 || fab == 20)
  670. ui_vco_freq = cpu_freq + CLK_CPU;
  671. else
  672. ui_vco_freq = cpu_freq;
  673. return ui_vco_freq;
  674. }
  675. #ifdef STATIC_TRAINING
  676. /*
  677. * Name: ddr3_static_training_init - Init DDR3 Training with
  678. * static parameters
  679. * Desc: Use this routine to init the controller without the HW training
  680. * procedure
  681. * User must provide compatible header file with registers data.
  682. * Args: None.
  683. * Notes:
  684. * Returns: None.
  685. */
  686. void ddr3_static_training_init(void)
  687. {
  688. MV_DRAM_MODES *ddr_mode;
  689. u32 reg;
  690. int j;
  691. ddr_mode = ddr3_get_static_ddr_mode();
  692. j = 0;
  693. while (ddr_mode->vals[j].reg_addr != 0) {
  694. udelay(10); /* haim want to delay each write */
  695. reg_write(ddr_mode->vals[j].reg_addr,
  696. ddr_mode->vals[j].reg_value);
  697. if (ddr_mode->vals[j].reg_addr ==
  698. REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
  699. do {
  700. reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
  701. REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
  702. } while (reg);
  703. j++;
  704. }
  705. }
  706. #endif
  707. /*
  708. * Name: ddr3_get_static_mc_value - Init Memory controller with static
  709. * parameters
  710. * Desc: Use this routine to init the controller without the HW training
  711. * procedure
  712. * User must provide compatible header file with registers data.
  713. * Args: None.
  714. * Notes:
  715. * Returns: None.
  716. */
  717. u32 ddr3_get_static_mc_value(u32 reg_addr, u32 offset1, u32 mask1, u32 offset2,
  718. u32 mask2)
  719. {
  720. u32 reg, tmp;
  721. reg = reg_read(reg_addr);
  722. tmp = (reg >> offset1) & mask1;
  723. if (mask2)
  724. tmp |= (reg >> offset2) & mask2;
  725. return tmp;
  726. }
  727. /*
  728. * Name: ddr3_get_static_ddr_mode - Init Memory controller with static
  729. * parameters
  730. * Desc: Use this routine to init the controller without the HW training
  731. * procedure
  732. * User must provide compatible header file with registers data.
  733. * Args: None.
  734. * Notes:
  735. * Returns: None.
  736. */
  737. __weak MV_DRAM_MODES *ddr3_get_static_ddr_mode(void)
  738. {
  739. u32 chip_board_rev, i;
  740. u32 size;
  741. /* Do not modify this code. relevant only for marvell Boards */
  742. #if defined(DB_78X60_PCAC)
  743. chip_board_rev = Z1_PCAC;
  744. #elif defined(DB_78X60_AMC)
  745. chip_board_rev = A0_AMC;
  746. #elif defined(DB_88F6710_PCAC)
  747. chip_board_rev = A0_PCAC;
  748. #elif defined(RD_88F6710)
  749. chip_board_rev = A0_RD;
  750. #elif defined(MV88F672X)
  751. chip_board_rev = mv_board_id_get();
  752. #else
  753. chip_board_rev = A0;
  754. #endif
  755. size = sizeof(ddr_modes) / sizeof(MV_DRAM_MODES);
  756. for (i = 0; i < size; i++) {
  757. if ((ddr3_get_cpu_freq() == ddr_modes[i].cpu_freq) &&
  758. (ddr3_get_fab_opt() == ddr_modes[i].fab_freq) &&
  759. (chip_board_rev == ddr_modes[i].chip_board_rev))
  760. return &ddr_modes[i];
  761. }
  762. return &ddr_modes[0];
  763. }
  764. #ifdef DUNIT_STATIC
  765. /*
  766. * Name: ddr3_static_mc_init - Init Memory controller with static parameters
  767. * Desc: Use this routine to init the controller without the HW training
  768. * procedure
  769. * User must provide compatible header file with registers data.
  770. * Args: None.
  771. * Notes:
  772. * Returns: None.
  773. */
  774. void ddr3_static_mc_init(void)
  775. {
  776. MV_DRAM_MODES *ddr_mode;
  777. u32 reg;
  778. int j;
  779. ddr_mode = ddr3_get_static_ddr_mode();
  780. j = 0;
  781. while (ddr_mode->regs[j].reg_addr != 0) {
  782. reg_write(ddr_mode->regs[j].reg_addr,
  783. ddr_mode->regs[j].reg_value);
  784. if (ddr_mode->regs[j].reg_addr ==
  785. REG_PHY_REGISTRY_FILE_ACCESS_ADDR)
  786. do {
  787. reg = reg_read(REG_PHY_REGISTRY_FILE_ACCESS_ADDR) &
  788. REG_PHY_REGISTRY_FILE_ACCESS_OP_DONE;
  789. } while (reg);
  790. j++;
  791. }
  792. }
  793. #endif
  794. /*
  795. * Name: ddr3_check_config - Check user configurations: ECC/MultiCS
  796. * Desc:
  797. * Args: twsi Address
  798. * Notes: Only Available for ArmadaXP/Armada 370 DB boards
  799. * Returns: None.
  800. */
  801. int ddr3_check_config(u32 twsi_addr, MV_CONFIG_TYPE config_type)
  802. {
  803. #ifdef AUTO_DETECTION_SUPPORT
  804. u8 data = 0;
  805. int ret;
  806. int offset;
  807. if ((config_type == CONFIG_ECC) || (config_type == CONFIG_BUS_WIDTH))
  808. offset = 1;
  809. else
  810. offset = 0;
  811. ret = i2c_read(twsi_addr, offset, 1, (u8 *)&data, 1);
  812. if (!ret) {
  813. switch (config_type) {
  814. case CONFIG_ECC:
  815. if (data & 0x2)
  816. return 1;
  817. break;
  818. case CONFIG_BUS_WIDTH:
  819. if (data & 0x1)
  820. return 1;
  821. break;
  822. #ifdef DB_88F6710
  823. case CONFIG_MULTI_CS:
  824. if (CFG_MULTI_CS_MODE(data))
  825. return 1;
  826. break;
  827. #else
  828. case CONFIG_MULTI_CS:
  829. break;
  830. #endif
  831. }
  832. }
  833. #endif
  834. return 0;
  835. }
  836. #if defined(DB_88F78X60_REV2)
  837. /*
  838. * Name: ddr3_get_eprom_fabric - Get Fabric configuration from EPROM
  839. * Desc:
  840. * Args: twsi Address
  841. * Notes: Only Available for ArmadaXP DB Rev2 boards
  842. * Returns: None.
  843. */
  844. u8 ddr3_get_eprom_fabric(void)
  845. {
  846. #ifdef AUTO_DETECTION_SUPPORT
  847. u8 data = 0;
  848. int ret;
  849. ret = i2c_read(NEW_FABRIC_TWSI_ADDR, 1, 1, (u8 *)&data, 1);
  850. if (!ret)
  851. return data & 0x1F;
  852. #endif
  853. return 0;
  854. }
  855. #endif
  856. /*
  857. * Name: ddr3_cl_to_valid_cl - this return register matching CL value
  858. * Desc:
  859. * Args: clValue - the value
  860. * Notes:
  861. * Returns: required CL value
  862. */
  863. u32 ddr3_cl_to_valid_cl(u32 cl)
  864. {
  865. switch (cl) {
  866. case 5:
  867. return 2;
  868. break;
  869. case 6:
  870. return 4;
  871. break;
  872. case 7:
  873. return 6;
  874. break;
  875. case 8:
  876. return 8;
  877. break;
  878. case 9:
  879. return 10;
  880. break;
  881. case 10:
  882. return 12;
  883. break;
  884. case 11:
  885. return 14;
  886. break;
  887. case 12:
  888. return 1;
  889. break;
  890. case 13:
  891. return 3;
  892. break;
  893. case 14:
  894. return 5;
  895. break;
  896. default:
  897. return 2;
  898. }
  899. }
  900. /*
  901. * Name: ddr3_cl_to_valid_cl - this return register matching CL value
  902. * Desc:
  903. * Args: clValue - the value
  904. * Notes:
  905. * Returns: required CL value
  906. */
  907. u32 ddr3_valid_cl_to_cl(u32 ui_valid_cl)
  908. {
  909. switch (ui_valid_cl) {
  910. case 1:
  911. return 12;
  912. break;
  913. case 2:
  914. return 5;
  915. break;
  916. case 3:
  917. return 13;
  918. break;
  919. case 4:
  920. return 6;
  921. break;
  922. case 5:
  923. return 14;
  924. break;
  925. case 6:
  926. return 7;
  927. break;
  928. case 8:
  929. return 8;
  930. break;
  931. case 10:
  932. return 9;
  933. break;
  934. case 12:
  935. return 10;
  936. break;
  937. case 14:
  938. return 11;
  939. break;
  940. default:
  941. return 0;
  942. }
  943. }
  944. /*
  945. * Name: ddr3_get_cs_num_from_reg
  946. * Desc:
  947. * Args:
  948. * Notes:
  949. * Returns:
  950. */
  951. u32 ddr3_get_cs_num_from_reg(void)
  952. {
  953. u32 cs_ena = ddr3_get_cs_ena_from_reg();
  954. u32 cs_count = 0;
  955. u32 cs;
  956. for (cs = 0; cs < MAX_CS; cs++) {
  957. if (cs_ena & (1 << cs))
  958. cs_count++;
  959. }
  960. return cs_count;
  961. }
  962. /*
  963. * Name: ddr3_get_cs_ena_from_reg
  964. * Desc:
  965. * Args:
  966. * Notes:
  967. * Returns:
  968. */
  969. u32 ddr3_get_cs_ena_from_reg(void)
  970. {
  971. return reg_read(REG_DDR3_RANK_CTRL_ADDR) &
  972. REG_DDR3_RANK_CTRL_CS_ENA_MASK;
  973. }
  974. /*
  975. * mv_ctrl_rev_get - Get Marvell controller device revision number
  976. *
  977. * DESCRIPTION:
  978. * This function returns 8bit describing the device revision as defined
  979. * in PCI Express Class Code and Revision ID Register.
  980. *
  981. * INPUT:
  982. * None.
  983. *
  984. * OUTPUT:
  985. * None.
  986. *
  987. * RETURN:
  988. * 8bit desscribing Marvell controller revision number
  989. *
  990. */
  991. #if !defined(MV88F672X)
  992. u8 mv_ctrl_rev_get(void)
  993. {
  994. u8 rev_num;
  995. #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
  996. /* Check pex power state */
  997. u32 pex_power;
  998. pex_power = mv_ctrl_pwr_clck_get(PEX_UNIT_ID, 0);
  999. if (pex_power == 0)
  1000. mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 1);
  1001. #endif
  1002. rev_num = (u8)reg_read(PEX_CFG_DIRECT_ACCESS(0,
  1003. PCI_CLASS_CODE_AND_REVISION_ID));
  1004. #if defined(MV_INCLUDE_CLK_PWR_CNTRL)
  1005. /* Return to power off state */
  1006. if (pex_power == 0)
  1007. mv_ctrl_pwr_clck_set(PEX_UNIT_ID, 0, 0);
  1008. #endif
  1009. return (rev_num & PCCRIR_REVID_MASK) >> PCCRIR_REVID_OFFS;
  1010. }
  1011. #endif
  1012. #if defined(MV88F672X)
  1013. void get_target_freq(u32 freq_mode, u32 *ddr_freq, u32 *hclk_ps)
  1014. {
  1015. u32 tmp, hclk;
  1016. switch (freq_mode) {
  1017. case CPU_333MHz_DDR_167MHz_L2_167MHz:
  1018. hclk = 84;
  1019. tmp = DDR_100;
  1020. break;
  1021. case CPU_266MHz_DDR_266MHz_L2_133MHz:
  1022. case CPU_333MHz_DDR_222MHz_L2_167MHz:
  1023. case CPU_400MHz_DDR_200MHz_L2_200MHz:
  1024. case CPU_400MHz_DDR_267MHz_L2_200MHz:
  1025. case CPU_533MHz_DDR_267MHz_L2_267MHz:
  1026. case CPU_500MHz_DDR_250MHz_L2_250MHz:
  1027. case CPU_600MHz_DDR_300MHz_L2_300MHz:
  1028. case CPU_800MHz_DDR_267MHz_L2_400MHz:
  1029. case CPU_900MHz_DDR_300MHz_L2_450MHz:
  1030. tmp = DDR_300;
  1031. hclk = 150;
  1032. break;
  1033. case CPU_333MHz_DDR_333MHz_L2_167MHz:
  1034. case CPU_500MHz_DDR_334MHz_L2_250MHz:
  1035. case CPU_666MHz_DDR_333MHz_L2_333MHz:
  1036. tmp = DDR_333;
  1037. hclk = 165;
  1038. break;
  1039. case CPU_533MHz_DDR_356MHz_L2_267MHz:
  1040. tmp = DDR_360;
  1041. hclk = 180;
  1042. break;
  1043. case CPU_400MHz_DDR_400MHz_L2_200MHz:
  1044. case CPU_600MHz_DDR_400MHz_L2_300MHz:
  1045. case CPU_800MHz_DDR_400MHz_L2_400MHz:
  1046. case CPU_400MHz_DDR_400MHz_L2_400MHz:
  1047. tmp = DDR_400;
  1048. hclk = 200;
  1049. break;
  1050. case CPU_666MHz_DDR_444MHz_L2_333MHz:
  1051. case CPU_900MHz_DDR_450MHz_L2_450MHz:
  1052. tmp = DDR_444;
  1053. hclk = 222;
  1054. break;
  1055. case CPU_500MHz_DDR_500MHz_L2_250MHz:
  1056. case CPU_1000MHz_DDR_500MHz_L2_500MHz:
  1057. case CPU_1000MHz_DDR_500MHz_L2_333MHz:
  1058. tmp = DDR_500;
  1059. hclk = 250;
  1060. break;
  1061. case CPU_533MHz_DDR_533MHz_L2_267MHz:
  1062. case CPU_800MHz_DDR_534MHz_L2_400MHz:
  1063. case CPU_1100MHz_DDR_550MHz_L2_550MHz:
  1064. tmp = DDR_533;
  1065. hclk = 267;
  1066. break;
  1067. case CPU_600MHz_DDR_600MHz_L2_300MHz:
  1068. case CPU_900MHz_DDR_600MHz_L2_450MHz:
  1069. case CPU_1200MHz_DDR_600MHz_L2_600MHz:
  1070. tmp = DDR_600;
  1071. hclk = 300;
  1072. break;
  1073. case CPU_666MHz_DDR_666MHz_L2_333MHz:
  1074. case CPU_1000MHz_DDR_667MHz_L2_500MHz:
  1075. tmp = DDR_666;
  1076. hclk = 333;
  1077. break;
  1078. default:
  1079. *ddr_freq = 0;
  1080. *hclk_ps = 0;
  1081. break;
  1082. }
  1083. *ddr_freq = tmp; /* DDR freq define */
  1084. *hclk_ps = 1000000 / hclk; /* values are 1/HCLK in ps */
  1085. return;
  1086. }
  1087. #endif