cpu.h 3.4 KB

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  1. /*
  2. * (C) Copyright 2009
  3. * Marvell Semiconductor <www.marvell.com>
  4. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #ifndef _MVEBU_CPU_H
  9. #define _MVEBU_CPU_H
  10. #include <asm/system.h>
  11. #ifndef __ASSEMBLY__
  12. #define MVEBU_REG_PCIE_DEVID (MVEBU_REG_PCIE_BASE + 0x00)
  13. #define MVEBU_REG_PCIE_REVID (MVEBU_REG_PCIE_BASE + 0x08)
  14. enum memory_bank {
  15. BANK0,
  16. BANK1,
  17. BANK2,
  18. BANK3
  19. };
  20. enum cpu_winen {
  21. CPU_WIN_DISABLE,
  22. CPU_WIN_ENABLE
  23. };
  24. enum cpu_target {
  25. CPU_TARGET_DRAM = 0x0,
  26. CPU_TARGET_DEVICEBUS_BOOTROM_SPI = 0x1,
  27. CPU_TARGET_ETH23 = 0x3,
  28. CPU_TARGET_PCIE02 = 0x4,
  29. CPU_TARGET_ETH01 = 0x7,
  30. CPU_TARGET_PCIE13 = 0x8,
  31. CPU_TARGET_SASRAM = 0x9,
  32. CPU_TARGET_SATA01 = 0xa, /* A38X */
  33. CPU_TARGET_NAND = 0xd,
  34. CPU_TARGET_SATA23_DFX = 0xe, /* A38X */
  35. };
  36. enum cpu_attrib {
  37. CPU_ATTR_SASRAM = 0x01,
  38. CPU_ATTR_DRAM_CS0 = 0x0e,
  39. CPU_ATTR_DRAM_CS1 = 0x0d,
  40. CPU_ATTR_DRAM_CS2 = 0x0b,
  41. CPU_ATTR_DRAM_CS3 = 0x07,
  42. CPU_ATTR_NANDFLASH = 0x2f,
  43. CPU_ATTR_SPIFLASH = 0x1e,
  44. CPU_ATTR_SPI0_CS0 = 0x1e,
  45. CPU_ATTR_SPI0_CS1 = 0x5e,
  46. CPU_ATTR_SPI1_CS2 = 0x9a,
  47. CPU_ATTR_BOOTROM = 0x1d,
  48. CPU_ATTR_PCIE_IO = 0xe0,
  49. CPU_ATTR_PCIE_MEM = 0xe8,
  50. CPU_ATTR_DEV_CS0 = 0x3e,
  51. CPU_ATTR_DEV_CS1 = 0x3d,
  52. CPU_ATTR_DEV_CS2 = 0x3b,
  53. CPU_ATTR_DEV_CS3 = 0x37,
  54. };
  55. enum {
  56. MVEBU_SOC_AXP,
  57. MVEBU_SOC_A375,
  58. MVEBU_SOC_A38X,
  59. MVEBU_SOC_UNKNOWN,
  60. };
  61. /*
  62. * Default Device Address MAP BAR values
  63. */
  64. #define MBUS_PCI_MEM_BASE 0xE8000000
  65. #define MBUS_PCI_MEM_SIZE (128 << 20)
  66. #define MBUS_PCI_IO_BASE 0xF1100000
  67. #define MBUS_PCI_IO_SIZE (64 << 10)
  68. #define MBUS_SPI_BASE 0xF4000000
  69. #define MBUS_SPI_SIZE (8 << 20)
  70. #define MBUS_BOOTROM_BASE 0xF8000000
  71. #define MBUS_BOOTROM_SIZE (8 << 20)
  72. struct mbus_win {
  73. u32 base;
  74. u32 size;
  75. u8 target;
  76. u8 attr;
  77. };
  78. /*
  79. * System registers
  80. * Ref: Datasheet sec:A.28
  81. */
  82. struct mvebu_system_registers {
  83. #if defined(CONFIG_ARMADA_375)
  84. u8 pad1[0x54];
  85. #else
  86. u8 pad1[0x60];
  87. #endif
  88. u32 rstoutn_mask; /* 0x60 */
  89. u32 sys_soft_rst; /* 0x64 */
  90. };
  91. /*
  92. * GPIO Registers
  93. * Ref: Datasheet sec:A.19
  94. */
  95. struct kwgpio_registers {
  96. u32 dout;
  97. u32 oe;
  98. u32 blink_en;
  99. u32 din_pol;
  100. u32 din;
  101. u32 irq_cause;
  102. u32 irq_mask;
  103. u32 irq_level;
  104. };
  105. struct sar_freq_modes {
  106. u8 val;
  107. u8 ffc; /* Fabric Frequency Configuration */
  108. u32 p_clk;
  109. u32 nb_clk;
  110. u32 d_clk;
  111. };
  112. /* Needed for dynamic (board-specific) mbus configuration */
  113. extern struct mvebu_mbus_state mbus_state;
  114. /*
  115. * functions
  116. */
  117. unsigned int mvebu_sdram_bar(enum memory_bank bank);
  118. unsigned int mvebu_sdram_bs(enum memory_bank bank);
  119. void mvebu_sdram_size_adjust(enum memory_bank bank);
  120. int mvebu_mbus_probe(struct mbus_win windows[], int count);
  121. int mvebu_soc_family(void);
  122. u32 mvebu_get_nand_clock(void);
  123. void return_to_bootrom(void);
  124. int mv_sdh_init(unsigned long regbase, u32 max_clk, u32 min_clk, u32 quirks);
  125. void get_sar_freq(struct sar_freq_modes *sar_freq);
  126. /*
  127. * Highspeed SERDES PHY config init, ported from bin_hdr
  128. * to mainline U-Boot
  129. */
  130. int serdes_phy_config(void);
  131. /*
  132. * DDR3 init / training code ported from Marvell bin_hdr. Now
  133. * available in mainline U-Boot in:
  134. * drivers/ddr/marvell
  135. */
  136. int ddr3_init(void);
  137. struct mvebu_lcd_info {
  138. u32 fb_base;
  139. int x_res;
  140. int y_res;
  141. int x_fp; /* frontporch */
  142. int y_fp;
  143. int x_bp; /* backporch */
  144. int y_bp;
  145. };
  146. int mvebu_lcd_register_init(struct mvebu_lcd_info *lcd_info);
  147. /*
  148. * get_ref_clk
  149. *
  150. * return: reference clock in MHz (25 or 40)
  151. */
  152. u32 get_ref_clk(void);
  153. #endif /* __ASSEMBLY__ */
  154. #endif /* _MVEBU_CPU_H */