start.S 6.6 KB

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  1. /*
  2. * Startup Code for MIPS32 CPU-core
  3. *
  4. * Copyright (c) 2003 Wolfgang Denk <wd@denx.de>
  5. *
  6. * SPDX-License-Identifier: GPL-2.0+
  7. */
  8. #include <asm-offsets.h>
  9. #include <config.h>
  10. #include <asm/asm.h>
  11. #include <asm/regdef.h>
  12. #include <asm/mipsregs.h>
  13. #ifndef CONFIG_SYS_MIPS_CACHE_MODE
  14. #define CONFIG_SYS_MIPS_CACHE_MODE CONF_CM_CACHABLE_NONCOHERENT
  15. #endif
  16. #ifndef CONFIG_SYS_INIT_SP_ADDR
  17. #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + \
  18. CONFIG_SYS_INIT_SP_OFFSET)
  19. #endif
  20. #ifdef CONFIG_32BIT
  21. # define MIPS_RELOC 3
  22. # define STATUS_SET 0
  23. #endif
  24. #ifdef CONFIG_64BIT
  25. # ifdef CONFIG_SYS_LITTLE_ENDIAN
  26. # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  27. (((r_type) << 24) | ((r_type2) << 16) | ((r_type3) << 8) | (ssym))
  28. # else
  29. # define MIPS64_R_INFO(ssym, r_type3, r_type2, r_type) \
  30. ((r_type) | ((r_type2) << 8) | ((r_type3) << 16) | (ssym) << 24)
  31. # endif
  32. # define MIPS_RELOC MIPS64_R_INFO(0x00, 0x00, 0x12, 0x03)
  33. # define STATUS_SET ST0_KX
  34. #endif
  35. /*
  36. * For the moment disable interrupts, mark the kernel mode and
  37. * set ST0_KX so that the CPU does not spit fire when using
  38. * 64-bit addresses.
  39. */
  40. .macro setup_c0_status set clr
  41. .set push
  42. mfc0 t0, CP0_STATUS
  43. or t0, ST0_CU0 | \set | 0x1f | \clr
  44. xor t0, 0x1f | \clr
  45. mtc0 t0, CP0_STATUS
  46. .set noreorder
  47. sll zero, 3 # ehb
  48. .set pop
  49. .endm
  50. .set noreorder
  51. ENTRY(_start)
  52. /* U-Boot entry point */
  53. b reset
  54. nop
  55. .org 0x10
  56. #if defined(CONFIG_SYS_XWAY_EBU_BOOTCFG)
  57. /*
  58. * Almost all Lantiq XWAY SoC devices have an external bus unit (EBU) to
  59. * access external NOR flashes. If the board boots from NOR flash the
  60. * internal BootROM does a blind read at address 0xB0000010 to read the
  61. * initial configuration for that EBU in order to access the flash
  62. * device with correct parameters. This config option is board-specific.
  63. */
  64. .word CONFIG_SYS_XWAY_EBU_BOOTCFG
  65. .word 0x0
  66. #elif defined(CONFIG_MALTA)
  67. /*
  68. * Linux expects the Board ID here.
  69. */
  70. .word 0x00000420 # 0x420 (Malta Board with CoreLV)
  71. .word 0x00000000
  72. #endif
  73. .org 0x200
  74. /* TLB refill, 32 bit task */
  75. 1: b 1b
  76. nop
  77. .org 0x280
  78. /* XTLB refill, 64 bit task */
  79. 1: b 1b
  80. nop
  81. .org 0x300
  82. /* Cache error exception */
  83. 1: b 1b
  84. nop
  85. .org 0x380
  86. /* General exception */
  87. 1: b 1b
  88. nop
  89. .org 0x400
  90. /* Catch interrupt exceptions */
  91. 1: b 1b
  92. nop
  93. .org 0x480
  94. /* EJTAG debug exception */
  95. 1: b 1b
  96. nop
  97. .align 4
  98. reset:
  99. /* Clear watch registers */
  100. MTC0 zero, CP0_WATCHLO
  101. mtc0 zero, CP0_WATCHHI
  102. /* WP(Watch Pending), SW0/1 should be cleared */
  103. mtc0 zero, CP0_CAUSE
  104. setup_c0_status STATUS_SET 0
  105. /* Init Timer */
  106. mtc0 zero, CP0_COUNT
  107. mtc0 zero, CP0_COMPARE
  108. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  109. /* CONFIG0 register */
  110. li t0, CONF_CM_UNCACHED
  111. mtc0 t0, CP0_CONFIG
  112. #endif
  113. /*
  114. * Initialize $gp, force pointer sized alignment of bal instruction to
  115. * forbid the compiler to put nop's between bal and _gp. This is
  116. * required to keep _gp and ra aligned to 8 byte.
  117. */
  118. .align PTRLOG
  119. bal 1f
  120. nop
  121. PTR _gp
  122. 1:
  123. PTR_L gp, 0(ra)
  124. #ifndef CONFIG_SKIP_LOWLEVEL_INIT
  125. /* Initialize any external memory */
  126. PTR_LA t9, lowlevel_init
  127. jalr t9
  128. nop
  129. /* Initialize caches... */
  130. PTR_LA t9, mips_cache_reset
  131. jalr t9
  132. nop
  133. /* ... and enable them */
  134. li t0, CONFIG_SYS_MIPS_CACHE_MODE
  135. mtc0 t0, CP0_CONFIG
  136. #endif
  137. /* Set up temporary stack */
  138. li t0, -16
  139. PTR_LI t1, CONFIG_SYS_INIT_SP_ADDR
  140. and sp, t1, t0 # force 16 byte alignment
  141. PTR_SUB sp, sp, GD_SIZE # reserve space for gd
  142. and sp, sp, t0 # force 16 byte alignment
  143. move k0, sp # save gd pointer
  144. #ifdef CONFIG_SYS_MALLOC_F_LEN
  145. li t2, CONFIG_SYS_MALLOC_F_LEN
  146. PTR_SUB sp, sp, t2 # reserve space for early malloc
  147. and sp, sp, t0 # force 16 byte alignment
  148. #endif
  149. move fp, sp
  150. /* Clear gd */
  151. move t0, k0
  152. 1:
  153. PTR_S zero, 0(t0)
  154. blt t0, t1, 1b
  155. PTR_ADDI t0, PTRSIZE
  156. #ifdef CONFIG_SYS_MALLOC_F_LEN
  157. PTR_S sp, GD_MALLOC_BASE(k0) # gd->malloc_base offset
  158. #endif
  159. move a0, zero # a0 <-- boot_flags = 0
  160. PTR_LA t9, board_init_f
  161. jr t9
  162. move ra, zero
  163. END(_start)
  164. /*
  165. * void relocate_code (addr_sp, gd, addr_moni)
  166. *
  167. * This "function" does not return, instead it continues in RAM
  168. * after relocating the monitor code.
  169. *
  170. * a0 = addr_sp
  171. * a1 = gd
  172. * a2 = destination address
  173. */
  174. ENTRY(relocate_code)
  175. move sp, a0 # set new stack pointer
  176. move fp, sp
  177. move s0, a1 # save gd in s0
  178. move s2, a2 # save destination address in s2
  179. PTR_LI t0, CONFIG_SYS_MONITOR_BASE
  180. PTR_SUB s1, s2, t0 # s1 <-- relocation offset
  181. PTR_LA t3, in_ram
  182. PTR_L t2, -(3 * PTRSIZE)(t3) # t2 <-- __image_copy_end
  183. move t1, a2
  184. PTR_ADD gp, s1 # adjust gp
  185. /*
  186. * t0 = source address
  187. * t1 = target address
  188. * t2 = source end address
  189. */
  190. 1:
  191. PTR_L t3, 0(t0)
  192. PTR_S t3, 0(t1)
  193. PTR_ADDU t0, PTRSIZE
  194. blt t0, t2, 1b
  195. PTR_ADDU t1, PTRSIZE
  196. /* If caches were enabled, we would have to flush them here. */
  197. PTR_SUB a1, t1, s2 # a1 <-- size
  198. PTR_LA t9, flush_cache
  199. jalr t9
  200. move a0, s2 # a0 <-- destination address
  201. /* Jump to where we've relocated ourselves */
  202. PTR_ADDI t0, s2, in_ram - _start
  203. jr t0
  204. nop
  205. PTR __rel_dyn_end
  206. PTR __rel_dyn_start
  207. PTR __image_copy_end
  208. PTR _GLOBAL_OFFSET_TABLE_
  209. PTR num_got_entries
  210. in_ram:
  211. /*
  212. * Now we want to update GOT.
  213. *
  214. * GOT[0] is reserved. GOT[1] is also reserved for the dynamic object
  215. * generated by GNU ld. Skip these reserved entries from relocation.
  216. */
  217. PTR_L t3, -(1 * PTRSIZE)(t0) # t3 <-- num_got_entries
  218. PTR_L t8, -(2 * PTRSIZE)(t0) # t8 <-- _GLOBAL_OFFSET_TABLE_
  219. PTR_ADD t8, s1 # t8 now holds relocated _G_O_T_
  220. PTR_ADDI t8, t8, 2 * PTRSIZE # skipping first two entries
  221. PTR_LI t2, 2
  222. 1:
  223. PTR_L t1, 0(t8)
  224. beqz t1, 2f
  225. PTR_ADD t1, s1
  226. PTR_S t1, 0(t8)
  227. 2:
  228. PTR_ADDI t2, 1
  229. blt t2, t3, 1b
  230. PTR_ADDI t8, PTRSIZE
  231. /* Update dynamic relocations */
  232. PTR_L t1, -(4 * PTRSIZE)(t0) # t1 <-- __rel_dyn_start
  233. PTR_L t2, -(5 * PTRSIZE)(t0) # t2 <-- __rel_dyn_end
  234. b 2f # skip first reserved entry
  235. PTR_ADDI t1, 2 * PTRSIZE
  236. 1:
  237. lw t8, -4(t1) # t8 <-- relocation info
  238. PTR_LI t3, MIPS_RELOC
  239. bne t8, t3, 2f # skip non-MIPS_RELOC entries
  240. nop
  241. PTR_L t3, -(2 * PTRSIZE)(t1) # t3 <-- location to fix up in FLASH
  242. PTR_L t8, 0(t3) # t8 <-- original pointer
  243. PTR_ADD t8, s1 # t8 <-- adjusted pointer
  244. PTR_ADD t3, s1 # t3 <-- location to fix up in RAM
  245. PTR_S t8, 0(t3)
  246. 2:
  247. blt t1, t2, 1b
  248. PTR_ADDI t1, 2 * PTRSIZE # each rel.dyn entry is 2*PTRSIZE bytes
  249. /*
  250. * Clear BSS
  251. *
  252. * GOT is now relocated. Thus __bss_start and __bss_end can be
  253. * accessed directly via $gp.
  254. */
  255. PTR_LA t1, __bss_start # t1 <-- __bss_start
  256. PTR_LA t2, __bss_end # t2 <-- __bss_end
  257. 1:
  258. PTR_S zero, 0(t1)
  259. blt t1, t2, 1b
  260. PTR_ADDI t1, PTRSIZE
  261. move a0, s0 # a0 <-- gd
  262. move a1, s2
  263. PTR_LA t9, board_init_r
  264. jr t9
  265. move ra, zero
  266. END(relocate_code)