lowlevel_init.S 7.2 KB

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  1. /*
  2. * Copyright (C) 2010 Albert ARIBAUD <albert.u.boot@aribaud.net>
  3. *
  4. * (C) Copyright 2009
  5. * Marvell Semiconductor <www.marvell.com>
  6. * Written-by: Prafulla Wadaskar <prafulla@marvell.com>
  7. *
  8. * SPDX-License-Identifier: GPL-2.0+
  9. */
  10. #include <config.h>
  11. #include "asm/arch/orion5x.h"
  12. /*
  13. * Configuration values for SDRAM access setup
  14. */
  15. #define SDRAM_CONFIG 0x3148400
  16. #define SDRAM_MODE 0x62
  17. #define SDRAM_CONTROL 0x4041000
  18. #define SDRAM_TIME_CTRL_LOW 0x11602220
  19. #define SDRAM_TIME_CTRL_HI 0x40c
  20. #define SDRAM_OPEN_PAGE_EN 0x0
  21. /* DDR 1 2x 32M NANYA NT5DS16M16CS-6K ==> 64MB */
  22. #define SDRAM_BANK0_SIZE 0x3ff0001
  23. #define SDRAM_ADDR_CTRL 0x10
  24. #define SDRAM_OP_NOP 0x05
  25. #define SDRAM_OP_SETMODE 0x03
  26. #define SDRAM_PAD_CTRL_WR_EN 0x80000000
  27. #define SDRAM_PAD_CTRL_TUNE_EN 0x00010000
  28. #define SDRAM_PAD_CTRL_DRVN_MASK 0x0000003f
  29. #define SDRAM_PAD_CTRL_DRVP_MASK 0x00000fc0
  30. /*
  31. * For Guideline MEM-3 - Drive Strength value
  32. */
  33. #define DDR1_PAD_STRENGTH_DEFAULT 0x00001000
  34. #define SDRAM_PAD_CTRL_DRV_STR_MASK 0x00003000
  35. /*
  36. * For Guideline MEM-4 - DQS Reference Delay Tuning
  37. */
  38. #define MSAR_ARMDDRCLCK_MASK 0x000000f0
  39. #define MSAR_ARMDDRCLCK_H_MASK 0x00000100
  40. #define MSAR_ARMDDRCLCK_333_167 0x00000000
  41. #define MSAR_ARMDDRCLCK_500_167 0x00000030
  42. #define MSAR_ARMDDRCLCK_667_167 0x00000060
  43. #define MSAR_ARMDDRCLCK_400_200_1 0x000001E0
  44. #define MSAR_ARMDDRCLCK_400_200 0x00000010
  45. #define MSAR_ARMDDRCLCK_600_200 0x00000050
  46. #define MSAR_ARMDDRCLCK_800_200 0x00000070
  47. #define FTDLL_DDR1_166MHZ 0x0047F001
  48. #define FTDLL_DDR1_200MHZ 0x0044D001
  49. /*
  50. * Low-level init happens right after start.S has switched to SVC32,
  51. * flushed and disabled caches and disabled MMU. We're still running
  52. * from the boot chip select, so the first thing SPL should do is to
  53. * set up the RAM to copy U-Boot into.
  54. */
  55. .globl lowlevel_init
  56. lowlevel_init:
  57. #ifdef CONFIG_SPL_BUILD
  58. /* Use 'r4 as the base for internal register accesses */
  59. ldr r4, =ORION5X_REGS_PHY_BASE
  60. /* move internal registers from the default 0xD0000000
  61. * to their intended location, defined by SoC */
  62. ldr r3, =0xD0000000
  63. add r3, r3, #0x20000
  64. str r4, [r3, #0x80]
  65. /* Use R3 as the base for DRAM registers */
  66. add r3, r4, #0x01000
  67. /*DDR SDRAM Initialization Control */
  68. ldr r6, =0x00000001
  69. str r6, [r3, #0x480]
  70. /* Use R3 as the base for PCI registers */
  71. add r3, r4, #0x31000
  72. /* Disable arbiter */
  73. ldr r6, =0x00000030
  74. str r6, [r3, #0xd00]
  75. /* Use R3 as the base for DRAM registers */
  76. add r3, r4, #0x01000
  77. /* set all dram windows to 0 */
  78. mov r6, #0
  79. str r6, [r3, #0x504]
  80. str r6, [r3, #0x50C]
  81. str r6, [r3, #0x514]
  82. str r6, [r3, #0x51C]
  83. /* 1) Configure SDRAM */
  84. ldr r6, =SDRAM_CONFIG
  85. str r6, [r3, #0x400]
  86. /* 2) Set SDRAM Control reg */
  87. ldr r6, =SDRAM_CONTROL
  88. str r6, [r3, #0x404]
  89. /* 3) Write SDRAM address control register */
  90. ldr r6, =SDRAM_ADDR_CTRL
  91. str r6, [r3, #0x410]
  92. /* 4) Write SDRAM bank 0 size register */
  93. ldr r6, =SDRAM_BANK0_SIZE
  94. str r6, [r3, #0x504]
  95. /* keep other banks disabled */
  96. /* 5) Write SDRAM open pages control register */
  97. ldr r6, =SDRAM_OPEN_PAGE_EN
  98. str r6, [r3, #0x414]
  99. /* 6) Write SDRAM timing Low register */
  100. ldr r6, =SDRAM_TIME_CTRL_LOW
  101. str r6, [r3, #0x408]
  102. /* 7) Write SDRAM timing High register */
  103. ldr r6, =SDRAM_TIME_CTRL_HI
  104. str r6, [r3, #0x40C]
  105. /* 8) Write SDRAM mode register */
  106. /* The CPU must not attempt to change the SDRAM Mode register setting */
  107. /* prior to DRAM controller completion of the DRAM initialization */
  108. /* sequence. To guarantee this restriction, it is recommended that */
  109. /* the CPU sets the SDRAM Operation register to NOP command, performs */
  110. /* read polling until the register is back in Normal operation value, */
  111. /* and then sets SDRAM Mode register to its new value. */
  112. /* 8.1 write 'nop' to SDRAM operation */
  113. ldr r6, =SDRAM_OP_NOP
  114. str r6, [r3, #0x418]
  115. /* 8.2 poll SDRAM operation until back in 'normal' mode. */
  116. 1:
  117. ldr r6, [r3, #0x418]
  118. cmp r6, #0
  119. bne 1b
  120. /* 8.3 Now its safe to write new value to SDRAM Mode register */
  121. ldr r6, =SDRAM_MODE
  122. str r6, [r3, #0x41C]
  123. /* 8.4 Set new mode */
  124. ldr r6, =SDRAM_OP_SETMODE
  125. str r6, [r3, #0x418]
  126. /* 8.5 poll SDRAM operation until back in 'normal' mode. */
  127. 2:
  128. ldr r6, [r3, #0x418]
  129. cmp r6, #0
  130. bne 2b
  131. /* DDR SDRAM Address/Control Pads Calibration */
  132. ldr r6, [r3, #0x4C0]
  133. /* Set Bit [31] to make the register writable */
  134. orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
  135. str r6, [r3, #0x4C0]
  136. bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
  137. bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
  138. bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
  139. bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
  140. /* Get the final N locked value of driving strength [22:17] */
  141. mov r1, r6
  142. mov r1, r1, LSL #9
  143. mov r1, r1, LSR #26 /* r1[5:0]<DrvN> = r3[22:17]<LockN> */
  144. orr r1, r1, r1, LSL #6 /* r1[11:6]<DrvP> = r1[5:0]<DrvN> */
  145. /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
  146. orr r6, r6, r1
  147. str r6, [r3, #0x4C0]
  148. /* DDR SDRAM Data Pads Calibration */
  149. ldr r6, [r3, #0x4C4]
  150. /* Set Bit [31] to make the register writable */
  151. orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
  152. str r6, [r3, #0x4C4]
  153. bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
  154. bic r6, r6, #SDRAM_PAD_CTRL_TUNE_EN
  155. bic r6, r6, #SDRAM_PAD_CTRL_DRVN_MASK
  156. bic r6, r6, #SDRAM_PAD_CTRL_DRVP_MASK
  157. /* Get the final N locked value of driving strength [22:17] */
  158. mov r1, r6
  159. mov r1, r1, LSL #9
  160. mov r1, r1, LSR #26
  161. orr r1, r1, r1, LSL #6 /* r1[5:0] = r3[22:17]<LockN> */
  162. /* Write to both <DrvN> bits [5:0] and <DrvP> bits [11:6] */
  163. orr r6, r6, r1
  164. str r6, [r3, #0x4C4]
  165. /* Implement Guideline (GL# MEM-3) Drive Strength Value */
  166. /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
  167. ldr r1, =DDR1_PAD_STRENGTH_DEFAULT
  168. /* Enable writes to DDR SDRAM Addr/Ctrl Pads Calibration register */
  169. ldr r6, [r3, #0x4C0]
  170. orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
  171. str r6, [r3, #0x4C0]
  172. /* Correct strength and disable writes again */
  173. bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
  174. bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
  175. orr r6, r6, r1
  176. str r6, [r3, #0x4C0]
  177. /* Enable writes to DDR SDRAM Data Pads Calibration register */
  178. ldr r6, [r3, #0x4C4]
  179. orr r6, r6, #SDRAM_PAD_CTRL_WR_EN
  180. str r6, [r3, #0x4C4]
  181. /* Correct strength and disable writes again */
  182. bic r6, r6, #SDRAM_PAD_CTRL_DRV_STR_MASK
  183. bic r6, r6, #SDRAM_PAD_CTRL_WR_EN
  184. orr r6, r6, r1
  185. str r6, [r3, #0x4C4]
  186. /* Implement Guideline (GL# MEM-4) DQS Reference Delay Tuning */
  187. /* Relevant for: 88F5181-A1/B0/B1 and 88F5281-A0/B0 */
  188. /* Get the "sample on reset" register for the DDR frequancy */
  189. ldr r3, =0x10000
  190. ldr r6, [r3, #0x010]
  191. ldr r1, =MSAR_ARMDDRCLCK_MASK
  192. and r1, r6, r1
  193. ldr r6, =FTDLL_DDR1_166MHZ
  194. cmp r1, #MSAR_ARMDDRCLCK_333_167
  195. beq 3f
  196. cmp r1, #MSAR_ARMDDRCLCK_500_167
  197. beq 3f
  198. cmp r1, #MSAR_ARMDDRCLCK_667_167
  199. beq 3f
  200. ldr r6, =FTDLL_DDR1_200MHZ
  201. cmp r1, #MSAR_ARMDDRCLCK_400_200_1
  202. beq 3f
  203. cmp r1, #MSAR_ARMDDRCLCK_400_200
  204. beq 3f
  205. cmp r1, #MSAR_ARMDDRCLCK_600_200
  206. beq 3f
  207. cmp r1, #MSAR_ARMDDRCLCK_800_200
  208. beq 3f
  209. ldr r6, =0
  210. 3:
  211. /* Use R3 as the base for DRAM registers */
  212. add r3, r4, #0x01000
  213. ldr r2, [r3, #0x484]
  214. orr r2, r2, r6
  215. str r2, [r3, #0x484]
  216. /* enable for 2 GB DDR; detection should find out real amount */
  217. sub r6, r6, r6
  218. str r6, [r3, #0x500]
  219. ldr r6, =0x7fff0001
  220. str r6, [r3, #0x504]
  221. #endif /* CONFIG_SPL_BUILD */
  222. /* Return to U-Boot via saved link register */
  223. mov pc, lr