sdram.c 16 KB

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  1. // SPDX-License-Identifier: GPL-2.0
  2. /*
  3. * Copyright (c) 2011 The Chromium OS Authors.
  4. * (C) Copyright 2010,2011
  5. * Graeme Russ, <graeme.russ@gmail.com>
  6. *
  7. * Portions from Coreboot mainboard/google/link/romstage.c
  8. * Copyright (C) 2007-2010 coresystems GmbH
  9. * Copyright (C) 2011 Google Inc.
  10. */
  11. #include <common.h>
  12. #include <dm.h>
  13. #include <errno.h>
  14. #include <fdtdec.h>
  15. #include <init.h>
  16. #include <log.h>
  17. #include <malloc.h>
  18. #include <net.h>
  19. #include <rtc.h>
  20. #include <spi.h>
  21. #include <spi_flash.h>
  22. #include <syscon.h>
  23. #include <sysreset.h>
  24. #include <asm/cpu.h>
  25. #include <asm/processor.h>
  26. #include <asm/gpio.h>
  27. #include <asm/global_data.h>
  28. #include <asm/intel_regs.h>
  29. #include <asm/mrccache.h>
  30. #include <asm/mrc_common.h>
  31. #include <asm/mtrr.h>
  32. #include <asm/pci.h>
  33. #include <asm/report_platform.h>
  34. #include <asm/arch/me.h>
  35. #include <asm/arch/pei_data.h>
  36. #include <asm/arch/pch.h>
  37. #include <asm/post.h>
  38. #include <asm/arch/sandybridge.h>
  39. DECLARE_GLOBAL_DATA_PTR;
  40. #define CMOS_OFFSET_MRC_SEED 152
  41. #define CMOS_OFFSET_MRC_SEED_S3 156
  42. #define CMOS_OFFSET_MRC_SEED_CHK 160
  43. ulong board_get_usable_ram_top(ulong total_size)
  44. {
  45. return mrc_common_board_get_usable_ram_top(total_size);
  46. }
  47. int dram_init_banksize(void)
  48. {
  49. mrc_common_dram_init_banksize();
  50. return 0;
  51. }
  52. static int read_seed_from_cmos(struct pei_data *pei_data)
  53. {
  54. u16 c1, c2, checksum, seed_checksum;
  55. struct udevice *dev;
  56. int ret = 0;
  57. ret = uclass_get_device(UCLASS_RTC, 0, &dev);
  58. if (ret) {
  59. debug("Cannot find RTC: err=%d\n", ret);
  60. return -ENODEV;
  61. }
  62. /*
  63. * Read scrambler seeds from CMOS RAM. We don't want to store them in
  64. * SPI flash since they change on every boot and that would wear down
  65. * the flash too much. So we store these in CMOS and the large MRC
  66. * data in SPI flash.
  67. */
  68. ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED, &pei_data->scrambler_seed);
  69. if (!ret) {
  70. ret = rtc_read32(dev, CMOS_OFFSET_MRC_SEED_S3,
  71. &pei_data->scrambler_seed_s3);
  72. }
  73. if (ret) {
  74. debug("Failed to read from RTC %s\n", dev->name);
  75. return ret;
  76. }
  77. debug("Read scrambler seed 0x%08x from CMOS 0x%02x\n",
  78. pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
  79. debug("Read S3 scrambler seed 0x%08x from CMOS 0x%02x\n",
  80. pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
  81. /* Compute seed checksum and compare */
  82. c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
  83. sizeof(u32));
  84. c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
  85. sizeof(u32));
  86. checksum = add_ip_checksums(sizeof(u32), c1, c2);
  87. seed_checksum = rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK);
  88. seed_checksum |= rtc_read8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1) << 8;
  89. if (checksum != seed_checksum) {
  90. debug("%s: invalid seed checksum\n", __func__);
  91. pei_data->scrambler_seed = 0;
  92. pei_data->scrambler_seed_s3 = 0;
  93. return -EINVAL;
  94. }
  95. return 0;
  96. }
  97. static int prepare_mrc_cache(struct pei_data *pei_data)
  98. {
  99. struct mrc_data_container *mrc_cache;
  100. struct mrc_region entry;
  101. int ret;
  102. ret = read_seed_from_cmos(pei_data);
  103. if (ret)
  104. return ret;
  105. ret = mrccache_get_region(MRC_TYPE_NORMAL, NULL, &entry);
  106. if (ret)
  107. return ret;
  108. mrc_cache = mrccache_find_current(&entry);
  109. if (!mrc_cache)
  110. return -ENOENT;
  111. pei_data->mrc_input = mrc_cache->data;
  112. pei_data->mrc_input_len = mrc_cache->data_size;
  113. debug("%s: at %p, size %x checksum %04x\n", __func__,
  114. pei_data->mrc_input, pei_data->mrc_input_len,
  115. mrc_cache->checksum);
  116. return 0;
  117. }
  118. static int write_seeds_to_cmos(struct pei_data *pei_data)
  119. {
  120. u16 c1, c2, checksum;
  121. struct udevice *dev;
  122. int ret = 0;
  123. ret = uclass_get_device(UCLASS_RTC, 0, &dev);
  124. if (ret) {
  125. debug("Cannot find RTC: err=%d\n", ret);
  126. return -ENODEV;
  127. }
  128. /* Save the MRC seed values to CMOS */
  129. rtc_write32(dev, CMOS_OFFSET_MRC_SEED, pei_data->scrambler_seed);
  130. debug("Save scrambler seed 0x%08x to CMOS 0x%02x\n",
  131. pei_data->scrambler_seed, CMOS_OFFSET_MRC_SEED);
  132. rtc_write32(dev, CMOS_OFFSET_MRC_SEED_S3, pei_data->scrambler_seed_s3);
  133. debug("Save s3 scrambler seed 0x%08x to CMOS 0x%02x\n",
  134. pei_data->scrambler_seed_s3, CMOS_OFFSET_MRC_SEED_S3);
  135. /* Save a simple checksum of the seed values */
  136. c1 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed,
  137. sizeof(u32));
  138. c2 = compute_ip_checksum((u8 *)&pei_data->scrambler_seed_s3,
  139. sizeof(u32));
  140. checksum = add_ip_checksums(sizeof(u32), c1, c2);
  141. rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK, checksum & 0xff);
  142. rtc_write8(dev, CMOS_OFFSET_MRC_SEED_CHK + 1, (checksum >> 8) & 0xff);
  143. return 0;
  144. }
  145. /* Use this hook to save our SDRAM parameters */
  146. int misc_init_r(void)
  147. {
  148. int ret;
  149. ret = mrccache_save();
  150. if (ret)
  151. printf("Unable to save MRC data: %d\n", ret);
  152. return 0;
  153. }
  154. static void post_system_agent_init(struct udevice *dev, struct udevice *me_dev,
  155. struct pei_data *pei_data)
  156. {
  157. uint16_t done;
  158. /*
  159. * Send ME init done for SandyBridge here. This is done inside the
  160. * SystemAgent binary on IvyBridge
  161. */
  162. dm_pci_read_config16(dev, PCI_DEVICE_ID, &done);
  163. done &= BASE_REV_MASK;
  164. if (BASE_REV_SNB == done)
  165. intel_early_me_init_done(dev, me_dev, ME_INIT_STATUS_SUCCESS);
  166. else
  167. intel_me_status(me_dev);
  168. /* If PCIe init is skipped, set the PEG clock gating */
  169. if (!pei_data->pcie_init)
  170. setbits_le32(MCHBAR_REG(0x7010), 1);
  171. }
  172. static int recovery_mode_enabled(void)
  173. {
  174. return false;
  175. }
  176. static int copy_spd(struct udevice *dev, struct pei_data *peid)
  177. {
  178. const void *data;
  179. int ret;
  180. ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data);
  181. if (ret) {
  182. debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret);
  183. return ret;
  184. }
  185. memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));
  186. return 0;
  187. }
  188. /**
  189. * sdram_find() - Find available memory
  190. *
  191. * This is a bit complicated since on x86 there are system memory holes all
  192. * over the place. We create a list of available memory blocks
  193. *
  194. * @dev: Northbridge device
  195. */
  196. static int sdram_find(struct udevice *dev)
  197. {
  198. struct memory_info *info = &gd->arch.meminfo;
  199. uint32_t tseg_base, uma_size, tolud;
  200. uint64_t tom, me_base, touud;
  201. uint64_t uma_memory_base = 0;
  202. unsigned long long tomk;
  203. uint16_t ggc;
  204. u32 val;
  205. /* Total Memory 2GB example:
  206. *
  207. * 00000000 0000MB-1992MB 1992MB RAM (writeback)
  208. * 7c800000 1992MB-2000MB 8MB TSEG (SMRR)
  209. * 7d000000 2000MB-2002MB 2MB GFX GTT (uncached)
  210. * 7d200000 2002MB-2034MB 32MB GFX UMA (uncached)
  211. * 7f200000 2034MB TOLUD
  212. * 7f800000 2040MB MEBASE
  213. * 7f800000 2040MB-2048MB 8MB ME UMA (uncached)
  214. * 80000000 2048MB TOM
  215. * 100000000 4096MB-4102MB 6MB RAM (writeback)
  216. *
  217. * Total Memory 4GB example:
  218. *
  219. * 00000000 0000MB-2768MB 2768MB RAM (writeback)
  220. * ad000000 2768MB-2776MB 8MB TSEG (SMRR)
  221. * ad800000 2776MB-2778MB 2MB GFX GTT (uncached)
  222. * ada00000 2778MB-2810MB 32MB GFX UMA (uncached)
  223. * afa00000 2810MB TOLUD
  224. * ff800000 4088MB MEBASE
  225. * ff800000 4088MB-4096MB 8MB ME UMA (uncached)
  226. * 100000000 4096MB TOM
  227. * 100000000 4096MB-5374MB 1278MB RAM (writeback)
  228. * 14fe00000 5368MB TOUUD
  229. */
  230. /* Top of Upper Usable DRAM, including remap */
  231. dm_pci_read_config32(dev, TOUUD + 4, &val);
  232. touud = (uint64_t)val << 32;
  233. dm_pci_read_config32(dev, TOUUD, &val);
  234. touud |= val;
  235. /* Top of Lower Usable DRAM */
  236. dm_pci_read_config32(dev, TOLUD, &tolud);
  237. /* Top of Memory - does not account for any UMA */
  238. dm_pci_read_config32(dev, 0xa4, &val);
  239. tom = (uint64_t)val << 32;
  240. dm_pci_read_config32(dev, 0xa0, &val);
  241. tom |= val;
  242. debug("TOUUD %llx TOLUD %08x TOM %llx\n", touud, tolud, tom);
  243. /* ME UMA needs excluding if total memory <4GB */
  244. dm_pci_read_config32(dev, 0x74, &val);
  245. me_base = (uint64_t)val << 32;
  246. dm_pci_read_config32(dev, 0x70, &val);
  247. me_base |= val;
  248. debug("MEBASE %llx\n", me_base);
  249. /* TODO: Get rid of all this shifting by 10 bits */
  250. tomk = tolud >> 10;
  251. if (me_base == tolud) {
  252. /* ME is from MEBASE-TOM */
  253. uma_size = (tom - me_base) >> 10;
  254. /* Increment TOLUD to account for ME as RAM */
  255. tolud += uma_size << 10;
  256. /* UMA starts at old TOLUD */
  257. uma_memory_base = tomk * 1024ULL;
  258. debug("ME UMA base %llx size %uM\n", me_base, uma_size >> 10);
  259. }
  260. /* Graphics memory comes next */
  261. dm_pci_read_config16(dev, GGC, &ggc);
  262. if (!(ggc & 2)) {
  263. debug("IGD decoded, subtracting ");
  264. /* Graphics memory */
  265. uma_size = ((ggc >> 3) & 0x1f) * 32 * 1024ULL;
  266. debug("%uM UMA", uma_size >> 10);
  267. tomk -= uma_size;
  268. uma_memory_base = tomk * 1024ULL;
  269. /* GTT Graphics Stolen Memory Size (GGMS) */
  270. uma_size = ((ggc >> 8) & 0x3) * 1024ULL;
  271. tomk -= uma_size;
  272. uma_memory_base = tomk * 1024ULL;
  273. debug(" and %uM GTT\n", uma_size >> 10);
  274. }
  275. /* Calculate TSEG size from its base which must be below GTT */
  276. dm_pci_read_config32(dev, 0xb8, &tseg_base);
  277. uma_size = (uma_memory_base - tseg_base) >> 10;
  278. tomk -= uma_size;
  279. uma_memory_base = tomk * 1024ULL;
  280. debug("TSEG base 0x%08x size %uM\n", tseg_base, uma_size >> 10);
  281. debug("Available memory below 4GB: %lluM\n", tomk >> 10);
  282. /* Report the memory regions */
  283. mrc_add_memory_area(info, 1 << 20, 2 << 28);
  284. mrc_add_memory_area(info, (2 << 28) + (2 << 20), 4 << 28);
  285. mrc_add_memory_area(info, (4 << 28) + (2 << 20), tseg_base);
  286. mrc_add_memory_area(info, 1ULL << 32, touud);
  287. /* Add MTRRs for memory */
  288. mtrr_add_request(MTRR_TYPE_WRBACK, 0, 2ULL << 30);
  289. mtrr_add_request(MTRR_TYPE_WRBACK, 2ULL << 30, 512 << 20);
  290. mtrr_add_request(MTRR_TYPE_WRBACK, 0xaULL << 28, 256 << 20);
  291. mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base, 16 << 20);
  292. mtrr_add_request(MTRR_TYPE_UNCACHEABLE, tseg_base + (16 << 20),
  293. 32 << 20);
  294. /*
  295. * If >= 4GB installed then memory from TOLUD to 4GB
  296. * is remapped above TOM, TOUUD will account for both
  297. */
  298. if (touud > (1ULL << 32ULL)) {
  299. debug("Available memory above 4GB: %lluM\n",
  300. (touud >> 20) - 4096);
  301. }
  302. return 0;
  303. }
  304. static void rcba_config(void)
  305. {
  306. /*
  307. * GFX INTA -> PIRQA (MSI)
  308. * D28IP_P3IP WLAN INTA -> PIRQB
  309. * D29IP_E1P EHCI1 INTA -> PIRQD
  310. * D26IP_E2P EHCI2 INTA -> PIRQF
  311. * D31IP_SIP SATA INTA -> PIRQF (MSI)
  312. * D31IP_SMIP SMBUS INTB -> PIRQH
  313. * D31IP_TTIP THRT INTC -> PIRQA
  314. * D27IP_ZIP HDA INTA -> PIRQA (MSI)
  315. *
  316. * TRACKPAD -> PIRQE (Edge Triggered)
  317. * TOUCHSCREEN -> PIRQG (Edge Triggered)
  318. */
  319. /* Device interrupt pin register (board specific) */
  320. writel((INTC << D31IP_TTIP) | (NOINT << D31IP_SIP2) |
  321. (INTB << D31IP_SMIP) | (INTA << D31IP_SIP), RCB_REG(D31IP));
  322. writel(NOINT << D30IP_PIP, RCB_REG(D30IP));
  323. writel(INTA << D29IP_E1P, RCB_REG(D29IP));
  324. writel(INTA << D28IP_P3IP, RCB_REG(D28IP));
  325. writel(INTA << D27IP_ZIP, RCB_REG(D27IP));
  326. writel(INTA << D26IP_E2P, RCB_REG(D26IP));
  327. writel(NOINT << D25IP_LIP, RCB_REG(D25IP));
  328. writel(NOINT << D22IP_MEI1IP, RCB_REG(D22IP));
  329. /* Device interrupt route registers */
  330. writel(DIR_ROUTE(PIRQB, PIRQH, PIRQA, PIRQC), RCB_REG(D31IR));
  331. writel(DIR_ROUTE(PIRQD, PIRQE, PIRQF, PIRQG), RCB_REG(D29IR));
  332. writel(DIR_ROUTE(PIRQB, PIRQC, PIRQD, PIRQE), RCB_REG(D28IR));
  333. writel(DIR_ROUTE(PIRQA, PIRQH, PIRQA, PIRQB), RCB_REG(D27IR));
  334. writel(DIR_ROUTE(PIRQF, PIRQE, PIRQG, PIRQH), RCB_REG(D26IR));
  335. writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D25IR));
  336. writel(DIR_ROUTE(PIRQA, PIRQB, PIRQC, PIRQD), RCB_REG(D22IR));
  337. /* Enable IOAPIC (generic) */
  338. writew(0x0100, RCB_REG(OIC));
  339. /* PCH BWG says to read back the IOAPIC enable register */
  340. (void)readw(RCB_REG(OIC));
  341. /* Disable unused devices (board specific) */
  342. setbits_le32(RCB_REG(FD), PCH_DISABLE_ALWAYS);
  343. }
  344. int dram_init(void)
  345. {
  346. struct pei_data _pei_data __aligned(8) = {
  347. .pei_version = PEI_VERSION,
  348. .mchbar = MCH_BASE_ADDRESS,
  349. .dmibar = DEFAULT_DMIBAR,
  350. .epbar = DEFAULT_EPBAR,
  351. .pciexbar = CONFIG_PCIE_ECAM_BASE,
  352. .smbusbar = SMBUS_IO_BASE,
  353. .wdbbar = 0x4000000,
  354. .wdbsize = 0x1000,
  355. .hpet_address = CONFIG_HPET_ADDRESS,
  356. .rcba = DEFAULT_RCBABASE,
  357. .pmbase = DEFAULT_PMBASE,
  358. .gpiobase = DEFAULT_GPIOBASE,
  359. .thermalbase = 0xfed08000,
  360. .system_type = 0, /* 0 Mobile, 1 Desktop/Server */
  361. .tseg_size = CONFIG_SMM_TSEG_SIZE,
  362. .ts_addresses = { 0x00, 0x00, 0x00, 0x00 },
  363. .ec_present = 1,
  364. .ddr3lv_support = 1,
  365. /*
  366. * 0 = leave channel enabled
  367. * 1 = disable dimm 0 on channel
  368. * 2 = disable dimm 1 on channel
  369. * 3 = disable dimm 0+1 on channel
  370. */
  371. .dimm_channel0_disabled = 2,
  372. .dimm_channel1_disabled = 2,
  373. .max_ddr3_freq = 1600,
  374. .usb_port_config = {
  375. /*
  376. * Empty and onboard Ports 0-7, set to un-used pin
  377. * OC3
  378. */
  379. { 0, 3, 0x0000 }, /* P0= Empty */
  380. { 1, 0, 0x0040 }, /* P1= Left USB 1 (OC0) */
  381. { 1, 1, 0x0040 }, /* P2= Left USB 2 (OC1) */
  382. { 1, 3, 0x0040 }, /* P3= SDCARD (no OC) */
  383. { 0, 3, 0x0000 }, /* P4= Empty */
  384. { 1, 3, 0x0040 }, /* P5= WWAN (no OC) */
  385. { 0, 3, 0x0000 }, /* P6= Empty */
  386. { 0, 3, 0x0000 }, /* P7= Empty */
  387. /*
  388. * Empty and onboard Ports 8-13, set to un-used pin
  389. * OC4
  390. */
  391. { 1, 4, 0x0040 }, /* P8= Camera (no OC) */
  392. { 1, 4, 0x0040 }, /* P9= Bluetooth (no OC) */
  393. { 0, 4, 0x0000 }, /* P10= Empty */
  394. { 0, 4, 0x0000 }, /* P11= Empty */
  395. { 0, 4, 0x0000 }, /* P12= Empty */
  396. { 0, 4, 0x0000 }, /* P13= Empty */
  397. },
  398. };
  399. struct pei_data *pei_data = &_pei_data;
  400. struct udevice *dev, *me_dev;
  401. int ret;
  402. /* We need the pinctrl set up early */
  403. ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev);
  404. if (ret) {
  405. debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret);
  406. return ret;
  407. }
  408. ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev);
  409. if (ret) {
  410. debug("%s: Could not get northbridge (ret=%d)\n", __func__,
  411. ret);
  412. return ret;
  413. }
  414. ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev);
  415. if (ret) {
  416. debug("%s: Could not get ME (ret=%d)\n", __func__, ret);
  417. return ret;
  418. }
  419. ret = copy_spd(dev, pei_data);
  420. if (ret) {
  421. debug("%s: Could not get SPD (ret=%d)\n", __func__, ret);
  422. return ret;
  423. }
  424. pei_data->boot_mode = gd->arch.pei_boot_mode;
  425. debug("Boot mode %d\n", gd->arch.pei_boot_mode);
  426. debug("mrc_input %p\n", pei_data->mrc_input);
  427. /*
  428. * Do not pass MRC data in for recovery mode boot,
  429. * Always pass it in for S3 resume.
  430. */
  431. if (!recovery_mode_enabled() ||
  432. pei_data->boot_mode == PEI_BOOT_RESUME) {
  433. ret = prepare_mrc_cache(pei_data);
  434. if (ret)
  435. debug("prepare_mrc_cache failed: %d\n", ret);
  436. }
  437. /* If MRC data is not found we cannot continue S3 resume. */
  438. if (pei_data->boot_mode == PEI_BOOT_RESUME && !pei_data->mrc_input) {
  439. debug("Giving up in sdram_initialize: No MRC data\n");
  440. sysreset_walk_halt(SYSRESET_COLD);
  441. }
  442. /* Pass console handler in pei_data */
  443. pei_data->tx_byte = sdram_console_tx_byte;
  444. /* Wait for ME to be ready */
  445. ret = intel_early_me_init(me_dev);
  446. if (ret) {
  447. debug("%s: Could not init ME (ret=%d)\n", __func__, ret);
  448. return ret;
  449. }
  450. ret = intel_early_me_uma_size(me_dev);
  451. if (ret < 0) {
  452. debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret);
  453. return ret;
  454. }
  455. ret = mrc_common_init(dev, pei_data, false);
  456. if (ret) {
  457. debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret);
  458. return ret;
  459. }
  460. ret = sdram_find(dev);
  461. if (ret) {
  462. debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret);
  463. return ret;
  464. }
  465. gd->ram_size = gd->arch.meminfo.total_32bit_memory;
  466. debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,
  467. pei_data->mrc_output);
  468. post_system_agent_init(dev, me_dev, pei_data);
  469. report_memory_config();
  470. /* S3 resume: don't save scrambler seed or MRC data */
  471. if (pei_data->boot_mode != PEI_BOOT_RESUME) {
  472. struct mrc_output *mrc = &gd->arch.mrc[MRC_TYPE_NORMAL];
  473. /*
  474. * This will be copied to SDRAM in reserve_arch(), then written
  475. * to SPI flash in mrccache_save()
  476. */
  477. mrc->buf = (char *)pei_data->mrc_output;
  478. mrc->len = pei_data->mrc_output_len;
  479. ret = write_seeds_to_cmos(pei_data);
  480. if (ret)
  481. debug("Failed to write seeds to CMOS: %d\n", ret);
  482. }
  483. writew(0xCAFE, MCHBAR_REG(SSKPD));
  484. if (ret)
  485. return ret;
  486. rcba_config();
  487. return 0;
  488. }